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Experiment: Design of Synchronous and Asynchronous Counters Design of Mod-5 Synchronous Counter

The document describes experiments conducted on designing synchronous and asynchronous counters. It provides the components, theory, truth tables and circuit diagrams for a mod-5 synchronous counter, a mod-6 asynchronous counter, and a decade counter that counts from 0 to 9 seconds using a timer circuit. Procedures for each experiment include writing truth tables, drawing circuit diagrams using logic gates and flip-flops, building the circuits on a breadboard, and verifying the results.

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Vrushali patil
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192 views3 pages

Experiment: Design of Synchronous and Asynchronous Counters Design of Mod-5 Synchronous Counter

The document describes experiments conducted on designing synchronous and asynchronous counters. It provides the components, theory, truth tables and circuit diagrams for a mod-5 synchronous counter, a mod-6 asynchronous counter, and a decade counter that counts from 0 to 9 seconds using a timer circuit. Procedures for each experiment include writing truth tables, drawing circuit diagrams using logic gates and flip-flops, building the circuits on a breadboard, and verifying the results.

Uploaded by

Vrushali patil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Kathmandu University

Department of Electrical and Electronics Engineering


Digital logic laboratory experiments

Experiment: Design of synchronous and asynchronous counters


Design of mod-5 synchronous counter
Components Required:
 T flip flop
 IC 7432
 IC 7408
Theory:
Common clock pulse is applied to all flip flops and the output changes simultaneously.
Procedure:
 Truth table was written.
 Circuit diagram was drawn using appropriate logic gates and T flipflop.
 Then circuit was connected in breadboard.
 And finally verified the result.
Truth table:
Present state Next state
Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 0 0 0 1 0 0
 Solving the truth table using k- map for T2, T1 and T0 we get,
 T2=Q2+Q1.Q0, T1=Q2’.Q0+Q2.Q1, T0=Q2’+Q0
Here, Q2=MSB, Q0=LSB
Circuit diagram of mod-5 synchronous counter:
U9A U3A

7432N 7408N
U7A
U0 U1 7432N U2
SET SET SET
T Q T Q T Q

CLK ~Q CLK ~Q CLK ~Q


RESET RESET RESET

T_FF T_FF T_FF

U8A U4A
7432N
U5A
7408N

7408N

Design of mod-6 asynchronous counter


Components Required:
 T flip flop
 IC 7408
 IC 7404
Theory:
Different clock pulse is applied to different flip flops and the output changes as input changes.
Procedure:
 Truth table was written.
 Circuit diagram was drawn using appropriate logic gates and T flipflop.
 Then circuit was connected in breadboard.
 And finally verified the result.
Truth table:
Q2 Q1 Q0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0 0 0
Here, Q2=MSB, Q0=LSB
Circuit Diagram of mod-6 asynchronous counter:

U0 U1 U2
SET SET SET
T Q T Q T Q

CLK ~Q CLK ~Q CLK ~Q


RESET RESET RESET

T_FF T_FF T_FF


U5A

7408J
U3A
U4A

7408J
7404N

Decade counter using timer circuit (counts 0 to 9 seconds)

CA
U4
555_TIMER_RATED
U3
VCC
A B C D E F G
RST OUT
R1
DIS
R2 U2 U1
1000Ω THR

TRI 15 A QA 3 7 A OA 13
V1 1000Ω 1 B QB 2 1 B OB 12
CON 10 C QC 6 2 C OC 11
5V 9 7 6 10
D QD D OD
GND OE 9
C1 C2 4 ~CTEN 3 ~LT OF 15
11 ~LOAD 5 ~RBI OG 14
10µF 0.01µF 5 ~U/D ~RCO 13 4 ~BI/RBO
MAX/MIN 12
14 CLK
7447N
74190N V2
5V

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