ARM Processor Fundamentals

ARM Core data flow model

ARM core is functional units connected by data
buses (Figure 1), where, the arrows represent the
flow of data, the lines represent the buses, and the
boxes represent either an operation unit or a
storage area.
The figure shows not only the flow of data but also
the abstract components that make up an ARM
core.
Data enters the processor core through the Data
bus
Data may be an instruction to execute or a data item
Von Neumann implementation of the ARM-data
items and instructions share the same bus (Figure 1)
In contrast, Harvard implementations of the ARM
use two different buses
The instruction decoder translates instructions before they are executed.
Each instruction executed belongs to a particular instruction set.
 ARM Core data flow model
ARM processor uses a load-store
architecture
 load instructions - copy data from
memory to registers in the core
 store instructions - copy data from
registers to memory.
 No data processing instructions that
directly manipulate data in memory
Data processing is carried out solely in
registers
Data items are placed in the register file—a
storage bank made up of 32-bit registers
ARM core is a 32-bit processor, most
instructions treat the registers as holding
signed or unsigned 32-bit values
Sign extend hardware converts signed 8-
bit/16-bit numbers to 32-bit values as they
are read from memory and placed in a
register
 ARM Core data flow model
ARM instructions have two source registers, Rn
and Rm, and a single result or destination
register, Rd
Source operands are read from the register file
using the internal buses A and B, respectively
ALU (arithmetic logic unit) or MAC (multiply-
accumulate unit) takes the register values Rn
and Rm from the A and B buses and computes a
result
Data processing instructions write the result in
Rd directly to the register file
Load and store instructions use the ALU to
generate an address to be held in the address
register and broadcast on the Address bus
One important feature of the ARM is that
register Rm alternatively can be preprocessed in
the barrel shifter before it enters the ALU
Together the barrel shifter and ALU can calculate
a wide range of expressions and addresses.
 ARM Core data flow model
After passing through the functional
units, the result in Rd is written back
to the register file using the Result
bus
For load and store instructions the
incrementer updates the address
register before the core reads or
writes the next register value from
or to the next sequential memory
location
The processor continues executing
instructions until an exception or
interrupt changes the normal
execution flow.
 ARM Register Set
General purpose registers
 General purpose registers hold either data or
an address
 Identified with the letter r prefixed to the
register number - example, register 4 is given
the r4.
 The processor can operate in seven different
modes
 All the registers shown are 32 bits in size
 18 active registers: 16 data registers and 2
processor status registers
 Data registers are visible to the programmer
as r0 to r15
 ARM Register Set
r0 - r12 are general purpose registers /‘scratch
pad’ registers
o These are the registers into which data and
address are loaded
o They are also the registers used in
computations.
Shaded registers identify the assigned special-
purpose registers:
 r13 – stack pointer (sp) and stores the head of
the stack in the current processor mode
 r14 - link register (lr) and is where the core puts
the return address whenever it calls a
subroutine
 r15 - program counter (pc) and contains the
address of the next instruction to be fetched by
the processor.
 ARM Register Set
During branch the value of PC is saved in the
link register, and PC takes on a new branch
address
When returning to the original sequence, the
PC value can be retrieved from the link register
No need to push the PC value onto the stack
Storing return address in LR helps to reduce the
delay associated with procedure calls and
interrupts
In ARM state the registers r0 to r13 are
orthogonal—any instruction that you can apply
to r0 you can equally well apply to any of the
other registers
However, there are instructions that treat r14
and r15 in a special way.
 ARM Register Set
Two program status registers:
o cpsr (current program status register)
o spsr (saved program status register)
The register file contains all the registers
available to a programmer
Which registers are visible to the
programmer depend upon the current mode
of the processor.
 ARM Register Set
CPSR (Current Program Status Register)
– To monitor and control internal operations
– Dedicated 32-bit register and resides in the register file
– Divided into four fields, each 8 bits wide:
o Flags
o Status
o Extension
o control
– Flags field - condition flags
– Status and Extension fields - reserved for future use
– Control field - the processor mode, state, and interrupt
mask bits.
 CPSR

Some ARM processor cores have extra bits allocated. For

example, the J bit, which can be found in the flags field, is
only available on Jazelle-enabled processors, which
execute 8-bit instructions.
 Processor modes
Processor mode determines which registers are active and the
access rights to the cpsr register itself
Processor modes –
o Privileged mode - allows full read-write access to the cpsr
o Non-privileged mode - only allows read access to the
control field in the cpsr but still allows read-write access to
the condition flags
Seven processor modes
 six privileged modes (abort, fast interrupt request, interrupt
request, supervisor, system, and undefined)
 One non-privileged mode (user).
 Processor modes
Abort mode – enters when there is a failed attempt to access
memory
Fast interrupt request and interrupt request modes -
correspond to the two interrupt levels available on the ARM
processor
Supervisor mode - mode that the processor is in after reset
and is generally the mode that an operating system kernel
operates in
System mode - special version of user mode that allows full
read-write access to the cpsr
Undefined mode - used when the processor encounters an
instruction that is undefined or not supported by the
implementation
User mode - used for programs and applications.
 Banked Registers
37 registers in the register file
20 registers are hidden from a
program at different times are
called banked registers
They are available only when
the processor is in a particular
mode
For example, abort mode has
banked registers r13_abt,
r14_abt and spsr_abt.
Banked registers of a
particular mode are denoted
by an underline character
post-fixed to the mode
mnemonic or _mode.
 Banked Registers
Every processor mode except user mode can change mode by
writing directly to the mode bits of the cpsr
All processor modes except system mode have a set of
associated banked registers that are a subset of the main 16
registers
If you change processor mode, a banked register from the new
mode will replace an existing register
For example, when the processor is in the interrupt request
mode, the instructions you execute still access registers named
r13 and r14. However, these registers are the banked registers
r13_irq and r14_irq
user mode registers r13_usr and r14_usr are not affected by the
instruction referencing these registers
A program still has normal access to the other registers r0 to r12
 Changing the Processor Mode
Processor mode can be changed by a program that writes
directly to the cpsr (the processor core has to be in privileged
mode) or by hardware when the core responds to an exception
or interrupt
The following exceptions and interrupts cause a mode change:
 Reset
 interrupt request
 fast interrupt request
 software interrupt
 data abort
 prefetch abort
 undefined instruction
Exceptions and interrupts suspend the normal execution of
sequential instructions and jump to a specific location
 Changing the Processor mode
Figure shows the core changing from user mode
to interrupt request mode, which happens when
an interrupt request occurs due to an external
device raising an interrupt to the processor core
This change causes user registers r13 and r14 to
be banked
The user registers are replaced with registers
r13_irq and r14_irq, respectively
r14_irq - return address
r13_irq - stack pointer for interrupt request mode
spsr:
can only be modified and read in a
privileged mode
store previous modes’s cpsr
not available in user mode.
 Changing the Processor mode
Important feature - cpsr is not copied into the spsr when a mode
change is forced due to a program writing directly to the cpsr
Saving of the cpsr only occurs when an exception or interrupt is
raised
When power is applied to the core, it starts in supervisor mode,
which is privileged
Starting in a privileged mode is useful since initialization code can
use full access to the cpsr to set up the stacks for each of the other
modes.
Processor modes and Banked Registers
 State and Instruction Sets
State of the core determines which instruction set is being executed.
Three instruction sets: ARM, Thumb, and Jazelle
o ARM instruction set: only active when the processor is in ARM state
o Thumb instruction set: only active when the processor is in Thumb state
Cannot intermingle sequential ARM, Thumb, and Jazelle instructions
The Jazelle J and Thumb T bits in the cpsr reflect the state of the
processor
J = T = 0, the processor is in ARM state
o This is the case when power is applied to the processor
T = 1, then the processor is in Thumb state
ARM designers introduced a third instruction set called Jazelle
Jazelle executes 8-bit instructions and is a hybrid mix of software and
hardware designed to speed up the execution of Java bytecodes
State and Instruction Sets
 Interrupt Masks
Interrupt masks are used to stop specific interrupt requests
from interrupting the processor
There are two interrupt request levels available on the ARM
processor core:
1. Interrupt request (IRQ)
2. fast interrupt request (FIQ)
The cpsr has two interrupt mask bits, 7 and 6 (or I and F), which
control the masking of IRQ and FIQ, respectively
I bit masks IRQ when set to binary 1
F bit masks FIQ when set to binary 1
Condition Flags
 Conditional Execution
Prior to execution, the processor compares the condition attribute
with the condition flags in the cpsr. If they match, then the
instruction is executed; otherwise the instruction is ignored
Exceptions, Interrupts, and the Vector Table
When an exception or interrupt occurs, the processor sets the pc to a
specific memory address
Address is within a special address range called the vector table
The entries in the vector table are instructions that branch to specific
routines designed to handle a particular exception or interrupt
 Reset vector: when power is applied
 Undefined instruction vector: used when the processor cannot decode an
instruction
 Software interrupt vector: called when you execute a SWI instruction
 Prefetch abort vector: occurs when the processor attempts to fetch an
instruction from an address without the correct access permission
 Data abort vector: raised when an instruction attempts to access data
memory without the correct access permissions
 Interrupt request vector: used by external hardware to interrupt the
normal execution flow of the processor
 Fast interrupt request vector: reserved for hardware requiring faster
response times
Exceptions, Interrupts, and the Vector Table
 PIPELINE
A pipeline is the mechanism a RISC processor uses to
execute instructions.
Using a pipeline speeds up execution by fetching the
next instruction while other instructions are being
decoded and executed.
One way to view the pipeline is to think of it as an
automobile assembly line, with each stage carrying out
a particular task to manufacture the vehicle.
 PIPELINE
ARM7 three-stage pipelining

 Fetch: loads an instruction from memory.

 Decode: identifies the instruction to be executed.
 Execute: processes the instruction and writes the result back to
a register
 PIPELINE
 Each instruction takes a single cycle to complete after the pipeline is filled.
 The three instructions are placed into the pipeline sequentially.
 First cycle - core fetches the ADD instruction from memory.
 Second cycle - core fetches the SUB instruction and decodes the ADD
instruction.
 Third cycle - both the SUB and ADD instructions are moved along the
pipeline.
 The ADD instruction is executed, the SUB instruction is decoded, and the
CMP instruction is fetched. This procedure is called filling the pipeline.
 The pipeline allows the core to execute an instruction every cycle.
 PIPELINE

 As the pipeline length increases, the amount of work done at each

stage is reduced
 This in turn increases the performance.
 The system latency also increases because it takes more cycles to fill the
pipeline before the core can execute an instruction.
 The increased pipeline length also means there can be data
dependency between certain stages.
 reduce this dependency by using instruction scheduling
 3 stage Pipelining ARM organization
 The organisation of ARM with a 3-stage pipeline illustrates following:
 Register bank
o which stores the processor state
o It has two read ports and one write port which can each be used to
access any register, plus an additional read port and an additional
write port that give special access to r15, the program counter.
o Additional write port on r15 allows it to be updated as the instruction
fetch address is incremented and the read port allows instruction fetch
to resume after a data address has been issued.
o Barrel shifter - which can shift or rotate one operand by any number
of bits.
o ALU - which performs the arithmetic and logic functions required by
the instruction set
o Address register and incrementer - which select and hold all memory
addresses and generate sequential addresses when required
o Data registers - which hold data passing to and from memory
o Instruction decoder and associated control logic
3 stage Pipelining ARM organization
• In a single-cycle data processing
instruction, two register
operands are accessed, the
value on the B bus is shifted and
combined with the value on the
A bus in the ALU, then the result
is written back into the register
bank
• Program counter value is in the
address register, from where it is
fed into the incrementer, then
the incremented value is copied
back into rl5 in the register bank
and also into the address
register to be used as the
address for the next instruction
fetch
 3 stage Pipelining ARM organization
ARM processors up to the ARM7 employ a simple 3-stage
pipeline with the following pipeline stages:
 Fetch: the instruction is fetched from memory and placed in
the instruction pipeline
 Decode: the instruction is decoded and the datapath control
signals prepared for the next cycle. In this stage the
instruction 'owns' the decode logic but not the datapath.
 Execute: the instruction 'owns' the datapath; the register
bank is read, an operand shifted, the ALU result generated
and written back into a destination register.
At any one time, three different instructions may occupy each of
these stages, so the hardware in each stage has to be capable of
independent operation.
 3 stage Pipelining ARM organization

• When the processor is executing simple data processing

instructions the pipeline enables one instruction to be
completed every clock cycle.
• An individual instruction takes three clock cycles to complete, so
it has a three-cycle latency, but the throughput is one instruction
per cycle.
 3 stage Pipelining ARM organization

• When a multi-cycle instruction is executed the flow is less regular

• This shows a sequence of single-cycle ADD instructions with a data store
instruction, STR, occurring after the first ADD
• The cycles that access main memory are shown with light shading so it can be
seen that memory is used in every cycle
• The datapath is likewise used in every cycle, being involved in all the execute
cycles, the address calculation and the data transfer
• The decode logic is always generating the control signals for the datapath to use
in the next cycle, so in addition to the explicit decode cycles it is also generating
the control for the data transfer during the address calculation cycle of the STR
 5 stage Pipelining ARM organization
All processors have to develop to meet the demand for higher
performance
3-stage pipeline used in the ARM cores up to the ARM7 is very
cost-effective, but higher performance requires the processor
organization to be rethought
The time, Tprog , required to execute a given program is given by:

𝑁𝑖𝑛𝑠𝑡 × 𝐶𝑃𝐼
𝑇𝑝𝑟𝑜𝑔 =
𝑓𝑐𝑙𝑘
• where
− Ninst is the number of ARM instructions executed in the
course of the program
− CPI is the average number of clock cycles per instruction
− fclk is the processor's clock frequency.
 5 stage Pipelining ARM organization
Since Ninst is constant for a given program there are only two
ways to increase performance:
1. Increase the clock rate, fclk
o This requires the logic in each pipeline stage to be
simplified and, therefore, the number of pipeline stages to
be increased
2. Reduce the average number of clock cycles per instruction,
CPI
o This requires either that instructions which occupy more
than one pipeline slot in a 3-stage pipeline ARM are re-
implemented to occupy fewer slots, or that pipeline stalls
caused by dependencies between instructions are
reduced, or a combination of both.
5 stage Pipelining ARM organization
 Fetch - instruction is fetched from
memory and placed in the instruction
pipeline
 Decode - the instruction is decoded and
register operands read from the register
file. There are three operand read ports in
the register file, so most ARM instructions
can source all their operands in one cycle
 Execute - an operand is shifted and the
ALU result generated. If the instruction is
a load or store the memory address is
computed in the ALU
 Buffer/data - data memory is accessed if
required. Otherwise the ALU result is
simply buffered for one clock cycle to give
the same pipeline flow for all instructions
 Write-back - the results generated by the
instruction are written back to the
register file, including any data loaded
from memory.
5 stage Pipelining ARM organization
Fundamental problem with reducing the CPI relative to a 3-
stage core is related to the von Neumann bottleneck - any
stored-program computer with a single instruction and data
memory will have its performance limited by the available
memory bandwidth.
A 3-stage ARM core accesses memory on (almost) every clock
cycle either to fetch an instruction or to transfer data
Simply tightening up on the few cycles where the memory is not
used will yield only a small performance gain
To get a significantly better CPI the memory system must
deliver more than one value in each clock cycle either by
delivering more than 32 bits per cycle from a single memory or
by having separate memories for instruction and data accesses.
5 stage Pipelining ARM organization
Higher performance ARM cores employ a 5-stage pipeline and
have separate instruction and data memories
Breaking instruction execution down into five components
rather than three reduces the maximum work which must be
completed in a clock cycle, and hence allows a higher clock
frequency to be used
Separate instruction and data memories (which may be separate
caches connected to a unified instruction and data main
memory) allow a significant reduction in the core's CPI
A typical 5-stage ARM pipeline is that employed in the
ARM9TDMI