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TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015

TLC5971 12-Channel, 16-Bit, Enhanced Spectrum, PWM, RGB, LED Driver With 3.3-V
Linear Regulator
1 Features 2 Applications
•
1 12 Constant-Current Sink Output Channels RGB LED Cluster Lamp Displays
• Current Capability: 60 mA Per Channel
3 Description
• Grayscale (GS) Control With Enhanced Spectrum
The TLC5971 device is a 12-channel, constant-
PWM:
current sink driver. Each output channel has
16-Bit (65536 Steps) individually adjustable currents with 65536 PWM
• Global Brightness Control (BC): grayscale (GS) steps. Also, each color group can be
7-Bit (128 Steps) for Each Color Group controlled by 128 constant-current sink steps with the
• Power-Supply Voltage Range: global brightness control (BC) function. GS control
and BC are accessible through a two-wire signal
– Internal Linear Regulator: 6 V to 17 V interface. The maximum current value for each
– Direct Power Supply: 3 V to 5.5 V channel is set by a single external resistor. All
• LED Supply Voltage: Up to 17 V constant-current outputs are turned off when the IC is
• Constant-Current Accuracy: in an overtemperature condition.
– Channel-to-Channel = ±1% (Typical) Device Information(1)
– Device-to-Device = ±1% (Typical) PART NUMBER PACKAGE BODY SIZE (NOM)
• Data Transfer Rate: 20 MHz HTSSOP (20) 6.50 mm × 4.40 mm
TLC5971
• Linear Voltage Regulator: 3.3 V VQFN (24) 4.00 mm × 4.00 mm
• Auto Display Repeat Function (1) For all available packages, see the orderable addendum at
the end of the data sheet.
• Display Timing Reset Function
• Internal and External Selectable GS Clock
• Thermal Shutdown (TSD) With Auto Restart
• Unlimited Device Cascading
• Operating Temperature Range: –40°C to +85°C
Typical Application Circuit Example (Internal Linear Regulator Using VCC = 6 V to 17 V)
VCC
Power
Supply
(6 V to 17 V) GND

Device Optional Device Optional

GND VCC GND VCC
1 mF 1 mF
VREG OUTR0 VREG OUTR0

IREF OUTG0 IREF OUTG0

¼

OUTG3 OUTG3

OUTB3 OUTB3

DATA SDTI SDTO SDTI SDTO

(1)
Controller CLK SCKI SCKO SCKI SCKO

GND

(1) The output voltage range is from 0 V to 3.3 V.

NOTE: The number of LEDs in series changes, depending on the VCC voltage.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLC5971
SBVS146D – AUGUST 2010 – REVISED DECEMBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ....................................... 14
2 Applications ........................................................... 1 8.3 Feature Description................................................. 15
3 Description ............................................................. 1 8.4 Device Functional Modes........................................ 18
8.5 Programming........................................................... 19
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 9 Application and Implementation ........................ 26
9.1 Application Information............................................ 26
6 Specifications......................................................... 4
9.2 Typical Application .................................................. 26
6.1 Absolute Maximum Ratings ...................................... 4
9.3 System Examples ................................................... 31
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4 10 Power Supply Recommendations ..................... 32
6.4 Thermal Information .................................................. 5 11 Layout................................................................... 32
6.5 Electrical Characteristics........................................... 5 11.1 Layout Guidelines ................................................. 32
6.6 Switching Characteristics .......................................... 7 11.2 Layout Example .................................................... 32
6.7 Dissipation Ratings ................................................... 8 12 Device and Documentation Support ................. 33
6.8 Typical Characteristics ............................................ 11 12.1 Community Resources.......................................... 33
7 Parametric Measurement Information ............... 13 12.2 Trademarks ........................................................... 33
7.1 Test Circuits ............................................................ 13 12.3 Electrostatic Discharge Caution ............................ 33
7.2 Pin Equivalent Input and Output Schematics ......... 13 12.4 Glossary ................................................................ 33
8 Detailed Description ............................................ 14 13 Mechanical, Packaging, and Orderable
8.1 Overview ................................................................. 14
Information ........................................................... 33

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2012) to Revision D Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision B (June 2012) to Revision C Page

• Changed typical application circuit (internal linear regulator), added footnote 1.................................................................... 1
• Changed typical application circuit (direct power), added footnote 1................................................................................... 31
• Added typical application circuit example (direct power supplying VCC = 3 V to 5.5 V, VLED = 15 V), added footnote 1..... 31

Changes from Revision A (December 2010) to Revision B Page

• Changed IOLKG parameter test conditions in Electrical Characteristics table.......................................................................... 5

• Updated Figure 23................................................................................................................................................................ 15
• Changed bit 217 description in Table 5................................................................................................................................ 24

Changes from Original (August 2010) to Revision A Page

• Changed Global Brightness Control bullet in Features .......................................................................................................... 1

• Changed typical application circuit (internal linear regulator)................................................................................................. 1
• Moved Thermal Shutdown and Noise Reduction sections................................................................................................... 18
• Updated bit names for BCR, BCG, and BCB in Table 5 ...................................................................................................... 24
• Changed typical application circuit (direct power) ................................................................................................................ 31

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5 Pin Configuration and Functions

PWP Package
20-Pin HTSSOP RGE Package
Bottom View 24-Pin VQFN
Bottom View

OUTG1

OUTG0
OUTR1

OUTR0
OUTB0
OUTB1
IREF 1 20 VREG

GND 2 19 VCC

21
23

22
24

20

19
OUTR0 3 18 OUTB3
SDTI 1 18 GND
OUTG0 4 17 OUTG3
SCKI 2 17 NC
OUTB0 5 PowerPAD 16 OUTR3 (1)
3 16 IREF
NC Thermal Pad
(Bottom Side) (Bottom Side)
OUTR1 6 15 OUTB2 NC 4 15 VREG

SCKO 5 14 NC
OUTG1 7 14 OUTG2
SDTO 6 13 VCC
OUTB1 8 13 OUTR2

11

12
10
8

9
7
SDTI 9 12 SDTO

OUTR2

OUTR3
OUTB2

OUTG3

OUTB3
OUTG2
SCKI 10 11 SCKO

NC = not connected

Pin Functions
PIN
I/O DESCRIPTION
NAME PWP RGE
SDTI 9 1 I Serial data input for the 224-bit shift register
Serial data shift clock input.
Data present on SDTI are shifted to the LSB of the 224-bit shift register with the SCKI rising edge
SCKI 10 2 I
Data in the shift register are shifted toward the MSB at each SCKI rising edge.
The MSB data of the shift register appear on SDTO.
Serial data output of the 224-bit shift register.
SDTO 12 6 O SDTO is connected to the MSB of the 224-bit shift register.
Data are clocked out at the SCKI rising edge.
Serial data shift clock output.
SCKO 11 5 O The input shift clock signal from SCKI is adjusted to the timing of the serial data output for SDTO
and the signal is then output at SCKO.
Internal linear voltage regulator output.
A decoupling capacitor of 1 µF must be connected. This output can be used for external devices
VREG 20 15 I/O as a 3.3-V power supply. This terminal can be connected with the VREG terminal of other
devices to increase the supply current. Also, this pin can be supplied with 3 V to 5.5 V from an
external power supply by connecting it to VCC.
Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-
IREF 1 16 I/O
current output. When this terminal is directly connected to GND, all outputs are forced off. The
external resistor should be placed close to the device.
OUTR0 3 19 O
OUTR1 6 22 O RED constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTR2 13 7 O Different voltages can be applied to each output.
OUTR3 16 10 O
OUTG0 4 20 O
OUTG1 7 23 O GREEN constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTG2 14 8 O Different voltages can be applied to each output.
OUTG3 17 11 O
OUTB0 5 21 O
OUTB1 8 24 O BLUE constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTB2 15 9 O Different voltages can be applied to each output.
OUTB3 18 12 O
VCC 19 13 — Power-supply terminal

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Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME PWP RGE
GND,
PowerPAD 2 — —
(PWP)
GND, Power ground terminal
exposed
— 18 —
thermal
pad (RGE)
3, 4, 14,
NC — — No internal connection
17

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted. (1) (2)
MIN MAX UNIT
Supply voltage, VCC –0.3 18 V
IREF –0.3 VREG + 0.3 V
Input voltage
SDTI, SCKI –0.3 VREG + 0.6 V
OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3 –0.3 18 V
Output voltage SDTO, SCKO –0.3 VREG + 0.3 V
VREG –0.3 6 V
OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3 75 mA
Output current (DC)
VREG –30 mA
Operating junction temperature, TJ (max) 150 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

at TA = –40°C to +85°C, and VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, unless otherwise noted.
MIN NOM MAX UNIT
DC CHARACTERISTICS
VCC Supply voltage, internal voltage regulator used 6 17 V
VREG Supply voltage, VREG connected to VCC 3 3.3 5.5 V
Voltage applied to output
VO 17 V
(OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3)
VIH High-level input voltage (SDTI, SCKI) 0.7 × VREG VREG V
VIL Low-level input voltage (SDTI, SCKI) GND 0.3 × VREG V
VIHYS Input voltage hysteresis (SDTI, SCKI) 0.2 × VREG V
IOH High-level output current (SDTO) –2 mA
IOL Low-level output current (SDTO) 2 mA
Constant output sink current
IOLC 60 mA
(OUTR0 to OUTR3, OUTG0 to OUTG3, OUTB0 to OUTB3)

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Recommended Operating Conditions (continued)

at TA = –40°C to +85°C, and VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, unless otherwise noted.
MIN NOM MAX UNIT
IREG Voltage regulator output current (VREG) –25 mA
TA Operating free temperature range –40 85 °C
TJ Operating junction temperature –40 125 °C
AC CHARACTERISTICS
fCLK (SCKI) Data clock frequency and GS control clock frequency, SCKI 0.007 20 MHz
tWH/tWL Pulse duration, SCKI 10 ns
tSU Setup time, SDTI – SCKI↑ 5 ns
tH Hold time, SDTI – SCKI↑ 3 ns

6.4 Thermal Information

TLC5971
(1)
THERMAL METRIC PWP (HTSSOP) RGE (VQFN) UNIT
20 PINS 24 PINS
θJA Junction-to-ambient thermal resistance 68.6 38 °C/W
θJCtop Junction-to-case (top) thermal resistance 44.2 40.5 °C/W
θJB Junction-to-board thermal resistance 19.3 10.2 °C/W
ψJT Junction-to-top characterization parameter 2.7 0.3 °C/W
ψJB Junction-to-board characterization parameter 15.7 10 °C/W
θJCbot Junction-to-case (bottom) thermal resistance 1.8 2.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwise
noted. Typical values are at TA = 25°C and VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage, SDTO/SCKO IOH = –2 mA VREG – 0.4 VREG V
VOL Low-level output voltage, SDTO/SCKO IOL = 2 mA 0 0.4 V
II Input current, SDTI/SCKI VI = VREG or GND –1 1 µA
SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,
ICC 2 4 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 24 kΩ (IOLCMax = 2 mA)
SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,
ICC1 6 9 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 1.6 kΩ (IOLCMax = 30 mA)

Supply current SDTI = 10 MHz, SCKI = 20 MHz, BLANK = 0,

ICC2 auto repeat enable, external GS clock selected, GSn = FFFFh, 14 22 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 1.6 kΩ (IOLCMax = 30 mA)
SDTI = 10 MHz, SCKI = 20 MHz, BLANK = 0,
ICC3 auto repeat enable, external GS clock selected, GSn = FFFFh, 21 36 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)
All OUTXn on, BCX = 7Fh, VOUTXn = 1 V,
IOLC Constant output current, OUTXn 56.3 60.5 64.7 mA
VOUTfix = 1 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)
All OUTXn off, BCX = 7Fh, VOUTXn = 17 V,
IOLKG Leakage output current, OUTXn 0.1 µA
VOUTfix = 17 V, RIREF = 0.82 kΩ (IOLCMax = 60 mA)

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Electrical Characteristics (continued)

At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwise
noted. Typical values are at TA = 25°C and VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Constant-current error (1)
All OUTXn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
ΔIOLC (channel-to-channel in same color group), –3% ±1% 3%
RIREF = 0.82 kΩ (IOLCMax = 60 mA)
OUTXn
Constant current error (2) All OUTXn on, BCX = 7Fh, VOUTXn = VOUTfix = 1V,
ΔIOLC1 (device-to-device in same color group), RIREF = 0.82 kΩ (IOLCMax = 60 mA), at same grouped color output –4% ±1 4%
OUTXn of OUTR0-3, OUTG0-3, and OUTB0-3
Line regulation of constant-current output, All OUTn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
ΔIOLC2 –1 ±0.5 1 %/V
OUTXn (3) RIREF = 0.82 kΩ (IOLCMax = 60 mA)

(1)
The deviation of each output in the same color group (OUTR0-OUTR3 or OUTG0-OUTG3 or OUTB0-OUTB3)
from the average current from the same color group. Deviation is calculated by Equation 1:
IOLCXn
D (%) = -1 ´ 100
(IOLCX0 + IOLCX1 + IOLCX2 + IOLCX3)
4

where
(a) X = R/G/B,
(b) n = 0-3. (1)
(2)
The deviation of each color group constant-current average from the ideal constant-current value. Deviation is
calculated by Equation 2:
(IOLCX0 + IOLCX1 + IOLCX2 + IOLCX3)
- (Ideal Output Current)
4
D (%) = ´ 100
Ideal Output Current

where
(a) X = R/G/B. (2)
Ideal current is calculated by Equation 3 for the OUTRn and OUTGn groups:
1.21
IOLCXn(IDEAL) (mA) = 41 ´
RIREF (W)

where
(a) X = R/G/B. (3)
(3)
Line regulation is calculated by Equation 4:
(IOLCXn at VCC = 5.5 V) - (IOLCXn at VCC = 3 V) 100
D (%/V) = ´
(IOLCXn at VCC = 3 V) 5.5 V - 3 V

where
(a) X = R/G/B,
(b) n = 0-3. (4)

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Electrical Characteristics (continued)

At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwise
noted. Typical values are at TA = 25°C and VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Load regulation of constant-current output, All OUTn on, BCX = 7Fh, VOUTXn = VOUTfix = 1 V,
ΔIOLC3 –3 ±1 3 %/V
OUTXn (4) RIREF = 0.82 kΩ (IOLCMax = 60 mA)
(5)
TTSD Thermal shutdown temperature Junction temperature 150 165 180 °C
THYS Thermal shutdown hysteresis Junction temperature (5) 5 10 20 °C
VIREF Reference voltage output, IREF RIREF = 0.82 kΩ 1.18 1.21 1.24 V
VREG Linear regulator output voltage, VREG VCC = 6 V to 17 V, IREG = 0 mA to –25 mA 3.1 3.3 3.5 V
ΔVREG Line regulation of linear regulator, VREG VCC = 6 V to 17 V, IREG = 0 mA 90 mV
ΔVREG1 Load regulation of linear regulator, VREG VCC = 12 V, IREG = 0 mA to –25 mA 120 mV
VSTR Undervoltage lockout release, VREG 2.5 2.7 2.9 V
VHYS Undervoltage lockout hysteresis, VREG 300 400 500 mV

(4)
Load regulation is calculated by Equation 5:
(IOLCXn at VOUTXn = 3 V) - (IOLCXn at VOUTXn = 1 V) 100
D (%/V) = ´
(IOLCXn at VOUTXn = 1 V) 3V-1V

where
(a) X = R/G/B,
(b) n = 0-3. (5)
(5) Not tested, specified by design.

6.6 Switching Characteristics

At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, CVREG = 1 µF, CL = 15 pF, RL = 68 Ω, and VLED =
5 V, unless otherwise noted. Typical values are at TA = 25°C and VCC = 12 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 Rise time, SDTO/SCKO 3 10 ns
tR1 Rise time, OUTXn BCX = 7Fh 5 15 ns
tF0 Fall time, SDTO/SCKO 3 10 ns
tF1 Fall time, OUTXn BCX = 7Fh 15 25 ns
tD0 SCKI↑ to SDTO↑↓ 10 25 60 ns
tD1 SCKI↑ to SCKO↑ 5 15 40 ns
(1)
tD2 SCKO↑ to SDTO↑↓ 5 10 20 ns
SCKI↑ to OUTRn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 1
tD3 10 25 60 ns
Or SCKI↓ to OUTRn↑↓, BLANK = 0,
BCXn = 7Fh, OUTTMG = 0
SCKI↑ to OUTGn↑↓, BLANK = 0, BCXn
Propagation delay
= 7Fh, OUTTMG = 1
tD4 25 50 90 ns
Or SCKI↓ to OUTGn↑↓, BLANK = 0,
BCXn = 7Fh, OUTTMG = 0
SCKI↑ to OUTBn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 1
tD5 40 75 120 ns
Or SCKI↓ to OUTBn↑↓, BLANK = 0,
BCXn = 7Fh, OUTTMG = 0
Last SCKI↑ to internal latch pulse
tD6 (2) 8/fOSC 16384/fOSC s
genaration
tW(SCKO) Shift clock output one pulse width SCKO↑ to SCKO↓ 12 25 35 ns
fOSC Internal oscillator frequency 6 10 12 MHz

(1) The propagation delays are calculated by tD2 = tD0 – tD1.

(2) The generation timing of the internal latch pulse changes depending on the SCKI clock frequency; see the Internal Latch Pulse
Generation Timing section.

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6.7 Dissipation Ratings

DERATING FACTOR POWER RATING POWER RATING POWER RATING
PACKAGE
ABOVE TA = 25°C TA < 25°C TA = 70°C TA = 85°C
HTSSOP 20-pin with PowerPAD soldered (1) 25.7 mW/°C 3121 mW 1998 mW 1623 mW
QFN 24-pin exposed thermal pad
24.8 mW/°C 3106 mW 1988 mW 1615 mW
soldered (2)

(1) With PowerPAD soldered onto copper area on TI recommended printed circuit board (PCB); 2-oz. copper. For more information, see
application report PowerPAD Thermally-Enhanced Package (SLMA002) available for download at www.ti.com.
(2) The package thermal impedance is calculated in accordance with JESD51-5.

TWH, TWL:
VREG

(1)
SCKI 50%

GND
TWH TWL

TSU, TH:
VREG

(1)
SCKI 50%

GND
TSU TH

VREG

(1)
SDTI 50%

GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 1. Input Timing

tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5:
VREG

(1) 50%
INPUT

GND

tD

VOH or VOUTXnH
90%

OUTPUT 50%

10%
VOL or VOUTXnL

tR or tF

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 2. Output Timing

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Write Command (6 Bits) Write Data (218 Bits)

DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTI 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C 215C
tH
tSU tWH

SCKI
1 2 6 222 223 224 1 2 3 4 5 6 7 8 9
tWL

224-Bit Shift Register DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA
LSB (Internal) 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C

224-Bit Shift Register DATA DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA
CMD0
LSB + 1 (Internal) 1A 0A CMD5 CMD1 3B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C
¼

¼
224-Bit Shift Register WRT WRT WRT DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA DATA
MSB - 1 (Internal) CMD4 CMD3 CMD2 216A 215A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B 214B

224-Bit Shift Register WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
MSB (Internal) CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B

(2)
tD6

Latch Signal
(Internal)

Latch Data
Previous Data Latest Data (All GS Data are 0001h)
(Internal)

1
BLANK Bit in Data Latch
(Internal) 0

1
EXTGCK Bit in Data Latch
(Internal) 0

1
OUTTMG Bit in Data Latch
(Internal) 0

tD0

WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTO CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B

tR0/tF0
tD1 tW(SCKO)

SCKO

tF1
(VOUTXnH)
OFF (1)
OUTR0-R3 (VOUTXnL)
ON
tR1
(VOUTXnH) tD3
OFF (1)
OUTG0-G3 (VOUTXnL)
ON
tD4
(VOUTXnH)
OFF (1)
OUTB0-B3 (VOUTXnL)
ON
tD5

(1) OUTXn ON-OFF timing depends on previous GS data in the 218-bit data latch.
(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal
latch signal generation.

Figure 3. Data Write and OUTXn Switching Timing (OUTTMG = 1)

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Write Command (6 Bits) Write Data (218 Bits)

DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTI 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C 215C
tH
tSU tWH

SCKI
1 2 6 222 223 224 1 2 3 4 5 6 7 8 9
tWL

224-Bit Shift Register DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA
LSB (Internal) 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C

224-Bit Shift Register DATA DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA
CMD0
LSB + 1 (Internal) 1A 0A CMD5 CMD1 3B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C
¼

¼
224-Bit Shift Register WRT WRT WRT DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA DATA
MSB - 1 (Internal) CMD4 CMD3 CMD2 216A 215A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B 214B

224-Bit Shift Register WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
MSB (Internal) CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B

(2)
tD6

Latch Signal
(Internal)

Latch Data
Previous Data Latest Data (All GS Data are 0001h)
(Internal)

1
BLANK Bit in Data Latch
(Internal) 0

1
EXTGCK Bit in Data Latch
(Internal) 0

1
OUTTMG Bit in Data Latch
(Internal) 0
tD0

WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTO CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B

tR0/tF0
tD1 tW(SCKO)

SCKO

tF1
(VOUTXnH)
OFF (1)
OUTR0-R3 (VOUTXnL)
ON
tR1
(VOUTXnH) tD3
OFF (1)
OUTG0-G3 (VOUTXnL)
ON
tD4
(VOUTXnH)
OFF (1)
OUTB0-B3 (VOUTXnL)
ON
tD5

(1) OUTXn ON-OFF timing depends on previous GS data in the 218-bit data latch.
(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal
latch signal generation.

Figure 4. Data Write and OUTXn Switching Timing (OUTTMG = 0)

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6.8 Typical Characteristics

At TA = 25°C and VCC = 24 V, unless otherwise noted.

100 4000
RIREF, Reference Resistor (kW)

Power Dissipation Rate (mW)

24.805
3000
9.922
10
3.307
4.961 1.984 2000
1.417
2.481 1.102 0.902
1 1.654
1.240
0.992 0.827 1000
TLC5971PWP
TLC5971RGE
0.1 0
0 10 20 30 40 50 60 70 -40 -20 0 20 40 60 80 100
IOLC, Output Current (mA) Free-Air Temperature (°C)

Figure 5. Reference Resistor vs Output Current Figure 6. Power Dissipation vs Temperature

70 64
TA = +25°C, VCC = 12 V, BCx = 7Fh IOLCMax = 60 mA
63
60 VCC = 12 V
IOLCMax = 60 mA IOLCMax = 50 mA 62 BCx = 7Fh
Output Current (mA)

50 Output Current (mA) 61

IOLCMax = 40 mA
40 60
IOLCMax = 30 mA 59
30
58
IOLCMax = 20 mA
20 57
TA = -40°C
IOLCMax = 2 mA IOLCMax = 5 mA
IOLCMax = 10 mA 56
10 TA = +25°C
55 TA = +85°C
0 54
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Output Voltage (V) Output Voltage (V)
Figure 7. Output Current vs Output Voltage Figure 8. Output Current vs Output Voltage
3 3
TA = +25°C IOLCMax = 60 mA
VCC = 12 V VCC = 12 V
2 2
BCx = 7Fh BCx = 7Fh

1 1
DIOLC (%)
DIOLC (%)

0 0

-1 -1

-2 -2

-3 -3
0 10 20 30 40 50 60 -40 -20 0 20 40 60 80 100
Output Current (mA) Ambient Temperature (°C)
Figure 9. Constant-Current Error vs Output Current Figure 10. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Color Group) (Channel-to-Channel in Color Group)

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Typical Characteristics (continued)

At TA = 25°C and VCC = 24 V, unless otherwise noted.
70 30
TA = +25°C TA = +25°C, VCC = 12 V
60 VCC = 12 V BCx = 7Fh, GSx = FFFFh
25
IOLCMax = 60 mA EXTGCK = 1, DSPRPT = 1
SDTI = 10 MHz, SCKI = 20 MHz
Output Current (mA)

50
20

ICC (mA)
40
IOLCMax = 2 mA IOLCMax = 30 mA 15
30
10
20
IOLCMax = 10 mA
10 5

0 0
0 16 32 48 64 80 96 112 128 0 10 20 30 40 50 60
Brightness Control Data (dec) Output Current (mA)
Figure 11. Global Brightness Control Linearity Figure 12. Supply Current vs Output Current
30 3.5

Linear Regulator Output Voltage, VREG (V)

3.45
25
3.4
20
3.35
ICC (mA)

15 3.3

3.25
10
IOLCMax = 60 mA, VCC = 12 V TA = +25°C, IOLCMax = 60 mA,
3.2
5 BCx = 7Fh, GSx = FFFFh VCC = 12 V
EXTGCK = 1, DSPRPT = 1 3.15 BCx = 7Fh, GSx = FFFFh
SDTI = 10 MHz, SCKI = 20 MHz EXTGCK = 0, DSPRPT = 1
0 3.1
-40 -20 0 20 40 60 80 100 0 5 10 15 20 25
Ambient Temperature (°C) Linear Regulator Output Current, IREG (mA)
Figure 13. Supply Current vs Ambient Temperature Figure 14. Linear Regulator Output Voltage vs Linear
Regulator Output Current
3.5
Linear Regulator Output Voltage, VREG (V)

TA = +25°C, IOLCMax = 60 mA,

CH1 TA = +25°C, VCC = 12 V
3.45 BCx = 7Fh, GSx = FFFFh CH1 (2 V/div) (OUTR0) IOLCMax = 60 mA, BCx = 7Fh,
EXTGCK = 0, DSPRPT = 1 GSXn = 0001h, VLED = 5 V,
3.4 RL = 68 W, OUTTMG = 1
CH 2
3.35 (OUTG0)
CH2 (2 V/div)
3.3 IREG = 0 mA
CH3
3.25 (OUTB0)
IREG = -25 mA
CH3 (2 V/div) CH4
3.2
(SCKI)
3.15 CH4 (5 V/div)

3.1 Time (20 ns/div)

6 8 10 12 14 16 18
Supply Voltage, VCC (V)

Figure 15. Linear Regulator Output Voltage vs Supply Figure 16. Constant-Current Output Voltage Waveform
Voltage

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7 Parametric Measurement Information

7.1 Test Circuits

VCC
RL
VREG VCC
(1)
OUTXn VLED
VCC
IREF
CVREG CL
(2) VREG SDTO/SCKO
GND VCC
RIREF
(1)
CVREG CL
GND

(1) X = R/G/B, n = 0-3.

(2) CL includes measurement probe and stray
capacitance. (1) CL includes measurement probe and stray
capacitance.
Figure 17. Rise/Fall Time Test Circuit for OUTXn
Figure 18. Rise/Fall Time Test Circuit for
SDTO/SCKO

VCC
OUTR0
VREG ¼ ¼
(1)
OUTXn
VCC
IREF
CVREG OUTB3 VOUTXn
RIREF GND
VOUTfix

(1) X = R/G/B, n = 0-3.

Figure 19. Constant-Current Test Circuit for OUTXn

7.2 Pin Equivalent Input and Output Schematics

VREG
VREG

INPUT
OUTPUT

GND
GND
Figure 20. SDTI/SCKI
Figure 21. SDTO/SCKO

(1)
OUTXn

GND
(1) X = R/G/B, n = 0-3.

Figure 22. OUTR0 Through OUTB3

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8 Detailed Description

8.1 Overview
The TLC5971 is a 12-channel constant current sink driver. Each channel has an individually-adjustable, 65535-
step, pulse width modulation (PWM) grayscale (GS) control. Each color has a 128-step brightness control (BC).
GS data and BC data are input through a serial single-wire interface port.
The TLC5971 has a 60-mA current capability. The maximum current value of each channel is determined by the
external resistor. The TLC5971 can work without external CLK signals since it can select to use internal oscillator
or external GS clock.
The TLC5971 is integrated with a linear regulator that can be used for higher VCC power-supply voltage from 6
V to 17 V.

8.2 Functional Block Diagram

VCC

3.3 V VREG
REG
LSB MSB UVLO reset

SDTI
224-Bit Shift Register SDTO

Clock 0 223
SCKI Timing SCKO
Adjust 6
Write
218
Command
Decode
wrtena

LSB MSB
intlat
Data 218-Bit Data Latch
Latch reset
Control
0 217
26
EXTCLK
1 intlat 2 BLANK
TMGRST 192 3
Clock GS Clock Thermal
Select Counter BLANK Detection
DSPRPT
16 GSX
OUTTMG

Internal
16-Bit ES-PWM Timing Control
Oscillator
12
21

3-Grouped Switching Delay

BCX
12
Reference
12-Channel Constant Sink Current Driver
IREF Current
with 7-Bit, 3-Grouped BC
Control

GND

OUTR0 OUTG0 OUTB0 OUTR3 OUTG3 OUTB3

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8.3 Feature Description

8.3.1 Auto Display Repeat Function
This function repeats the total display period without a BLANK bit change, as long as the GS reference clock is
available. This function can be enabled or disabled with DSPRPT (bit 214) in the data latch. When the DSPRPT
bit is 1, this function is enabled and the entire display period repeats without a BLANK bit data change. When the
DSPRPT bit is 0, this function is disabled and the entire display period executes only once after the BLANK bit is
set to 0 or the internal latch pulse is generated when the display timing reset function is enabled. Figure 23
shows the auto display repeat operation timing.
BLANK Bit
in Data Latch
(Internal)
1 4 65534 1 4 65534 1 4 7 10 1 65534 1
2 5 65535 2 5 65535 2 5 8 2 65535 2
3 65533 65536 3 65533 65536 3 6 9 65536
GS Reference Clock
(SCKI or Internal Oscillator)

DSPRPT = 1
(Auto Repeat On)
DSPRPT Bit DSPRPT = 0
in Data Latch (Auto Repeat Off)
(Internal)
1st
1st Display Period 2nd Display Period 3rd Display Period Display Period

OUTn is not turned

Display period is repeated OUTn is forced off on until the next
by auto refresh function. when BLANK is ‘1’. BLANK changes
OFF to ‘0’.
OUTXn
(GSDATA = FFFFh) ON

Figure 23. Auto Repeat Display Function

8.3.2 Display Timing Reset Function

This function allows the display timing to be initialized using the internal latch pulse, as shown in Figure 24. This
function can be enabled or disabled by TMGRST (bit 215) in the data latch. When the TMGRST bit is 1, the GS
counter is reset to 0 and all outputs are forced off when the internal latch pulse is generated. This function is the
same when the BLANK bit changes (such as from 0 to 1 and from 1 to 0). Therefore, the BLANK bit does not
need to be controlled from an external controller to restart the PWM control from the next GS reference clock
rising edge. When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latch
pulse is generated. Figure 24 shows the display timing reset operation.

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Feature Description (continued)

BLANK Bit
in Data Latch 0 = No BLANK.
(Internal)

1 = Display timing reset function is enabled.

TMGRST Bit
in Data Latch
(Internal)

1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
EXTCLK Bit
in Data Latch
(Internal)
1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
OUTTMG Bit
in Data Latch
(Internal)

SCKI
N-4 N-3 N-2 N-1 N 8x or greater internal 1 2 3 ¼
8x Period A clock period
Internal Latch Pulse Period A (1.34 ms, min).
(Internal)

GS Counter M-4 M-3 M-2 M-1 M 0 1 2 3

for PWM Control
(Internal) When the TMGRST bit is ‘1’, the GS counter is
reset to ‘0’ at the internal latch pulse generation timing. OFF
OFF Also, OUTXn is forced off at the same time.
OUTXn ON ON
ON

Figure 24. Display Timing Reset Function

8.3.3 Output Timing Select Function

This function selects the ON-OFF change timing of the constant-current outputs (OUTXn) set by OUTTMG (bit
217) in the data latch. When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GS
reference clock. When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock.
Electromagnetic interference (EMI) of the total system can be reduced using this bit setting. For example, when
the odd number of devices in the system have this bit set to 0 and the even number of devices in the system
have this bit set to 1, EMI is reduced because the devices change the OUTXn status at a deferent timing.
Figure 25 and Figure 26 show the output switching timing when the OUTTMG bit is 1 and 0, respectively.

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Feature Description (continued)

1
BLANK Bit
in Data Latch 0
(Internal)

1 = SCKI used for OUTXn on-off timing control.

EXTCLK Bit
in Data Latch
(Internal)
1 = OUTXn on-off state changes at the rising edge of the clock selected by the EXTCLK bit.
OUTTMG Bit
in Data Latch
(Internal)

SCKI

1 2 3 ¼ 65534 65535 65536

OFF
OUTR0-R3
ON
tD3 OUTXn on-off state changes at the rising tD3
OFF edge of the clock selected by the EXTCLK bit.
OUTG0-G3
ON
tD4 tD4

OFF
OUTB0-B3
ON
tD5 tD5

Figure 25. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 1)

1
BLANK Bit
in Data Latch 0
(Internal)

1 = SCKI used for OUTXn on-off timing control.

EXTCLK Bit
in Data Latch
(Internal)

OUTTMG Bit
in Data Latch
(Internal)
0 = OUTXn on-off state changes at the falling edge of the clock selected by the EXTCLK bit.

SCKI

1 2 3 ¼ 65534 65535 65536

OFF
OUTR0-R3
ON
tD3 OUTXn on-off state changes at the falling tD3
edge of the clock selected by the EXTCLK bit.
OFF
OUTG0-G3
ON
tD4 tD4

OFF
OUTB0-B3
ON
tD5 tD5

Figure 26. Output ON-OFF Timing With Four-Channel Grouped Delay (OUTTMG = 0)

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Feature Description (continued)

8.3.4 Thermal Shutdown
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds the threshold (TTSD = 165°C, typical). When the junction temperature drops below (TTSD – THYS), the
output control starts at the first GS clock in the next display period.

8.3.5 Noise Reduction

Large surge currents may flow through the IC and the board if all 12 outputs turn on simultaneously at the start of
each GS cycle. These large current surges could induce detrimental noise and EMI into other circuits. The
TLC5971 turns on the outputs for each color group independently with a 25 ns (typical) rise time. The output
current sinks are grouped into three groups. The first group that is turned on/off are OUTR0-3; the second group
that is turned on/off are OUTG0-3; and the third group is OUTB0-3. However, the state of each output is
controlled by the selected GS clock; see the Output Timing Select Function section.

8.4 Device Functional Modes

8.4.1 Maximum Constant Sink Current Setting
The maximum constant sink current value for each channel, IOLCMax, is programmed through a single resistor,
RIREF, placed between IREF and GND. The desired value can be calculated with Equation 6:
VIREF (V)
RIREF (kW) = ´ 41
IOLCMax (mA)

where:
VIREF = the internal reference voltage on the IREF pin (1.21 V, typically, when the the global brightness
control data are at maximum),
IOLCMax = 2 mA to 60 mA. (6)
IOLCMax is the maximum current for each output. Each output sinks the IOLCMax current when it is turned on and
global brightness control data (BC) are set to the maximum value of 7Fh (127d).
RIREF must be between 0.82 kΩ and 24.8 kΩ to hold IOLCMax between 60 mA (typical) and 2 mA (typical).
Otherwise, the output may be unstable. Output currents lower than 2 mA can be achieved by setting IOLCMax to 2
mA or higher and then using global brightness control to lower the output current. The constant-current sink
values for specific external resistor values are shown in Figure 5 and Table 1.

Table 1. Maximum Constant-Current vs External Resistor Value

IOLCMax (mA) RIREF (kΩ, Typical)
60 0.827
55 0.902
50 0.992
45 1.1
40 1.24
35 1.42
30 1.65
25 1.98
20 2.48
15 3.31
10 4.96
5 9.92
2 24.8

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8.5 Programming
8.5.1 Global Brightness Control (BC) Function (Sink Current Control)
The TLC5971 has the capability to adjust all output currents of each color group (OUTR0-3, OUTG0-3, and
OUTB0-3) to the same current value. This function is called global brightness (BC) control. The BC data are
seven bits long, which allows each color group output current to be adjusted in 128 steps from 0% to 100% of
the maximum output current, IOLCMax. The BC data are set through the serial interface. When the BC data are
changed, the output current is changed immediately.
When the IC is powered on, all outputs are forced off by BLANK (bit 213). BLANK initializes in the data latch but
the data in the 224-bit shift register and the 218-bit data latch are not set to a default value, except for the
BLANK bit. Therefore, BC data must be written to the data latch when BLANK is set to 0.
Equation 7 determines each color group maximum output sink current:
BCX
IOUT (mA) = IOLCMax (mA) ´
127d

Where:
IOLCMax = the maximum channel current for each channel determined by RIREF
BC = the global brightness control value in the data latch for the specific color group
(BCX = 0d to 127d, X = R/G/B) (7)
Table 2 summarizes the BC data value versus the output current ratio and set current value.

Table 2. BC Data vs Current Ratio and Set Current Value

OUTPUT CURRENT
BC DATA BC DATA RATIO TO IOLCMax 60 mA IOLCMax 2 mA IOLCMax
BC DATA (BINARY) (DECIMAL) (HEX) (%, TYPICAL) (mA, TYPICAL) (mA, TYPICAL)
000 0000 0 00 0 0 0
000 0001 1 01 0.8 0.47 0.02
000 0010 2 02 1.6 0.94 0.03
— — — — — —
111 1101 125 7D 98.4 59.06 1.97
111 1110 126 7E 99.2 59.53 1.98
111 1111 127 7F 100 60 2

8.5.2 Grayscale (GS) Function (PWM Control)

The TLC5971 can adjust the brightness of each output channel using the enhanced spectrum pulse width
modulation (ES-PWM) control scheme. The PWM bit length for each output is 16 bits. The use of the 16-bit
length results in 65536 brightness steps from 0% to 100% brightness.
The PWM operation for all color groups is controlled by a 16-bit grayscale (GS) counter. The GS counter
increments on each rising or falling edge of the external or internal GS reference clock that is selected by
OUTTMG (bit 217) and EXTGCK (bit 216) in the data latch. When the external GS clock is selected, the GS
counter uses the SCKI clock as the grayscale clock. The GS counter is reset to 0000h and all outputs are forced
off when BLANK (bit 213) is set to 1 in the data latch and the counter value is held at 0 while BLANK is 1, even if
the GS reference clock is toggled in between.
Equation 8 calculates each output (OUTXn) total on-time (tOUT_ON):
tOUT_ON (ns) = tGSCLK (ns) ´ GSXn

Where:
tGSCLK = one period of the selected GS reference clock
(internal clock = 100ns typical, external clock = the period of SCKI)
GSXn = the programmed GS value for OUTXn (0d to 65535d) (8)

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Table 3 summarizes the GS data values versus the output total ON-time and duty cycle. When the IC is powered
up, BLANK (bit 213) is set to 1 to force all outputs off; however, the 224-bit shift register and the 218-bit data
latch are not set to default values. Therefore, the GS data must be written to the data latch when BLANK (bit
213) is set to 0.

Table 3. Output Duty Cycle and Total On-Time versus GS Data

GS DATA GS DATA
(DECIMAL) GS DATA (HEX) ON-TIME DUTY (%) (DECIMAL) GS DATA (HEX) ON-TIME DUTY (%)
0 0 0 32768 8000 50.001
1 1 0.002 32769 8001 50.002
2 2 0.003 32770 8002 50.004
3 3 0.005 32771 8003 50.005
— — — — — —
8191 1FFF 12.499 40959 9FFF 62.499
8192 2000 12.5 40960 A000 62.501
8193 2001 12.502 40961 A001 62.502
— — — — — —
16383 3FFF 24.999 49149 BFFF 74.997
16384 4000 25 49150 C000 74.998
16385 4001 25.002 49151 C001 75
— — — — — —
24575 5FFF 37.499 57343 DFFF 87.5
24576 6000 37.501 57344 E000 87.501
24577 6001 37.502 57345 E001 87.503
— — — — — —
32765 7FFD 49.996 65533 FFFD 99.997
32766 7FFE 49.998 65534 FFFE 99.998
32767 7FFF 49.999 65535 FFFF 100

8.5.3 Enhanced Spectrum (ES) PWM Control

Enhanced spectrum (ES) PWM has the total display period divided into 128 display segments. The total display
period refers the period between the first grayscale clock input to the 65536th grayscale clock input after BLANK
(bit 213) is set to 0. Each display period has 512 grayscale values, maximum. Each output on-time changes
depending on the grayscale data. Refer to Table 4 for sequence information and Figure 27 for timing information.

Table 4. ES-PWM Drive Turnon Time Length

GS DATA GS DATA
(DEC) (HEX) OUTn DRIVER OPERATION
0 0000h Does not turn on
1 0001h Turns on during one GS clock period in the 1st display period
2 0002h Turns on during one GS clock period in the 1st and 65th display period
3 0003h Turns on during one GS clock period in the 1st, 33rd, and 65th display period
4 0004h Turns on during one GS clock period in the 1st, 33rd, 65th, and 97th display period
5 0005h Turns on during one GS clock period in the 1st, 17th, 33rd, 65th, and 97th display period
6 0006h Turns on during one GS clock period in the 1st, 17th, 33rd, 65th, 81st, and 97th display period
The number of display periods that OUTXn is turned on during one GS clock is incremented by the GS
data increasing in the following order. The order of display periods that the output turns on are:
1, 65, 33, 97, 17, 81, 49, 113, 9, 73, 41, 105, 25, 89, 57, 121, 5, 69, 37, 101, 21, 85, 53, 117, 13, 77,
45, 109, 29, 93, 61, 125, 3, 67, 35, 99, 19, 83, 51, 115, 11, 75, 43, 107, 27, 91, 59, 123, 7, 71, 39, 103,
— —
23, 87, 55, 119, 15, 79, 47, 111, 31, 95, 63, 127, 2, 66, 34, 98, 18, 82, 50, 114, 10, 74, 42, 106, 26, 90,
58, 122, 6, 70, 38, 102, 22, 86, 54, 118, 14, 78, 46, 110, 30, 94, 62, 126, 4, 68, 36, 100, 20, 84, 52,
116, 12, 76, 44, 108, 28, 92, 60, 124, 8, 72, 40, 104, 24, 88, 56, 120, 16, 80, 48, 112, 32, 96, 64, and
128.

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Table 4. ES-PWM Drive Turnon Time Length (continued)

GS DATA GS DATA
(DEC) (HEX) OUTn DRIVER OPERATION
Turns on during one GS clock period in the 1st to 127th display period, but does not turn on in the
127 007Fh
128th display period
128 0080h Turns on during one GS clock period in all display periods (1st to 128th)
Turns on during two GS clock periods in the 1st display period and one GS clock period in the next
129 0081h
display period
The number of display periods where OUTn is turned on for two GS clocks is incremented by the
— —
increased GS data similar to the previous case where the GS value is 1 trough 127
Turns on during two GS clock periods in the 1st to 127th display period, but only turns on during one
255 00FFh
GS clock period in the 128th display period
256 0100h Turns on during two GS clock periods in all display periods (1st to 128th)
Turns on during three GS clock periods in the 1st display period and two GS clock periods in the next
257 0101h
display period
Display periods with OUTn turned on is incremented by the increased GS datasimilar to 0101h
— —
operation
Turns on during 511 GS clock periods in the 1st to 127th display period, but only turns on 510 GS
65478 FEFFh
clock periods in the 128th display period
65280 FF00h Turns on during 511 GS clock periods in all display periods (1st to 128th)
Turns on during 512 GS clock periods in the 1st display period and 511 GS clock periods in the 2nd to
65281 FF01h
128th display periods
— — —
Turns on during 512 GS clock periods in the 1st to 63th and 65th to 127th display periods, and turns on
65534 FFFEh
511 GS clock periods in the 64th and 128th display periods
Turns on during 512 GS clock periods in the 1st to 127th display period, but only turns on 511 GS
65535 FFFFh
clock periods in the 128th display period

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BLANK Bit in Data Latch

(Internal)
16382 16385 32766 32769 49150 49153 65023 65026 65534
511 513 16383 16386 32767 32770 49151 49154 65024 65535
1 2 3 ¼ 512 514 ¼ 16384 16387 ¼ 32768 32771 ¼
49152 49155 ¼ 65025 ¼ 65536
GS Reference Clock
(Internal)
1st ¼ 2nd ¼ 32nd 33rd ¼ 64th 65th ¼ 96th 97th ¼ 127th 128th 1st
High Voltage Level Period Period Period Period Period Period Period Period Period Period Period
OUTXn OFF
(GS Data = 0000h) ON Low Voltage Level

T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0001h) ON

T = GS Clock ´ 1d T = GS Clock ´ 1d When the DSPRPT Bit is ‘1’

OUTXn OFF
(GS Data = 0002h) ON
T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0003h) ON
T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0004h) ON
T = GS Clock ´ 1d T = GS Clock ´ 1d

¼
¼

T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0041h) ON
T = GS Clock ´ 1d T = GS Clock ´ 1d
¼

T = GS Clock ´ 1d
¼

T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0080h) ON
T = GS Clock ´ 1d T = GS Clock ´ 1d T = GS Clock ´ 1d
T = GS Clock ´ 2d T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0081h) ON
T = GS Clock ´ 1d T = GS Clock ´ 2d T = GS Clock ´ 1d
T = GS Clock ´ 2d T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0082h) ON
¼

T=
¼

GS Clock ´ 511d
T = GS Clock ´ 511d in 2nd to 128th Periods
OUTXn OFF
(GS Data = FF80h) ON

T = GSCLK ´ 512d
T = GS Clock ´ 511d in 2nd to 128th Periods
OUTXn OFF
(GS Data = FF81h) ON
¼

T= T=
¼

GS Clock ´ 512d T = GS Clock ´ 512d in 2nd to 63rd and 65th to 127th Periods, GS Clock ´ 511d
T = GS Clock ´ 511d in 64th Period
OUTXn OFF
(GS Data = FFFEh) ON
T= T=
GS Clock ´ 512d GS Clock ´ 511d
T = GS Clock ´ 512d in 2nd to 127th Periods
OUTXn OFF
(GS Data = FFFFh) ON

Figure 27. ES-PWM Operation

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8.5.4 Register and Data Latch Configuration

The TLC5971 has a 224-bit shift register and a 218-bit data latch that set grayscale (GS) data, global brightness
control (BC), and function control (FC) data into the device. When the internal latch pulse is generated and the
data of the six MSBs in the shift register are 25h, the 218 following data bits in the shift register are copied into
the 218-bit data latch. If the data of the six MSBs is not 25h, the 218 data bits are not copied into the 218-bit data
latch. The data in the data latch are used for GS, BC, and FC functions. Figure 28 shows the shift register and
the data latch configuration.
224-Bit Shift Register

MSB LSB
Write Write Write Write Write Write Write Write Write Write SDTI
SDTO Command ¼ Command Data Data Data Data ¼ Data Data Data Data
Bit 5 Bit 0 Bit 217 Bit 216 Bit 215 Bit 214 Bit 3 Bit 2 Bit 1 Bit 0 SCKI
223 218 217 216 215 214 3 2 1 0

218
6 218-Bit Data Latch

MSB LSB
Internal
6-Bit Write OUT EXT TMG DSP OUTR0 OUTR0 OUTR0 OUTR0 Latch Pulse
Command TMG GCK RST RPT
¼ Bit 3 Bit 2 Bit 1 Bit 0
Decoder
217 216 215 214 3 2 1 0

Write Command = 25h (100101b)

26 192 The internal latch pulse is generated

after eight periods between the last
2 SCKI rising edges with no input.
To the three groups of 7-bit BC, To GS timing control circuit.
PWM timing control, GS clock counter,
and clock select circuit.

Figure 28. Common Shift Register and Control Data Latch Configuration

8.5.4.1 224-Bit Shift Register

The 224-bit shift register is used to input data from the SDTI pin with the SCKI clock into the TLC5971. The
shifted data in this register is used for GS, BC, and FC. The six MSBs are used for the write command. The LSB
of the register is connected to the SDTI pin and the MSB is connected to the SDTO pin. On each SCKI rising
edge, the data on SDTI are shifted into the register LSB and all 224 bits are shifted towards the MSB. The
register MSB is always connected to SDTO. When the device is powered up, the data in the 224-bit shift register
is not set to any default value.

8.5.4.2 218-Bit Data Latch

The 218-bit data latch is used to latch the GS, BC, and FC data. The 218 LSBs in the 244-bit shift register are
copied to the data latch when the internal latch pulse is generated with the 6-bit write command, 25h (100101b).
When the device is powered up, the data in the latch are not reset except for BLANK (bit 213) which is set to 1 to
force all outputs off. Therefore, GS, BC, and FC data must be set to the proper values before BLANK is set to 0.
The 218-bit data latch configuration is shown in Figure 29 and the data bit assignment is shown in Table 5.

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From LSB-side of 224-bit shift register.

218
218-Bit Data Latch

MSB LSB
217 216 215 214 213 212-206 205-199 198-192 191 176 31 16 15 0

OUTTMG EXTCLK TMGRST DSPRPT BLANK BC Data BC Data BC Data

OUTB3 ¼ OUTB3 ¼ OUTG0 ¼ OUTG0 OUTR0 ¼ OUTR0
1= 1= 1= 1= 1= Bits 6-0 Bits 6-0 Bits 6-0
Bit 15 Bit 0 Bit 15 Bit 0 Bit 15 Bit 0
Rising Edge External Reset Repeat Blank for BLUE for GREEN for RED

Function Control Data (5 Bits) BC Data for OUTRn/Gn/Bn GS Data for OUTB3 GS Data for OUTG0 GS Data for OUTR0
(7 Bits ´ 3 = 21 Bits) (16 Bits) (16 Bits) (16 Bits)

5 21 192

To function control (FC) circuit. To global brightness control (BC) circuit. To grayscale timing control (GS) circuit.

Figure 29. 218-Bit Data Latch Configuration

Table 5. Data Latch Bit Assignment

BIT NUMBER BIT NAME CONTROLLED CHANNEL/FUNCTIONS
15-0 GSR0 GS data bits 15 to 0 for OUTR0
31-16 GSG0 GS data bits 15 to 0 for OUTG0
47-32 GSB0 GS data bits 15 to 0 for OUTB0
63-48 GSR1 GS data bits 15 to 0 for OUTR1
79-64 GSG1 GS data bits 15 to 0 for OUTG1
95-80 GSB1 GS data bits 15 to 0 for OUTB1
111-96 GSR2 GS data bits 15 to 0 for OUTR2
127-112 GSG2 GS data bits 15 to 0 for OUTG2
143-128 GSB2 GS data bits 15 to 0 for OUTB2
159-144 GSR3 GS data bits 15 to 0 for OUTR3
175-160 GSG3 GS data bits 15 to 0 for OUTG3
191-176 GSB3 GS data bits 15 to 0 for OUTB3
198-192 BCR BC data bits 6 to 0 for OUTR0-3
205-199 BCG BC data bits 6 to 0 for OUTG0-3
212-206 BCB BC data bits 6 to 0 for OUTB0-3
Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank).
When this bit is 0, all constant-current outputs (OUTR0-OUTB3) are controlled by the GS PWM timing
213 BLANK
controller. When this bit is 1, all constant-current outputs are forced off. The GS counter is reset to 0,
and the GS PWM timing controller is initialized. When the IC is powered on, this bit is set to 1.
Auto display repeat mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is 0, the auto repeat function is disabled. Each constant-current output is only turned on
214 DSPRPT once, according the GS data after BLANK is set to 0 or after the internal latch pulse is generated with
the TMGRST bit set to 1. When this bit is 1, each output turns on and off according to the GS data
every 65536 GS reference clocks.
Display timing reset mode enable bit in FC data (0 = disabled, 1 = enabled).
When this bit is 1, the GS counter is reset to 0 and all constant-current outputs are forced off when the
internal latch pulse is generated for data latching. This function is the same when BLANK is set to 0.
215 TMGRST
Therefore, BLANK does not need to be controlled by an external controller when this mode is enabled.
When this bit is 0, the GS counter is not reset and no output is forced off even if the internal latch pulse
is generated.
GS reference clock select bit in FC data (0 = internal oscillator clock, 1 = SCKI clock).
216 EXTGCK When this bit is 1, PWM timing refers to the SCKI clock. When this bit is 0, PWM timing refers to the
internal oscillator clock.
GS reference clock edge select bit for OUTXn on-off timing control in FC data (0 = falling edge, 1 =
rising edge).
217 OUTTMG
When this bit is 1, OUTXn are turned on or off at the rising edge of the selected GS reference clock.
When this bit is 0, OUTXn are turned on or off at the falling edge of the selected clock.

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8.5.5 Internal Latch Pulse Generation Timing

The internal latch pulse is generated when the SCKI rising edge does not change for 8x the period between the
last SCKI rising edge and the second to last SCKI rising edge if the data of the six MSBs in the 244-bit shift
register are the command code 25h. The generation timing changes as a result of the SCKI frequency with the
time range between 16384 times the internal oscillator period (2.74 ms), maximum, and 8x the internal oscillator
period (666 ns), minimum. Figure 30 shows the internal latch pulse generation timing.
The internal latch pulse is generated when the SCKI rising edge is not input during 8 times of
Period A if the 6-bit data of the MSB-side in the 244-bit shift register is the command code 25h.

SCKI

1 2 3 4 ¼ N-3 N-2 N-1 N

The next SCKI clock should start after 8 or more

Period A clock periods (1.34 ms, min) of the internal clock
Latch Pulse from the internal latch pulse generation timing.
(Internal)

Write command 25h + 218-bit data.

224-Bit Shift
Register Data
(Internal)

218-Bit
218-bit data are copied from shift register
Data Latch when the internal latch is generated.
(Internal)

Figure 30. Data Latch Pulse Generation Timing

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The device is a 12-channel, constant sink current, LED driver. This device can be connected in series to drive
many LED lamps with only a few controller ports. Functional control data and PWM control data can be written
from the SDI and SCK input terminal. The PWM timing reference clock can be chosen from the internal
oscillation or external SCK signal.

9.2 Typical Application

VCC
Power
Supply
(6 V to 17 V) GND

Device Optional Device Optional

GND VCC GND VCC
1 mF 1 mF
VREG OUTR0 VREG OUTR0

IREF OUTG0 IREF OUTG0

¼

¼
OUTG3 OUTG3

OUTB3 OUTB3

DATA SDTI SDTO SDTI SDTO

(1)
Controller CLK SCKI SCKO SCKI SCKO

GND

The output voltage range is from 0 V to 3.3 V.

NOTE: The number of LEDs in series changes, depending on the VCC voltage.

Figure 31. Typical Application Circuit Example (Internal Linear Regulator Using VCC = 6 V to 17 V)

9.2.1 Design Requirements

For this design example, use Table 6 as the input parameters.

Table 6. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VCC Input Voltage Range 3 V to 5.5 V
LED Lamp (VLED) Input Voltage Range Maximum 17 V
SIN, SCLK, LAT and GSCLK Voltage Range Low Level = GND, High Level = VCC

9.2.2 Detailed Design Procedure

9.2.2.1 Define Basic Parameters

To begin the design process, a few parameters must be decided as following"
• Maximum output constant-current value for each color LED lamp
• Maximum LED forward voltage (Vf) and maximum VLED
• Total LEDs and Cascaded IC Number

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9.2.2.2 Data Input Sequence

224-bit data packets are sent through single-wire interface for the PWM control of three output channels. Select
the BC data, FC data and write the GS data to the register following the signal timing.

9.2.2.3 How to Control the TLC5971

To set each function mode, BC color, GS output, 6-bit write command, 5-bit FC data, 21-bit BC data for each
color group, and 192-bit GS data for OUTXn, a total number of 224 bits must be written into the device.
Figure 32 shows the 224-bit data packet configuration.
When N units of the TLC5971 are cascaded (as shown in Figure 33), N × 224 bits must be written from the
controller into the first device to control all devices. The number of cascaded devices is not limited as long as the
proper voltage is supplied to the device at VCC. The packets for all devices must be written again whenever the
data in one packet is changed.
MSB LSB

Write Function BC for BC for BC for GS for GS for GS for GS for GS for GS for
16 Bits
Command Control BLUE GREEN RED OUTB3 OUTG3 OUTR3 OUTB0 OUTG0 OUTR0
´6
(6 bits, 25h) (5 bits) (7 bits) (7 bits) (7 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits)

Figure 32. 224-Bit Data Packet Configuration

VLED

¼ ¼ ¼ ¼
3.3 V

Controller VCC VCC VCC VCC

DATA SDTI SDTO SDTI SDTO SDTI SDTO SDTI SDTO

CLK SCKI SCKO SCKI SCKO SCKI SCKO SCKI SCKO

GND IREF VREF IREF VREF IREF VREF IREF VREF

1st 2nd N-1st Nth
TLC5971 TLC5971 TLC5971 TLC5971
GND GND GND GND

Figure 33. Cascading Connection of N TLC5971 Units

9.2.2.3.1 Data Write and PWM Control with Internal Grayscale Clock Mode
When the EXTCLK bit is 0, the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-
3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at
low frequencies. The data and clock timing is shown in Figure 3 and Figure 34. A writing procedure for the
function setting and display control follows:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The
first six bits of the 224-bit data packet are used as the write command. The write command must be 25h
(100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch.
The EXTCLK bit must be set to 0 for the internal oscillator mode. Also, the DSPRPT bit should be set to 1 to
repeat the PWM timing control and BLANK set to 0 to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 ×
N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last
SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.

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VLED Power The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
MSB LSB MSB LSB MSB LSB
Shift Data From 224-Bit Packet 224-Bit Packet for for 224-Bit Packet 224-Bit Packet Next
Controller (SDTI) for Nth TLC5971 for N-1st TLC5971 N-2’th 3’rd for 2nd TLC5971 for 1st TLC5971 Data
MSB LSB MSB LSB MSB

Shift Clock From Next

224 Shift Clocks 224 Shift Clocks 224 Shift Clocks 224 Shift Clocks
Controller (SCKI) Shift Clock

Latch Pulse
(Internal)

PWM Control Start

OUTXn
or data updated

The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.

Figure 34. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)

9.2.2.3.2 Data Write and PWM Control with External Grayscale Clock Mode
When the EXTCLK bit is 1, the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-
3) as the GS reference clock. This mode is ideal for video image applications that change the display image with
high frequencies or for certain display applications that must synchronize all TLC5971s. The data and clock
timing are shown in Figure 3 and Figure 35. A writing procedure for the display data and display timing control
follows:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six
bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b);
otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK
bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so that the
PWM control is not repeated, the TMGRST bit should be set to 1 to reset the PWM control timing at the
internal latch pulse generation, and BLANK must be set to 0 to start the PWM control.
3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N.
After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI
rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices.
5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34 µs or more from step 4.
The OUTXn are turned on when the output GS data are not 0000h.
6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized
with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
7. Repeat step 2 to step 6 for the next display period.

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VLED Power
The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
MSB LSB MSB LSB MSB
Shift Data From 224-Bit Packet for for 224-Bit Packet 224-Bit Packet
Controller (SDTI) for Nth TLC5971 N-1st 2nd for 1st TLC5971 Low for Nth TLC5971
MSB LSB

Shift Clock From 224 Shift

Controller (SCKI) 224 Shift Clocks 224 Shift Clocks 65536 Shift Clocks as GS Clock Clocks

Latch Pulse
(Internal)

OUTXn is controlled via the PWM

OUTXn synchronized with SCKI.

The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.

Figure 35. Data Packet and Display Start/Update Timing 2 (External Clock Mode)

There is another control procedure that is recommended for a long chain of cascaded devices. The data and
clock timings are shown in Figure 3 and Figure 36. When 256 TLC5971 units are cascaded, use the following
procedure:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to 1.
2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The
EXTCLK bit must be set to 1 for the external oscillator mode. Also, the DSPRPT bit should be set to 0 so
that the PWM control does not repeat, the TMGRST bit should be set to 1 to reset the PWM control timing
with the internal latch pulse, and BLANK must be set to 0 to start the PWM control.
3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256).
After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between
the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift
resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34 µs or more from step 3 (or step
7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI
clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and
one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for
PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and
the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-
bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.

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VLED Power The next shift clock should start after 1.34 ms or more from the internal latch pulse generation timing.
Timing clock for 1st display and
MSB LSB MSB LSB Timing clock for 1st display. 2nd display data write.
Shift Data From 224-Bit Packet for for for 224-Bit Packet 256 ´ 224-Bit Packet for
Low Low
Controller (SDTI) 256th TLC5971 255th 2nd for 1st TLC5971 256th TLC5971
MSB LSB

Shift Clock From 8192 57344 (256 ´ 224) Shift Clock

224 Shift Clocks 224 Shift Clocks for 2nd Display
Controller (SCKI) Shift Clocks Shift Clocks

224 ´ 256 = 57344 Clocks 65536 Clocks 65536 Clocks

Latch Pulse
(Internal)

OUTXn is controlled via the PWM synchronized 2nd Display

OUTXn OFF with SCKI for 1st dis playperiod. OFF Period

The time is 8 periods between the last SCLK rising edge and the second to last SCLK rising edge.
The wait time changes between 2.74 ms and 666 ns, depending on the period of the shift clock.

Figure 36. Data Packet and Display Start/Update Timing 3

(External Clock Mode With 256 Cascaded Devices)

9.2.3 Application Curve

Figure 37. Output Waveform With GS Data Latch Input

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9.3 System Examples

VCC
Power
Supply
(3 V to 5.5 V) GND

Device Optional Device Optional

GND VCC GND VCC

VREG OUTR0 VREG OUTR0

IREF OUTG0 IREF OUTG0

¼
OUTG3 OUTG3

VCC OUTB3 OUTB3

(1) DATA SDTI SDTO SDTI SDTO

Controller
CLK SCKI SCKO SCKI SCKO

GND

(1) The output operating voltage range is from 0 V to VCC.

Figure 38. Typical Application Circuit Example (Direct Power Supplying VCC = 3 V to 5.5 V)

VLED
Power
Supply
(15 V) GND

VCC
Power
Supply
(3 V to 5.5 V) GND

Device Optional Device Optional

GND VCC GND VCC

VREG OUTR0 VREG OUTR0

IREF OUTG0 IREF OUTG0

¼

¼
OUTG3 OUTG3

VCC OUTB3 OUTB3

(1) DATA SDTI SDTO SDTI SDTO

Controller
CLK SCKI SCKO SCKI SCKO

GND

(1) The output operating voltage range is from 0 V to VCC.

Figure 39. Typical Application Circuit Example

(Direct Power Supplying VCC = 3 V to 5.5 V, VLED = 15 V)

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10 Power Supply Recommendations

The VCC power supply voltage should be decoupled by placing a 0.1-uF ceramic capacitor close to VCC pin and
GND plane. Depending on panel size, several electrolytic capacitors must be placed on board equally distributed
to get a well regulated LED supply voltage (VLED). VLED voltage ripple should be less than 5% of its nominal
value.

11 Layout

11.1 Layout Guidelines

1. Place the decoupling capacitor near the VCC pin and GND plane.
2. Route the GND pattern as widely as possible for large GND currents.
3. Connecting wire between the chained ICs should be as short as possible to reduce wire inductance.

11.2 Layout Example

Figure 40. Layout Example

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12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 33

Product Folder Links: TLC5971
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Jun-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TLC5971PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971
& no Sb/Br)
TLC5971PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971
& no Sb/Br)
TLC5971RGER ACTIVE VQFN RGE 24 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
& no Sb/Br) 5971
TLC5971RGET ACTIVE VQFN RGE 24 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
& no Sb/Br) 5971

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Jun-2018

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Oct-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC5971PWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TLC5971RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TLC5971RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Oct-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC5971PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TLC5971RGER VQFN RGE 24 3000 367.0 367.0 35.0
TLC5971RGET VQFN RGE 24 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4204104/H
 PACKAGE OUTLINE
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

4.1 A
B
3.9

4.1
PIN 1 INDEX AREA 3.9

1 MAX C

SEATING PLANE
0.05
0.00 0.08 C

2X 2.5 (0.2) TYP

7 12

20X 0.5
6
13

2X 25 SYMM
2.5

1 18
PIN 1 ID 24X 0.30
0.18
(OPTIONAL) 24 19 0.1 C A B
SYMM
24X 0.48
0.28
0.05 C
4219016 / A 08/2017
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
(3.825)

( 2.7)
24 19

24X (0.58)

24X (0.24)
1
18
20X (0.5)

SYMM 25
(3.825)

2X
(1.1)
TYP

6 13

(R0.05)

7 12
2X(1.1)
SYMM

LAND PATTERN EXAMPLE

SCALE: 20X

0.07 MAX 0.07 MIN

ALL AROUND METAL ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK

DEFINED SOLDER MASK
(PREFERRED) DEFINED

SOLDER MASK DETAILS

4219016 / A 08/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGE0024H VQFN - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(3.825)

4X ( 1.188)
24 19

24X (0.58)
24X (0.24)
1
18
20X (0.5)

SYMM (3.825)
(0.694)
TYP

6 13

(R0.05) TYP 25

METAL
TYP 7 12
(0.694)
TYP
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
78% PRINTED COVERAGE BY AREA
SCALE: 20X

4219016 / A 08/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..

www.ti.com
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