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Batch 2 Solution

The document describes a Verilog code assignment to design a 8:1 multiplexer using behavioral and structural modeling. It provides the code for a 4:1 and 2:1 multiplexer module with active low enable. The 8:1 multiplexer is constructed by instantiating the 4:1 and 2:1 multiplexer modules. A testbench is also provided to simulate the 8:1 multiplexer for different input combinations and select lines, and display the output waveform and in a textual format.

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Jeswin Eldho
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28 views2 pages

Batch 2 Solution

The document describes a Verilog code assignment to design a 8:1 multiplexer using behavioral and structural modeling. It provides the code for a 4:1 and 2:1 multiplexer module with active low enable. The 8:1 multiplexer is constructed by instantiating the 4:1 and 2:1 multiplexer modules. A testbench is also provided to simulate the 8:1 multiplexer for different input combinations and select lines, and display the output waveform and in a textual format.

Uploaded by

Jeswin Eldho
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS


FIRST SEMESTER, 2018-2019
VERILOG EVALUATION-I, DIGITAL DESIGN (CS F215/ECE F215/EEE F215/INSTR F215)

Open Book Maximum Marks: 10 Date 23.09.2018

Task: Write a verilog code for 4:1 multiplexer and 2:1 multiplexer, both having active low enable inputs,
using behavioral modeling. From these multiplexer and gates, construct 8:1 multiplexer using structural
modeling. Write a testbench to show the output for following input combinations. Also show the textual
output with $monitor command.
8 bit input on input lines of 8:1 multiplexer=(01110011)2
(a) Enable=1 , select lines (000)2
(b)Enable=1 , select lines (011)2
(c) Enable=0 , select lines (000)2
(d) Enable=0 , select lines (011)2
(e) Enable=0 , select lines (110)2
Solution
module mux 4 1 ( o u t p u t reg O, i n p u t [ 1 : 0 ] S , i n p u t [ 3 : 0 ] I , i n p u t E ) ;
always @( S , E , I )
case ( {E , S} )
3 ’ b000 : O= I [ 0 ] ;
3 ’ b001 : O= I [ 1 ] ;
3 ’ b010 : O= I [ 2 ] ;
3 ’ b011 : O= I [ 3 ] ;
d e f a u l t : O=1 ’ b0 ;
endcase
endmodule
module mux 2 1 ( o u t p u t reg O, i n p u t S , i n p u t [ 1 : 0 ] I , i n p u t E ) ;
always @( S , E , I )
case ( {E , S} )
2 ’ b00 : O= I [ 0 ] ;
2 ’ b01 : O= I [ 1 ] ;
d e f a u l t : O=1 ’ b0 ;
endcase
endmodule
module mux 8 1 ( o u t p u t O, i n p u t [ 2 : 0 ] S , i n p u t [ 7 : 0 ] I , i n p u t E ) ;
w i r e [ 1 : 0 ] OS;
mux 4 1 m1(OS[ 0 ] , S [ 1 : 0 ] , I [ 3 : 0 ] , E ) ;
mux 4 1 m2(OS[ 1 ] , S [ 1 : 0 ] , I [ 7 : 4 ] , E ) ;
mux 2 1 m3(O, S [ 2 ] , OS[ 1 : 0 ] , E ) ;
endmodule

module tb mux 8 1 ;
reg [ 2 : 0 ] S ;
reg [ 7 : 0 ] I ;
reg E ;
w i r e O;
Digital Design (CS F215/ECE F215/EEE F215/INSTR F215) Page 2 of 2
mux 8 1 M1(O, S , I , E ) ;
initial
begin
I =8 ’ b01110011 ; E=1 ’ b1 ; S=3 ’ b000 ;
#20 E=1 ’ b1 ; S=3 ’ b011 ; I =8 ’ b01110011 ;
#20 E=1 ’ b0 ; S=3 ’ b000 ; I =8 ’ b01110011 ;
#20 E=1 ’ b0 ; S=3 ’ b011 ; I =8 ’ b01110011 ;
#20 E=1 ’ b0 ; S=3 ’ b110 ; I =8 ’ b01110011 ;
#20 E=1 ’ b0 ; S=3 ’ b110 ; I =8 ’ b01110011 ;
end
initial
begin
$display ( ” time E S [ 2 : 0 ] I [ 7 : 0 ] O” ) ;
$ m o n i t o r (”%0d %b %b %b %b ” , $time , E , S , I , O ) ;
end
i n i t i a l #140 $ f i n i s h ;
endmodule
Textual Result
# time E S[2:0] I[7:0] O
#0 1 000 01110011 0
# 20 1 011 01110011 0
# 40 0 000 01110011 1
# 60 0 011 01110011 0
# 80 0 110 01110011 1
Waveform Result

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