High-Level Synthesis -III

Virendra Singh Design

Indian Institute of Science

Computer

& Test
Laboratory

Bangalore
[email protected]

E0-285: CAD of VLSI Systems

 Resource Sharing
Resource sharing: Assignment of resource to more
than one operation
Goal: Reduce area
Resource binding: explicit definition of mapping
between resources and operation
Two or more operation may be bound to the same
resource if they are not concurrent and they can be
implemented by the resources of the same type
• Compatible operations

Design

Computer
Sep 2,2009 E0-285@SERC 2

& Test
Laboratory
 Scheduled Sequencing
Graph
NOP

1 2
TIME 1 * * + 10

TIME 2 3 * 6
* < 11

TIME 3 4 -
7
* * 8

TIME 4
5 - + 9

NOP
Design

Computer
Sep 2,2009 E0-285@SERC 3

& Test
Laboratory
 Compatibility Graph

3 1 8 10
4

5 11
7 6 2

Design

Computer
Sep 2,2009 E0-285@SERC 4

& Test
Laboratory
 Conflict Graph

3 1 8 10
4

5 11
7 6 2

Design

Computer
Sep 2,2009 E0-285@SERC 5

& Test
Laboratory
 Scheduled and Bound
Sequencing Graph
(1,2) NOP (2,1)
(1,1)
1 2
TIME 1 * * + 10

TIME 2 3 * 6
* < 11

TIME 3 4 -
7
* * 8

TIME 4
5 - (2,2)
+ 9

NOP
Design

Computer
Sep 2,2009 E0-285@SERC 6

& Test
Laboratory
 Resource Sharing in Non-
Hierarchical Seq. Graph
ILP Formulation
Ø All operations and resources have the same type
Ø Use binary decision variable with two indices
v B= {bir; i = 1,2,…, nop; r = 1,2, .. a}
Ø A set of binary decision constants with two indices
v X = {xil, i = 1,2, .., nop; l = 1,2, .., λ+1}
Ø bir is 1 only when vi is bound to resource r
Ø xil is 1 only when vi starts in step l
Design

Computer
Sep 2,2009 E0-285@SERC 7

& Test
Laboratory
Resource Sharing in Non-
Hierarchical Seq. Graph
ILP Formulation
Each operation should be assigned to one and only
one resource
Σr=1a bir = 1, i= 1,2, …., nop
At most one operation can be executing, among those
assigned to resource r, at any time step
Σi=1 nop bir Σm=l-di+1 l xim ≤ 1
bir Є {0, 1}
Design

Computer
Sep 2,2009 E0-285@SERC 8

& Test
Laboratory
Resource Sharing in Non-
Hierarchical Seq. Graph
Two operations (Multiplier type, ALU type)
Unit Delay
Resource 1
Σr=1a1 bir = 1, T (vi) = 1
Σi bir xil ≤ 1
Resource 2
Σr=1a2 bir = 1, T (vi) = 2
Σi bir xil ≤ 1
Design

Computer
Sep 2,2009 E0-285@SERC 9

& Test
Laboratory
Resource Sharing in Non-
Hierarchical Seq. Graph
a1 = 1
Find solution of
bi1 = 1, for all i Є {1,2,3,6,7,8}
Σi Є {1,2,3,6,7,8} bi1 xil ≤ 1, l = 1,2, …., 5

Solution does not exists

b1,1 + b2,1 ≤ 1
Contradict with the first
Design

Computer
Sep 2,2009 E0-285@SERC 10

& Test
Laboratory
Resource Sharing in Non-
Hierarchical Seq. Graph
a1 = 2
Find solution of
bi1 + bi2 = 1, for all i Є {1,2,3,6,7,8}
Σi Є {1,2,3,6,7,8} bi1 xil ≤ 1, l = 1,2, …., 5
Σi Є {1,2,3,6,7,8} bi2 xil ≤ 1, l = 1,2, …., 5

Solution
b1,1 = 1, b2,2 =1 , b3,1 = 1, b6,2 = 1, b7,1 = 1, b8,2 =1

Design

Computer
Sep 2,2009 E0-285@SERC 11

& Test
Laboratory
 Scheduled and Bound
Sequencing Graph
(1,2) NOP (2,1)
(1,1)
1 2
TIME 1 * * + 10

TIME 2 3 * 6
* < 11

TIME 3 4 -
7
* * 8

TIME 4
5 - (2,2)
+ 9

NOP
Design

Computer
Sep 2,2009 E0-285@SERC 12

& Test
Laboratory
 Register Binding
• Registers hold values of variables
v Lifetime
Ø Lifetime can be data dependent – branching
Ø Implementation that associates a register with each
variable is suffice
v Inefficient
Ø Variables that are alive in different interval can share
the same register
Ø Compatible
Design

Computer
Sep 2,2009 E0-285@SERC 13

& Test
Laboratory
 Register Sharing
Construct compatibility or conflict graph
1 2
TIME 1 * *
z1 z2 z1 z2
z1 z2

TIME 2 3 * 6
z4
*
z3 z3 z4 z3 z4

TIME 3 4 -z5
7
*
z6

TIME 4
5 - z5 z6 z5 z6

Variable interval Conflict Graph

Design

Computer
Sep 2,2009 E0-285@SERC 14

& Test
Laboratory
 Register Sharing
xl = x + dx
x u dx y x dx ul = u – (3*x*u*dx) – (3*y*dx)
u dx c = xl < a
3
1 2

1 * * + 10
x
3 a
z1 z2 xl z1 z2

2 3 * z4
6 * < 11
u
y
z3 dx

3
u

4 - 7
* y * 8 c
z3 z4
x
z6 z7
z5

4 5 - + 9
z5 z6 z7

ul yl u y
Design

Computer
Sep 2,2009 E0-285@SERC 15

& Test
Laboratory
 Register Sharing
u

z1 z2

x z3 z4 y

z5 z6

z7

Conflict Graph
Design

Computer
Sep 2,2009 E0-285@SERC 16

& Test
Laboratory
 Multi-port Memory Binding
• Multi-port memory arrays to store the values of variable
• Assume memory with a ports (either read or write) - GPRF
• Large memory - to hold all data
Ø Computing minimum number of memory ports a
required to access as many variables as needed
Ø If each variable access the memory through the
same port
Ø Functional resource binding
Ø Ports can be seen as interface resources
Design

Computer
Sep 2,2009 E0-285@SERC 17

& Test
Laboratory
 Multi-port Memory Binding
• If variables can be accessed through different port
• Minimum port – maximum number of concurrent access
• Max ∑i=1nvar xil
• Dual Problem
Ø Assume fix number of ports and maximize the
number of variables to be stored, subject to port
limitation
v Max 1Tb s.t.
v ∑i bi xil ≤ a
Design

Computer
Sep 2,2009 E0-285@SERC 18

& Test
Laboratory
 Multi-port Memory Binding
• Scheduled sequence of operations
• Step 1: z3 = z1+z2; z12 = z1
• Step 2: z5 = z3+z4; z7 = z3 * z6; z13 = z3
• Step 3: z8 = z3+z5; z9 = z1 + z7; z11 = z10/z5

• Step 4: z4 = z11^z8; z15 = z12 ^ z9; z11

• Step 5: z1 = z14 ; z2 = z15

Ø b1+b2 + b3 + b12 ≤ a

Design

Computer
Sep 2,2009 E0-285@SERC 19

& Test
Laboratory
 Multi-port Memory Binding
• b1+b2 + b3 + b12 ≤ a

• b3+b4 + b5 + b6 + b7 + b13 ≤ a

• b1+ b3+b5 + b7 + b8 + b9 + b10 + b11 ≤ a

• b8+ b9+b11 + b12 + b14 + b15 ≤ a

• b1+ b2+b14 + b15 ≤ a

Design

Computer
Sep 2,2009 E0-285@SERC 20

& Test
Laboratory
Multi-port Memory Binding

• for a =1
Ø {b2 , b4 , b8} are non-zero

•For a = 2
Ø{b2 , b4 , b5 , b10 , b12 , b14 } are non zero

•For a = 3
Ø{b1, b2 , b4 , b6 , b8 , b10 , b12, b13, b14 } are non zero

Design

Computer
Sep 2,2009 E0-285@SERC 21

& Test
Laboratory
 Bus Sharing
• Act as transfer resources the t feed data to functional
resources
• Operation of writing specific bus
• Vertex in SG
• Conflict and compatibility graph can be generated
• Alternate
• Bus may not be described in SG
• Usage can be derived from exploiting timing of data
transfer
Design

Computer
Sep 2,2009 E0-285@SERC 22

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Laboratory
 Bus Sharing
• Problems
• Minimum number of buses
• Maximum number of data transfer that can done
through given number of buses

Design

Computer
Sep 2,2009 E0-285@SERC 23

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Laboratory
 Bus Sharing and Binding

1 2 Ø b1 + b2 ≤ a
TIME 1 * * Ø b3 + b4 ≤ a
z1 z2

TIME 2 3 * 6
z4
* Ø b5 + b6 ≤ a
z3

TIME 3 4 -z5
7
*
z6

TIME 4
5 -
Design

Computer
Sep 2,2009 E0-285@SERC 24

& Test
Laboratory
 Concurrent Scheduling
and Binding
Concurrent Scheduling and Binding
Ø Define upper bound on resource usage and
latency

Problems
v Intractable problem

Design

Computer
Sep 2,2009 E0-285@SERC 25

& Test
Laboratory
 Concurrent Scheduling
and Binding
ILP Formulation
1. Start time of each operation is unique
Σl xil = 1
2. Sequencing relations represented by Gs(V,E) must be
satisfied
Σl l. xil ≥ Σl l. xjl + dj
3. Resource bound must be met at every schedule step
Σk Σm xim ≤ ak

Design

Computer
Sep 2,2009 E0-285@SERC 26

& Test
Laboratory
 Concurrent Scheduling
and Binding

4. Operation has to bound one and only one resource

Σr bir = 1
5. Operation bound to same resource must not be
concurrent
l
Σi bir Σ xim ≤ 1
m = l-d i+1

Latency: λ = ∑l l. xnl - ∑l l. x0l

Minimize area and latency simultaneously
Design

Computer
Sep 2,2009 E0-285@SERC 27

& Test
Laboratory
 ILP Formulation
NOP
All operation must
start only once
x6,1 + x6,2 = 1
1
*
2
* 6
* * 8 + 1
0

x0,1 = 1 * 7 * + 9 < 1
x7,2 + x7,3 = 1
3
1

4 -
x1,1 = 1
x8,1 + x8,2+x8,3 = 1 5 -

x2,1 = 1
NOP

x9,2 + x9,3+x9,4 = 1
x3,2 = 1
x10,1 + x10,2+x10,3 = 1
x4,3 = 1
x11,2 + x11,3+x11,4 = 1
x5,4 = 1
xn,5 = 1
Design

Computer
Sep 2,2009 E0-285@SERC 28

& Test
Laboratory
 ILP Formulation
Constraints – based on sequencing
(more than one starting time for at least one operation)
2 x7,2 + 3 x7,3 – x6,1 – 2 x6,2 – 1 ≥ 0
2 x9,2 + 3 x9,3 + 4 x9,4 – x8,1 – 2 x8,2 – 3 x8,3 – 1 ≥ 0
2 x11,2 + 3 x11,3 + 4 x11,4 – x10,1 – 2 x10,2 – 3 x10,3 – 1 ≥ 0
4 x5,4 – 2 x7,2 – 3 x7,3 – 1 ≥ 0
5 xn,5 – 2 x9,2 – 3 x9,3 – 4 x9,4 – 1 ≥ 0
5 xn,5 – 2 x11,2 – 3 x11,3 – 4 x11,4 – 1 ≥ 0
Design

Computer
Sep 2,2009 E0-285@SERC 29

& Test
Laboratory
 ILP Formulation
NOP
Resource Constraints
x1,1 + x2,2 + x6,1 + x8,1 ≤ a1
1
*
2
* 6
* * 8 + 1
0

3
* 7 * + 9 < 1
x3,2 + x6,2 + x7,2 + x8,2 ≤ a1 1

4 -
x7,3 + x8,3 ≤ a1 5 -
NOP

x10,1 ≤ a2
x9,2 + x10,2 + x11,2 ≤ a2
x4,3 + x9,3 + x10,3 + x11,3 ≤ a2
x5,4 + x9,4 +x11,4 ≤ a2
Design

Computer
Sep 2,2009 E0-285@SERC 30

& Test
Laboratory
 ILP Formulation
NOP
Resource Bind
b1,1 + b2,1 + b3,1 + b6,1 + b7,1 + b8,1 = 1
1
*
2
* 6
* * 8 + 1
0

* 7 * + 9 <
b1,2 + b2,2 + b3,2 + b6,2 + b7,2 + b8,2 = 1 3 1
1

4 -
5 -
NOP
b1,a1 + b2,a1 + b3,a1 + b6,a1 + b7,a1 + b8,a1 = 1

Design

Computer
Sep 2,2009 E0-285@SERC 31

& Test
Laboratory
 THANK YOU

Design

Computer
Sep 2,2009 E0-285@SERC 32

& Test
Laboratory