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Procesamiento Digital de Señales: Renán Antonio González Espinosa

This document summarizes a report on a digital signal processing practice. It includes: 1) A truth table analyzing Boolean logic functions. 2) A behavioral VHDL program implementing one of the logic functions from the truth table. 3) A structural VHDL program for the same logic function using AND, OR, and INV gates. 4) A process-based VHDL program for the logic function, along with timing analyses of the different VHDL implementations.

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RENAN ANTONIO GONZALEZ ESPINOSA
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47 views8 pages

Procesamiento Digital de Señales: Renán Antonio González Espinosa

This document summarizes a report on a digital signal processing practice. It includes: 1) A truth table analyzing Boolean logic functions. 2) A behavioral VHDL program implementing one of the logic functions from the truth table. 3) A structural VHDL program for the same logic function using AND, OR, and INV gates. 4) A process-based VHDL program for the logic function, along with timing analyses of the different VHDL implementations.

Uploaded by

RENAN ANTONIO GONZALEZ ESPINOSA
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Procesamiento digital de señales

Reporte Práctica 2

Alumno:
Renán Antonio González Espinosa

Primer punto es la forma de la tabla 1de Boole

TABLA INV(NOT) AND AND AND FUNCION(OR)


A2
# A1 A2 A3 A4 NEGADO A1A2 (A2NEG)A3 A1A2A4 F=(A1A2)+(A2NEG)A3+(A1A2A4)
1 0 0 0 0 1 0 0 0 0
2 0 0 0 1 1 0 0 0 0
3 0 0 1 0 1 0 1 0 1
4 0 0 1 1 1 0 1 0 1
5 0 1 0 0 0 0 0 0 0
6 0 1 0 1 0 0 0 0 0
7 0 1 1 0 0 0 0 0 0
8 0 1 1 1 0 0 0 0 0
9 1 0 0 0 1 0 0 0 0
10 1 0 0 1 1 0 0 0 0
11 1 0 1 0 1 0 1 0 1
12 1 0 1 1 1 0 1 0 1
13 1 1 0 0 0 1 0 0 1
14 1 1 0 1 0 1 0 1 1
15 1 1 1 0 0 1 0 0 1
16 1 1 1 1 0 1 0 1 1

Punto 2 el programa tipo Behavorial en VHDL

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using


-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating


-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pracren is
Port ( A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
A4 : in STD_LOGIC;
F1 : out STD_LOGIC);
end pracren;
architecture estructural of pracren is
begin
F1<= (A3 and ( not A2 )) or (A2 and A1) or (A4 and A2 and A1);
end estructural;

reporte del tiempo

Data Sheet report:


-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A1 |F1 | 5.879|
A2 |F1 | 6.050|
A3 |F1 | 5.930|
---------------+---------------+---------+

Analysis completed Tue Sep 25 15:45:57 2018


--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings

Peak Memory Usage: 175 MB

Esta es la imagen 1 con las compuertas


Imagen 1

Punto 3 el programa de ESTRUCTURA


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity caso2ren is
Port ( A1 : in STD_LOGIC;
A2 : in STD_LOGIC;
A3 : in STD_LOGIC;
A4 : in STD_LOGIC;
F : out STD_LOGIC);

end caso2ren;

architecture structural of caso2ren is


component AND2 port(o: out std_logic;
i0,i1: in std_logic);
end component;

component AND3 port(o: out std_logic;


i2,i1,i0: in std_logic);
end component;

component INV port(o: out std_logic;


I: in std_logic );
end component;

component OR3 port(o: out std_logic; i2,i1,i0: in std_logic); end component;


signal a5, a6, a7, a8: std_logic;
-- Declaracion de compononentes .
begin -- empieza tu programa
-- llamas a tus componentes o subrutinas
u0: AND2 port map (o=>a8, i1=>A1, i0=>A2);--(A=>A2,B=>B2,Z=>f2);
u1: INV port map (o=>a7, I=>A2);
u2: AND2 port map (o=>a5, i1=>a7,i0=>A3);
u3: AND3 port map (o=>a6, i1=>A2, i0=>A1, i2=>A4);
u4: OR3 port map (o=>F , i2=>a5, i1=>a8, i0=>a6);
end structural;

Tiempo utilizado en las entradas

Data Sheet report:


-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A1 |F | 6.305|
A2 |F | 6.281|
A3 |F | 6.216|
---------------+---------------+---------+

Analysis completed Tue Sep 25 15:18:00 2018


--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings

Peak Memory Usage: 174 MB


Insertamos la imagen 2

Imagen 2

Para el punto 4 caso que se trabaja es el programa de PROCESO este es el programa

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity practica4 is

port(
A1: in std_logic ;
A2: in std_logic ;
A3: in std_logic ;
A4: in std_logic ;
f1: out std_logic);

end;
architecture prosecution of practica4 is

begin

process (A1,A2,A3,A4)

begin
if ((A3='1' and ( not A2='1' )) or (A2='1' and A1='1') or (A4='1' and A2='1' and A1='1')) then
f1<='1';
else
f1<='0';
end if;
end process;

end prosecution;

tiempo de utilizado en el procesamiento

Data Sheet report:


-----------------
All values displayed in nanoseconds (ns)

Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
A1 |f1 | 6.305|
A2 |f1 | 6.281|
A3 |f1 | 6.216|
---------------+---------------+---------+

Analysis completed Tue Sep 25 15:52:38 2018


--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings

Peak Memory Usage: 174 MB

Imagen 3 con la forma de conectar los componentes,


Imagen 3

La corrida de 3 simulaciones de las salidas F en la imagen 4

Imagen 4

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