ECE 2300

Digital Logic & Computer Organization

Spring 2018

More Single Cycle Microprocessor

Lecture 16: 1
 Announcements
• HW6 due tomorrow

• Prelim 2: Tues April 17, 7:30pm, 101 Phillips Hall

– Coverage: Lectures 8~16
– Inform instructor ASAP to resolve schedule conflict
– An old exam will be released after spring break
– Review sessions
• Friday April 13, 4:30-6:00pm, PHL 219
• Monday April 16, 7:00-8:30pm, PHL 203

Lecture 16: 2
 Control Word Example
Fm … F0
DR RF DataA
SA M_address
SB LD
IMM DataB ALU RAM
SA 0 Data_in 0
MB SB 1
V FS 1
DR
C MD
D_in SE VCZN
N LD MW MD
Z MW
MB
CU IMM

DR SA SB IMM MB FS MD LD MW

R2 <= R0 + R1 010 000 001 x 0 ADD 0 1 0

R1 <= M[R2] 001 010 xxx 0 1 ADD 1 1 0

M[R2] <= R0 xxx 010 000 0 1 ADD x 0 1

R3 <= R1 – 3 011 001 xxx 3 1 SUB 0 1 0

Lecture 16: 3
 Unsigned Multiplication
• Form each partial product by multiplying a
single digit of the multiplier by the multiplicand
• Add shifted partial products to get result
multiplicand ( = 5) 101
multiplier ( = 3) x 011
101
partial
101
products 000
result ( = 15) 01111

Lecture 16: 4
 Revisit Sequential Multiplication
• Multiply A2A1A0 by B2B1B0
A 2A 1A 0 R1 <= M[0] // load A from M[0]
B 2B 1B 0 R2 <= M[1] // load B from M[1]
(A2A1A0)ÎB0 R3 <= 0 // initialize R3 (P) = 0
(A2A1A0) ÎB1
(A2A1A0) ÎB2 (*) R4 <= R2 & 1 // R4 = lsb(B)
P4 P3 P2 P1 P0 R2 <= SRL(R2) // shift B right
if (R4) R3 <= R3+R1 // if lsb(B)=1, P=P+A
R1 <= SLL(R1) // shift A left
if (R2) goto (*) // repeat until B=0

M[2] <= R3 // store P to M[2]

Multiply A=101 by B=011: R1 R2 R3 R4

Determine the values of R1~R4
after each loop iteration

Lecture 16: 5
 Instruction Sequence
R1 <= M[0] R0 <= R0-R0 S1
R1 <= M[R0] S2
R2 <= M[1] R2 <= M[R0 + 1] S3
R3 <= 0 R3 <= R3-R3 S4
R4 <= R2 & 1 R4 <= R2 & 1 S5
R2 <= SRL(R2) R2 <= SRL(R2) S6 R2 != 0
R3 <= R3 + R1 R3 <= R3 + R1 R4 = 0 S7
R1 <= SLL(R1) R1 <= SLL (R1) S8
M[2] <= R3 M[R0 + 2] <= R3 S9

Lecture 16: 6
 FSM for Sequential Multiplication
DR SA SB IMM MB FS MD LD MW
S1 R0 <= R0-R0 000 000 000 x 0 SUB 0 1 0
S2 R1 <= M[R0] 001 000 xxx 0 1 ADD 1 1 0
S3 R2 <= M[R0 + 1] 010 000 xxx 1 1 ADD 1 1 0
S4 R3 <= R3-R3 011 011 011 x 0 SUB 0 1 0
S5 R4 <= R2 & 1 100 010 xxx 1 1 AND 0 1 0
S6 R2 <= SRL(R2) 010 010 xxx x x SRL 0 1 0
S7 R3 <= R3 + R1 011 011 001 x 0 ADD 0 1 0
S8 R1 <= SLL(R1) 001 001 xxx x x SLL 0 1 0
S9 M[R0 + 2] <= R3 xxx 000 011 2 1 ADD x 0 1

Start=0
R4=0
R2=0
0 1 2 3 4 5 6 7 8 9
Start=1 R4=1
R2≠0
Lecture 16: 7
 Programmable Control Unit
• Datapath (RF, ALU, RAM, muxes) is flexible

• However, FSM-based multiplier control unit is

“hardwired”
– New operation sequence would require new state
machine

• Programmable Control Unit

– Control words stored in RAM
– State machine replaced by a Program Counter plus
branch operations
– Flexible: Can run different sequences of control
words (programs)
Lecture 16: 8
 Program Counter (PC)
• Special register that points to the location (address) in
RAM of the next control word

• Updated every clock cycle

• Sequential execution (default behavior)

– Control words read from sequential RAM locations
– PC is increased by 1 after each control word read

• Branch operations
– Special control flow operations
– Condition code determines whether to branch or not
– If so, next RAM address is PC + branch offset

Lecture 16: 9
 PC-Based Control Unit
1 Adder
Fm … F0
DR
SA
RF
DataA M_address
SB
LD ALU
IMM DataB RAM
MB SA 0 Data_in 0
SB 1
PC FS
DR
1
MD VCZN
D_in SE
LD MW MD
MW
MB
RAM IMM

PC+1 DR SA SB IMM MB FS MD LD MW
R0 <= R0 – R0 1: 000 000 000 x 0 SUB 0 1 0
R1 <= M[R0] 2: 001 000 xxx 0 1 ADD 1 1 0
R2 <= M[R0+1] 3: 010 000 xxx 1 1 ADD 1 1 0
R3 <= R3 – R3 4: 011 011 011 x 0 SUB 0 1 0

Lecture 16: 10
Instruction Sequence of Sequential Multiplication
R1 <= M[0] R0 <= R0-R0 S1
R1 <= M[R0] S2
R2 <= M[1] R2 <= M[R0 + 1] S3
R3 <= 0 R3 <= R3-R3 S4
R4 <= R2 & 1 R4 <= R2 & 1 S5
R2 <= SRL(R2) R2 <= SRL(R2) S6 R2 != 0
R3 <= R3 + R1 R3 <= R3 + R1 R4 = 0 S7
R1 <= SLL(R1) R1 <= SLL (R1) S8
M[2] <= R3 M[R0 + 2] <= R3 S9

Lecture 16: 11
 Branch Operations
• Used to jump to a different part of the program

• Consists of a condition and an offset

• Condition
– Checks to see whether the result of the last
instruction met a specified criteria, such as
• Zero (Z = 1), Negative (N = 1)

• Offset
– How far ahead, or back, to jump within the program
if the condition is met

Lecture 16: 12
 Branch Operations
Branch Operations
+1 0 0
0 1 1
+1 +1Adder0 1 Z
Z’
2
SE(OFF) 3 MP
N 4
1 MP
SE(OFF) Adder N’ 5
! MP
Fm … F0 C 6
DR RF V 7 BS
DataA Fm … F0
DR SA ! M_address
SA SB
RF
LD DataA ALU
SBIMM DataB M_address RAM
LD SA 0 Data_in 0
IMM MB ALU RAM
PC MB FS SA SB DataB 0 1 Data_in 0 1
SB DR 1
PC FS MD
DR D_in
1
VCZN
MD LD SE
D_in SE VCZN
MB MW MD
LDMW MW MD
ROM
MW BS IMMMB
BSOFF IMM
OFF
ROM
RAM
0 0
1 1
Z 2
Z’ 3
N 4 MP
N’ 5
C 6
V 7
BS
Lecture 16: 13
Lecture
 Branch Operations 0 0
1 1
Z
+1 Z’
2
0 3 MP
1 N 4
SE(OFF) Adder N’ 5
C 6
MP V 7 BS
Fm … F0
DR
SA
RF
DataA M_address
SB
LD ALU
IMM DataB RAM
MB SA 0 Data_in 0
SB 1
PC FS
DR
1
MD VCZN
D_in SE
LD MW MD
MW
MB
BS IMM
OFF
RAM
DR SA SB IMM MB FS MD LD MW BS OFF
R2 <= SRL(R2) 5: 010 010 xxx x x SRL 0 1 0 000 x
if (R4=0) goto 8 6:
R3 <= R3 + R1 7: 011 011 001 x 0 ADD 0 1 0 000 x
R1 <= SLL(R1) 8: 001 001 xxx x x SLL 0 1 0 000 x

Lecture 16: 14
 Branch Operations 0 0
1 1
Z
+1 Z’
2
0 3 MP
1 N 4
SE(OFF) Adder N’ 5
C 6
MP V 7 BS
Fm … F0
DR
SA
RF
DataA M_address
SB
LD ALU
IMM DataB RAM
MB SA 0 Data_in 0
SB 1
PC FS
DR
1
MD VCZN
D_in SE
LD MW MD
MW
MB
BS IMM
OFF
RAM
DR SA SB IMM MB FS MD LD MW BS OFF
R1 <= SLL(R1) 8: 001 001 xxx x x SLL 0 1 0 000 x
if (R2≠0) goto 4 9:
M[R0+2] <= R3 10: 010
xxx 000 011 2 1 ADD x 0 1 000 x

Lecture 16: 15
 Programmable Multiplication
DR SA SB IMM MB FS MD LD MW BS OFF
0: R0 <= R0-R0 000 000 000 x 0 SUB 0 1 0 000 x
1: R1 <= M[R0] 001 000 xxx 0 1 ADD 1 1 0 000 x
2: R2 <= M[R0 + 1] 010 000 xxx 1 1 ADD 1 1 0 000 x
3: R3 <= R3-R3 011 011 011 x 0 SUB 0 1 0 000 x
4: R4 <= R2 & 1 100 010 xxx 1 1 AND 0 1 0 000 x
5: R2 <= SRL(R2) 010 010 xxx x x SRL 0 1 0 000 x
6: if (R4=0) goto 8 xxx 100 xxx 0 1 SUB x 0 0 010 2
7: R3 <= R3 + R1 011 011 001 x 0 ADD 0 1 0 000 x
8: R1 <= SLL(R1) 001 001 xxx x x SLL 0 1 0 000 x
9: if (R2≠0) goto 4 xxx 010 xxx 0 1 SUB x 0 0 011 -5
10:M[R0+2] <= R3 xxx 000 011 2 1 ADD x 0 1 000 x

Lecture 16: 16
 Providing Even More Flexibility
DR
SA
SB
• Replace control words with IMM
MB
instructions PC FS
MD
– More intuitive and not specific to LD
MW
particular hardware BS
OFF
– Shorter than control words RAM
– Instruction decoder (hardwired logic)
creates the control words from the
instruction DR

Inst. RAM
SA

Decoder
SB

PC
IMM
MB
FS
MD
LD
MW
BS

Lecture 16: 17
 Assembly Language
• Human readable version of instructions

ADD rd,rs,rt // R[rd] = R[rs] + R[rt]

Src Reg
Src Reg
Dest Reg Function
Operation
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Lecture 16: 18
 Register to Register Format (R-type)
Register to Register Format

• ALU operations with two source registers

•• Shift
ALUoperations
operations with two
(arithmetic source
and logical) registers
•• NOP
Shiftand
operations
HALT
– Logical: Shift in a 0
– Arithmetic: Shift in the sign bit Lecture 16: 19
 Logical and Arithmetic Right Shift
• Logical Right Shift
– Shifts each bit right by 1 position
– 0 shifted into MSB

• Arithmetic Right Shift

– Preserves the sign bit
• Example: 11010000 SRA => 11101000
– Equivalent to division by 2 (for two’s complement)

Lecture 16: 20
 Immediate Format (I-type)
Immediate Format

• ALU instructions with an immediate operand

• • ALU
Load instructions with an immediate
and Store instructions operand
• Load
– LB, and Store
SB: Load instructions
or store a byte (8 bits)
– LW, SW: Load or store a word (16 bits)
– LB, SB: Load or store a byte (8 bits)
• Branch instructions
– LW, SW: Load or store a word (16 bits) Lecture 16: 21
 Memory Operations
• The smallest addressable quantity in modern memory is
typically a byte (8 bits)
– A memory address points to a particular byte location

• LB : Load a byte
– “give me the byte at this address”

• LW : Load a word, which in our case is two bytes

– “give me the byte at this address and the next one too”

Lecture 16: 22
 Branch Instructions
Branch Instructions
Target address

• Condition
• Condition
– Test two registers for equality (BEQ, BNE)
– Test two registers for equality (BEQ, BNE)
– Test if a register is positive or negative (BGEZ, BLTZ)
– Test if a register is positive or negative (BGEZ, BLTZ
• !Target address
• Target
– Where to jump in the program if the condition is true
– Formed
– Where by adding
to jump theprogram
in the offset to the PC condition is true
if the
– Formed by adding the offset to the PC
Lecture 16: 23
 Branch Instructions
Forming the Branch Target Address

• A memory address
• Condition
points to a byte location
+1 0
1
Adder
– Test two registers for equality SE(OFF)
(BEQ, BNE)
• If instructions are MP
– Test if a register is positive or negative (BGEZ, BLTZ
2 bytes wide
!– Instructions are located at
+2
even locations (0, 2, 4, ...)
• Target
0
1
– The PC must be incremented SE({OFF,0}) Adder
– Where to jump in the program if the conditionMPis true
by 2 (PC+2)
– Since the offset refers to the number of instructions (not bytes) to
– Formed by adding the offset to the PC
jump, we must append a 0 to it

Lecture 16: 24
 Multiplication Revisited
OP RS RT RD FUNCT
L0: SUB R0,R0,R0 1111 000 000 000 001
L1: LB R1,0(R0) 0010 000 001 000000
L2: LB R2,1(R0) 0010 000 010 000001
L3: SUB R3,R3,R3 1111 011 011 011 001
L4: ANDI R4,R2,1 0110 010 100 000001
L5: SRL R2,R2 1111 010 xxx 010 011
L6: BEQ R4,R0,L8 1000 000 100 000010
L7: ADD R3,R3,R1 1111 011 001 011 000
L8: SLL R1,R1 1111 001 xxx 001 100
L9: BNE R2,R0,L4 1001 000 010 111011
L10: SW R3,2(R0) 0011 000 010 000010

Lecture 16: 25
 Before Next Class
• H&H 7.5.1-7.5.2

Next Time

Pipelined Microprocessor

Lecture 16: 26