ECE 2300

Digital Logic & Computer Organization

Spring 2018

More Pipelined Microprocessor

Lecture 19: 1
 Announcements

•  Prelim 2 tonight, 7:30-9:00pm, PHL 101

Lecture 19: 2
 Example: Branch Delay Slot
BEQ R2,R3,X
NOP
OR R4,R1,R3
X: AND R6,R1,R2
ADDI R7,R2,3
SUB R6,R2,R2
...

•  Can you identify one instruction to fill the branch

delay slot?

Lecture 19: 3
 Review: Load Instructions and Forwarding
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9

A
LW R1,0(R2) IM Reg L DM Reg
U

A
OR R4,R1,R3 IM Reg L DM Reg
U

A
SUB R5,R2,R1 IM Reg L DM Reg
U

A
AND R6,R1,R2 IM Reg L DM Reg
U

A
ADDI R7,R7,3 IM Reg L DM Reg
U

Lecture 19: 4
 Pipeline Control Unit (CU)
Control
CU Signals

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB V C Z N
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

Lecture 19: 5
 Pipeline Control Requirements
•  Generate control signals for each stage
–  IF: PCJ
–  EX: MB, F
–  MEM: MW, MD
–  WB: LD

•  Detect forwarding conditions and generate MUX control

signals

•  Detect data hazards and insert pipeline bubbles

–  Assumes no load delay slot defined in ISA

•  Assume branch delay slot defined in ISA

Lecture 19: 6
 Generating Control for Each Stage
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

Lecture 19: 7
 Forwarding Unit (Partial)
MUX controls

ID.SA MEM.R-type
ID.SB MEM.DR
ID.R-type Forwarding
EX.SA Unit WB.R-type
EX.SB WB.DR
EX.R-type
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

Lecture 19: 8
 R-type to R-type Forwarding
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9

A
ADD R1,R2,R3 IM Reg L DM Reg
U

A
OR R4,R1,R3 IM Reg L DM Reg
U

A
SUB R5,R2,R1 IM Reg L DM Reg
U

A
AND R6,R1,R2 IM Reg L DM Reg
U

•  MEM➞EX : MEM.DR == (EX.SA || EX.SB)

•  WB➞EX : (1) WB.DR == (EX.SA || EX.SB) and
(2) there is no forwarding from MEM➞EX in this cycle
•  WB➞ID : WB.DR == (ID.SA || ID.SB)

Lecture 19: 9
 R-type to R-type Forwarding
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9

A
ADD R1,R2,R3 IM Reg L DM Reg
U

A
OR R1,R1,R3 IM Reg L DM Reg
U

A
SUB R5,R2,R1 IM Reg L DM Reg
U

A
AND R6,R1,R2 IM Reg L DM Reg
U

A
ADDI R7,R1,3 IM Reg L DM Reg
U

Lecture 19: 10
 R-type to R-type Forwarding
•  MEM➞EX
–  MEM.DR == (EX.SA || EX.SB)

•  WB➞EX
–  WB.DR == (EX.SA || EX.SB) and
–  MEM.DR != (EX.SA || EX.SB)

•  WB➞ID
–  WB.DR == (ID.SA || ID.SB)

Lecture 19: 11
 R-type to Branch Forwarding
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9

A
ADD R1,R2,R3 IM Reg L DM Reg
U

A
OR R4,R6,R3 IM Reg L DM Reg
U

A
BGEZ R1,X IM Reg L DM Reg
U

A
AND R6,R5,R2 IM Reg L DM Reg
U

A
X:ADDI R7,R7,3 IM Reg L DM Reg
U

•  Other forwarding conditions to handle as well

Lecture 19: 12
Pipeline with Fwding + Branch HW in ID
Control
CU Signals

=?
sign bit

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

Lecture 19: 13
 Data Hazards Requiring Bubbles
•  Occur when instructions are too close together for
forwarding to work

•  Requires adding bubbles in the pipeline

•  Data hazard conditions to detect and handle

–  Load followed by R-type
–  Load followed by I-type ALU instruction
–  Load followed by Load
–  Load followed by Store (two cases)
–  Load followed by Branch
–  ALU instruction followed by Branch

Lecture 19: 14
 Example: Data Hazards w/ Forwarding
•  Assume HW forwarding and NO delay slot for load

•  Identify all data hazards in the following instruction

sequences by circling each source register that is read
before the updated value is written back
LW R2, 0(R1)
ADDI R3, R2, 1
BEQ R2, R1, X
SW R3, 4(R1)
X: …

Lecture 19: 15
 Load Followed by R-type Instruction
CC1 CC2 CC3 CC4 CC5 CC6 CC7

A
LW R1,0(R2) IM Reg L DM Reg
U

A
OR R4,R1,R3 IM Reg bubble L DM Reg
U

if (EX.Load && ID.R-type) { // Inst in EX is a Load and inst in ID is R-type

if (EX.DR == (ID.SA || ID.SB)) { // DR of Load matches SA or SB of inst in ID
Insert NOP into EX in next cycle // Insert bubble
Don’t Load IF/ID in next cycle // Hold instruction in ID for a cycle
Don’t Load PC in next cycle // Hold instruction in IF for a cycle
}
}

Lecture 19: 16
 Load Followed by R-type Instruction

IM Reg DM Reg
LW R1,0(R2)
A
OR R4,R1,R3 L
SUB R5,R2,R1
AND R6,R1,R2 U

LW R1,0(R2)

Lecture 19: 17
 Load Followed by R-type Instruction

IM Reg DM Reg
LW R1,0(R2)
A
OR R4,R1,R3 L
SUB R5,R2,R1
AND R6,R1,R2 U

OR R4,R1,R3 LW R1,0(R2)

Lecture 19: 18
 Load Followed by R-type Instruction

IM Reg DM Reg
LW R1,0(R2)
A
OR R4,R1,R3 L
SUB R5,R2,R1
AND R6,R1,R2 U

SUB R5,R2,R1 OR R4,R1,R3 LW R1,0(R2)

Detect hazard

Lecture 19: 19
 Load Followed by R-type Instruction

IM Reg DM Reg
LW R1,0(R2)
A
OR R4,R1,R3 L
SUB R5,R2,R1
AND R6,R1,R2 U

SUB R5,R2,R1 OR R4,R1,R3 NOP LW R1,0(R2)

Insert bubble
Hold these
instructions

Lecture 19: 20
 Load Followed by R-type Instruction

IM Reg DM Reg
LW R1,0(R2)
A
OR R4,R1,R3 L
SUB R5,R2,R1
AND R6,R1,R2 U

AND R6,R1,R2 SUB R5,R2,R1 OR R4,R1,R3 NOP LW R1,0(R2)

Pipeline continues normally

R1 value forwarded from WB to EX and ID

Lecture 19: 21
 Hazard Detection Unit (Partial)
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD

SE
IF/ID ID/EX EX/MEM MEM/WB

PCL IF/IDL Clear

Hazard EX.DR
ID.SA Detection ‘Clear’ puts 0 into ID/EX
ID.SB
ID.R-type Unit EX.Load

Lecture 19: 22
 Pipeline with Datapath and Control
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD

SE
IF/ID ID/EX EX/MEM MEM/WB

PCL IF/IDL Clear MUX controls

Hazard EX.DR
ID.SA Detection ID.SA MEM.R-type
ID.SB ID.SB
ID.R-type Unit EX.Load Forwarding MEM.DR
ID.R-type
EX.SA Unit WB.R-type
EX.SB WB.DR
EX.R-type Lecture 19: 23
 Load Followed by Branch Instruction
CC1 CC2 CC3 CC4 CC5 CC6 CC7

A
LW R1,0(R2) IM Reg L DM Reg
U

BEQ R4,R1,X IM bubble Reg

A
L
DM
bubble
U

Two bubbles are needed

•  Also need to handle Load followed by branch

two instructions apart

Lecture 19: 24
 R-type to Store Forwarding
CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9

A
SUB R3,R1,R2 IM Reg L DM Reg
U

A
SW R3,4(R1) IM Reg L DM Reg
U

A
ADD R4,R3,R2 IM Reg L DM Reg
U

Lecture 19: 25
 Pipeline without Forwarding for Store
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

R[SB] not forwarded

Lecture 19: 26
Slight Pipeline Improvement for Stores
PCJ CU
=? LD
MW, MD
sign bit MB, F

Adder
+2 Fm … F0 Data
M
RF U M
RAM
M LD X
P U
Decoder

U Inst SA X M
C M ALU
X RAM SB
M
U U
DR X D_IN
U
X
M
U
X
PCJ X MB
D_in MW MD
PCL
SE
IF/ID ID/EX EX/MEM MEM/WB

R[SB] forwarded from MEM or WB

Lecture 19: 27
 Next Time
•  H&H 8-8.3

Caches

Lecture 19: 28