ECE 410 Homework 5 -Solutions Spring 2008

Problem 1
A pn junction is constructed by diffusing phosphorus (n-type) into a p-type silicon substrate doped at NA
= 1015 cm-3. The cross sectional area of the junction is 10µm2.
a) Assuming a one-sided step junction is formed, calculate the minimum phosphorus doping
concentration (ND) that will ensure the junction capacitance is less than 1fF with no reverse bias.
b) If the calculated value of ND is impractically high and must be reduced, will that increase or decrease
the junction capacitance?
c) Will the junction capacitance increase or decrease if a reverse bias is applied?

solution:
a) ND must be greater than NA because the n-type is diffused into the p-type. Because it’s
a one-sided step junction, ND >> NA , and thus we can write the junction capacitance as
⎛ ⎞
1
⎡ qε N A ⎤ 2
⎜ 1 ⎟
C j = A⎢ ⎥
⎣ 2 ⎦ ⎜ Ψ +V ⎟
⎝ 0 R ⎠
Because VR = 0, the only unknown is Ψ0, which is a function of the ND we are looking for.
To simply the algebra, let’s define
1
⎡ qεN A ⎤ 2 C j0 C j0
C j0 = A⎢ ⎥ , thus C j = =
⎣ 2 ⎦ Ψ0 + V R Ψ0
Solving for Ψ0 we get
2
⎛ C j0 ⎞ ⎛ ⎞
Ψ0 = ⎜ ⎟ = VT ln⎜ N A N D ⎟⎟ and the only unknown is the ND we are looking for.
⎜C ⎟ ⎜ n2
⎝ j ⎠ ⎝ i ⎠
Now we do the math…
1 1
⎡ qεN A ⎤ 2 ⎡1.6 × 10 −19 × 11.8 × 8.85 × 10 -14 (1015 ) ⎤ 2
C j0 = A⎢ ⎥ = 10 × 10 −8 ⎢ ⎥ = 9.14 x10 −16
⎣ 2 ⎦ ⎣ 2 ⎦
2
⎛ C j0 ⎞ ⎛ 9.14 x10 −16 ⎞
2
⎜ ⎟ ⎜ ⎟
⎛N N ⎞ ⎜ C ⎟ ⎜ 1x10 −15 ⎟
ln⎜⎜ A 2 D ⎟⎟ = ⎝ j ⎠ =⎝ ⎠ 0.835
= = 33.4
V 0.025
⎝ ni ⎠ T 0.025
NAND 3.2 x1014 • ni2
2
= e = 3.2 x10 and thus N D =
33.4 14
= 6.73x1019
ni NA
which is possible, but impractically high since the concentration of silicon is only ~1020.

b) decreasing ND will decrease Ψ0 and therefore increase junction capacitance

c) applying reverse bias will increase the depletion layer thickness, thus separating the
charge and decreasing junction capacitance.

1
Problem 2
A pMOS transistor has W/L=10 with process parameters k’p = 30μA/V2 and Vtp = -0.6V. For
each of the cases below, identify the region of operation (cutoff, triode, saturation). Assume VSB
= 0V and VDD = 3V.
a) VSG = 1V, VSD = 3V
b) VSG = 3V, VSD = 2V
c) VSG = 0.5, VSD = 1V

solution:
The regions of operation for a pMOS transistor are defined as
Again, let’s first define the regions
Cut Off Saturation Tiode
VSD < |Vtp| VSD > Vsat = (VSG –|Vtp|) VSD < Vsat = (VSG –|Vtp|)
ID = 0 ID = βp/2 (VSG –|Vtp|)2 ID = βp/2 [2(VSG –|Vtp|) VSD - VSD 2]
Since W & L are constant, calculate βp = k’p (W/L) = 30(10) = 300μA/V2

(a) VSG = 1V, VSD = 3V

Vsat = (VSG –|Vtp|) = 0.4V ; VSD > Vsat = (VSG –|Vtp|); saturation region
ID = βp/2 (VSG –|Vtp|)2 = 150 (0.4)2 = 24µA
(b) VSG = 3V, VSD = 2V
Vsat = (VSG –|Vtp|) = 2.4V ; VSD < Vsat = (VSG –|Vtp|); triode region
ID = βp/2 [2(VSG –|Vtp|) VSD - VSD 2] = 150 [2(2.4)(2) – (2)2] = 840µA
(c) VSG = 0.5V, VSD = 1V
VSG <|Vtp|) so the device is turned off; cutoff region
ID = 0µA

Problem 3
A pMOS transistor with a channel length modulation factor of λ=0.05V-1 is sized so that it has a
drain current of ID=15μA when VSD = VSG-|Vtp|.
a) Accounting for channel length modulation what is the drain current if the drain voltage VD
drops by 2.5V? Note: you do have all the information needed.
b) Recognizing that the output resistance is defined as the change in drain voltage relative to the
change in drain current, calculate the output resistance in the saturation (active) region.

solution
a) At the onset of saturation, I D = μ n COX W (VGS − Vtn ) 2 . With channel length modulation,
2 L
μ n COX W
ID = (VGS − Vtn ) 2 (1 + λ (VDS − (VGS − Vtn ))
2 L
Thus, the ratio of currents for these two cases is just 1 + λ (VDS − (VGS − Vtn) =
1+0.05(2.5) = 1.125, and the new ID = 16.875μA.

∂VDS
b) ro = = 1 = 1 = 1.333MΩ
∂I D (15μA.λ.ΔVd ) 15μA.0.05

2
Problem 4
A pMOS transistor of W=3μm and L=0.6μm has parameters tox = 500nm, surface mobility μp
=200 cm2 /V-sec and threshold voltage Vtp = -0.6V. VDD = 3V.
a) Calculate the transistor transconductance, βp.
b) Estimate the channel resistance, Rp, at VSG=VDD.
c) If the lateral diffusion parameter is LD=0.05μm, what is the effective channel length?
d) What is the percentage change in Rp using the effective channel length rather than the
drawn length?

solution:
(a) The gate oxide capacitance per unit area is
ε 3.6(8.85 × 10 −14 )
C OX = OX = −7
= 6.9nF/cm2
t OX 500 × 10

The transistor transconductance is

βp = μpCox (W/L) = (200)(6.9n)(3/0.6) = 6.9μA/V2

(b) Rp = 1 / (βp (VDD - ⏐Vtp ⏐)) = 1 / (6.9u (3 – 0.6)) = 144/86kΩ

(c) We don’t have enough information to determine the depletion component, so we

must assume it can be ignored. The effective channel length is therefore
Leff = L – 2 LD = 0.6μm – 2(0.05μm) = 0.5μm

(d) Since Rp is linearly (and inversely) proportional to β and β is linearly (and

inversely) proportional to L, we can setup a ratio to calculate the new ‘effective’ Rp.
Rp (eff ) βp Leff Leff
= = ⇒ Rp (eff ) = Rp
Rp β p eff L L
The percentage of change from Rp to Rp(eff) can be expressed as

Rp(eff ) − Rp Rp Leff − Rp ⎛ Leff ⎞ ⎛ 0.5 ⎞

%change = 100 = 100 L = 100⎜ − 1⎟ = 100⎜ − 1⎟ = -16.67%
Rp Rp ⎝ L ⎠ ⎝ 0.6 ⎠
where the negative sign reflects that the resistance has decreased.

3
Problem 5 0.5um
The simplified layout of a pMOS transistor in a 0.5μm process is shown here 1um 1um
with the “actual” fabricated dimensions. Determine the device parasitics
below using the following process model values:
k’p =90μA/V2, |Vtp| = 0.5V, Cox = 1.8fF/μm2 , Cj = 0.75fF/μm2 2um
and Cjsw = 0.25 fF/μm
a) What is the gate capacitance, CG?
b) What is the gate-to-drain capacitance, CGD?
c) What is the drain-to-bulk capacitance, CDB?
d) What is the total capacitance at the drain node?
e) If the drain node RC time constant is 4psec, what is channel resistance?

solution:
a) CG = Cox (W L) = (1.8fF/μm2) (2μm) (0.5μm) = 1.8fF

b) CGD = ½ CG = ½ (2f) = 0.9fF

c) CDB = Cj ADbot + CjSW PDSW

ADbot = 2μm x 1μm =2μm2
PDSW = 2 (2μm + 1μm) = 6μm
CDB = Cj ADbot + CjSW PDSW = 0.75f (2) + 0.25f (6) = 3fF

d) Total capacitance at the drain node is

CD = CGD + CDB = 0.9 + 3 = 3.9fF

e) τ = Rn CD Æ Rn = τ/CD = 4p/3.9f = 1,025 Ω