LM 5030
LM 5030
LM 5030
LM5030
SNVS215D – APRIL 2003 – REVISED NOVEMBER 2015
VIN VOUT
LM5030
VIN OUT1
VCC OUT2
CS
COMP
RT VFB
ISOLATED
FEEDBACK
SS GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5030
SNVS215D – APRIL 2003 – REVISED NOVEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 13
2 Applications ........................................................... 1 8 Application and Implementation ........................ 14
3 Description ............................................................. 1 8.1 Application Information............................................ 14
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 14
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 20
6 Specifications......................................................... 4 10 Layout................................................................... 20
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 20
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 20
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 21
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 21
6.5 Electrical Characteristics........................................... 5 11.2 Documentation Support ....................................... 21
6.6 Typical Characteristics .............................................. 8 11.3 Community Resources.......................................... 21
7 Detailed Description ............................................ 10 11.4 Trademarks ........................................................... 21
7.1 Overview ................................................................. 10 11.5 Electrostatic Discharge Caution ............................ 21
7.2 Functional Block Diagram ....................................... 10 11.6 Glossary ................................................................ 21
7.3 Feature Description................................................. 11 12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
1 10
VIN SS
2 9
VFB RT
3 8
COMP CS
4 7
VCC GND
5 6
OUT1 OUT2
Pin Functions
PIN
I/O DESCRIPTION APPLICATION INFORMATION
NAME NO.
There is an internal 5-kΩ pullup resistor on this pin. The
COMP 3 O Output to the error amplifier
error amplifier provides an active sink.
Current sense input for current mode control and current
limit sensing. Using separate dedicated comparators, if CS
CS 8 I Current sense input exceeds 0.5 V, the outputs will go into cycle-by-cycle
current limit. If CS exceeds 0.625 V the outputs will be
disabled and a softstart commenced.
GND 7 — Return Ground
OUT1 5 O Output of the PWM controller Alternating PWM output gate driver
OUT2 6 O Output of the PWM controller Alternating PWM output gate driver
An external resistor sets the oscillator frequency. This pin
Oscillator timing resistor pin and
RT 9 I will also accept synchronization pulses from an external
synchronization input
oscillator.
A 10-µA current source and an external capacitor set the
softstart timing length. The controller will enter a low power
SS 10 I Dual purpose soft start and shutdown pin
state if the SS pin is pulled below the typical shutdown
threshold of 0.45 V.
VIN 1 I Source input voltage Input to start-up regulator. Input range 14 to 100 V.
The non-inverting input is internally connected to a 1.25-V
VFB 2 I Inverting input to the error amplifier
reference.
Output from the internal high-voltage series If an auxiliary winding raises the voltage on this pin above
VCC 4 I/O pass regulator. The regulation setpoint is the regulation setpoint, the internal series pass regulator
7.7 V. will shutdown, reducing the IC power dissipation.
The exposed die attach pad on the WSON package should
be connected to a PCB thermal pad at ground potential.
WSON
SUB — Die substrate For additional information on using TI's No Pull Back
DAP
WSON package, refer to WSON Application Note AN-1187
(SNOA401).
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN to GND (Survival) –0.3 100 V
VCC to GND (Survival) –0.3 16 V
RT to GND (Survival) –0.3 5.5 V
All other pins to GND (Survival) –0.3 7 V
Power dissipation Internally Limited
Lead temperature (soldering 4 seconds) 260 °C
Operating junction temperature 150 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
(2) Typical numbers represent the most likely parametric norm for 25°C operation.
16 10
14 9
8
12
7
10
6
VCC (V)
VCC (V)
8 5
6 4
3
4
2
2
1
0 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 18 20
202.5
OSCILLATOR FREQUENCY (kHz)
202.0
201.5
201.0
200.5
200.0
199.5
100 199.0
1 10 100
-50 0 50 100 150
RT (K:) o
TEMPERATURE ( C)
Figure 3. Oscillator Frequency vs RT
Figure 4. Oscillator Frequency vs Temperature RT = 26.7 kΩ
10.7 160
10.6
155
10.5
10.4
150
DEADTIME (ns)
10.3
ISS (PA)
10.2 145
10.1
140
10.0
9.9
135
9.8
9.7 130
-50 0 50 100 150 -50 0 50 100 150
o o
TEMPERATURE ( C) TEMPERATURE ( C)
Figure 5. Softstart Current vs Temperature Figure 6. Deadtime vs Temperature
7 Detailed Description
7.1 Overview
The LM5030 high-voltage PWM controller contains all of the features needed to implement push-pull and bridge
topologies, using current-mode control in a small 10-pin package. Features included are, start-up regulator, dual
mode current limit, dual alternating gate drivers, thermal shutdown, softstart, and slope compensation. This high
speed IC has total propagation delays < 100 ns. The functional block diagram of the LM5030 is shown in
Functional Block Diagram.
The LM5030 is designed for current-mode control converters that require alternating outputs, such as push-pull
and half- and full-bridge topologies. The features included in the LM5030 enable all of the advantages of current-
mode control, line feed-forward, cycle-by-cycle current limit, and simplified loop compensation. The oscillator
ramp is internally buffered and added to the PWM comparator input to provide the necessary slope
compensation for current-mode control at higher duty cycles.
7.7V SERIES
REGULATOR
VIN VCC
GENERATOR 5V
REFERENCE 1.25V
ENABLE
LOGIC
CLK
Rt / SYNC OSC
SLOPECOMP RAMP
GENERATOR SET VCC
J Q
45PA
K Q OUT1
CLR
5V 0 SET
COMP S Q
DRIVER
1.25V 5k PWM R Q
CLR
100k +
VFB -
1.4V LOGIC
50k VCC
SS
OUT2
CS
+
2k 0.5V - DRIVER
GND
+
0.625V -
CLK
ERROR AMP
SOFT START 10PA
SS
SHUTDOWN
COMPARATOR
+
ENABLE
-
0.45V
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
Figure 8. Typical Application Circuit, 36-V to 75-V IN and 3.3-V, 10-A OUT
8.2.2.1 VCC
While the LM5030 internally generates a voltage at VCC (7.7 V), the internal regulator is used mainly during the
start-up sequence. Once the load current begins flowing through L2, which is both an inductor for the output filter
and a transformer, a voltage is generated at the secondary of L2, which powers the VCC pin. When the
externally applied voltage exceeds the internal value (7.7 V), the internal regulator shuts off, thereby reducing
internal power dissipation in the LM5030. L2 is constructed such that the voltage supplied to VCC ranges from
approximately 10.6 V to approximately 11.3 V, depending on the load current (see Figure 9).
11.3
11.2
11.1
11.0
VCC (V)
10.9
10.8
10.7
10.6
10.5
0.0 2.0 4.0 6.0 8.0 10.0
0.25
0.15
0.10
0.05
0.00
0.0 0.2 0.4 0.6 0.8 1.0
8.2.2.3 Shutdown
The Shutdown pad (SD) on the board connects to the SoftStart pin on the LM5030 (pin 10), and permits on/off
control of the converter by an external switch. SD should be pulled below 0.45 V, with an open collector or open
drain device, to shut down the LM5030 outputs and the VCC regulator. If the voltage at the SD pad is between
1.0 and 1.5 V, a partial-on condition results, which could be disruptive to the system. Therefore, the voltage at
the SD pad should transition quickly between its open circuit voltage (4.9 V) and ground.
V1
Q2 Gate
0V
t1 t2
V1
Q1 Gate
0V
V4
V3
Q2 Drain V2
tR = 150 ns
0V
V5
V6
T1 (Pin 4)
0V
V8
V7
V9
V10
D1 Output
0V
L2 Output
3.3V
100 mVp-p
1.2 100
90 VIN = 36 V
1.0
80
INPUT CURRENT (A)
VIN = 36 V VIN = 75 V
EFFICIENCY (%)
0.8
70
0.6 VIN = 75 V 60
50
0.4
40
0.2 30
20
0.0
0 2 4 6 8 10
0 5 10
LOAD CURRENT (A) LOAD CURRENT (A)
Figure 12. Input Current vs Load Current and VIN Figure 13. Efficiency vs Load Current and VIN
10 Layout
VIN SS
VFB RT
From VIN
COMP CS
To Current Sense
VCC Resistor
GND
To Isolated Feedback
To Gate Drive 1
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 27-Oct-2015
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
LM5030MM NRND VSSOP DGS 10 1000 TBD Call TI Call TI -40 to 125 S73B
LM5030MM/NOPB ACTIVE VSSOP DGS 10 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S73B
& no Sb/Br)
LM5030MMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 S73B
& no Sb/Br)
LM5030SD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 5030SD
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 27-Oct-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Oct-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 27-Oct-2015
Pack Materials-Page 2
MECHANICAL DATA
DPR0010A
SDC10A (Rev A)
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