Assignments Week04
Assignments Week04
Answer: (b)
Option (a) is false, as procedural statement can be used to update
variables of type reg, integer, real and time. Part of register type variable
can be selected for update using procedural statement. Thus option (b) is
true. Assigned value remains unchanged until changed by other
procedural assignment. Thus option (c) is false. Continuous assignment is
not used inside a procedural block. Thus option (d) is also false.
2. For the following code segment, the final value of variable “Z” will be
…………..
integer X, Y, Z;
initial
begin
X = 33; Y = 27; Z = 16;
#10 Y = X - Z;
#10 X = Y * 5;
#10 Z = X + Y;
end
Answer: 102
Here the blocking assignment statements will be executed sequentially in
the following way:
Y = X – Z = 33 – 16 = 17
X = Y * 5 = 17 * 5 = 85
Z = X + Y = 85 + 17 = 102
3. For the following code segment, the final value of variable “Z” will be
…………..
integer X, Y, Z;
initial
begin
X = 33; Y = 27; Z = 16;
end
initial
begin
Y <= #10 X - Z;
X <= #10 Y * 5;
Z <= #10 X + Y;
end
Answer: 60
Here all the three non-blocking procedural assignments will be executed
parallelly in the following way:
Y <= X – Z = 33 – 16 = 17
X <= Y * 5 = 27 * 5 = 135
Z <= X + y = 33 + 27 = 60
Answer: (a)
Both the variable int1 and int2 will be updated with the same value of
int1 or int2 based on order of execution of the two procedural blocks,
which is a race condition. Thus option (a) is true and option (b), (c) and
(d) are false.
Answer: (b)
Here the value of x is initially 8’b10101101, which after executing of the
following non-blocking assignment statements become
x <= x << 1, left shift 1 bit.
Value of x becomes 8’b01011010, and after
x[0] <= x[7], initial value of x[7] which was 1 is assigned to x[0].
Value of x becomes 8’b01011011, left rotation of 1 bit.
Answer: (c)
As all the three blocking assignments will run concurrently inside three
always block on the same clock edge, x1 and x0 may get new or old value
of x2 and x1 respectively. Thus option (c) is correct whereas option (a),
(b) and (d) are not correct.
Answer: (a)
Here the generate block dynamically creates N-1 non-blocking
assignment statements where in the LHS of these assignment statements
variables x[1], x[2], … , x[N-1] will be updated with the values of variables
x[0], x[1], …, x[N-2] respectively and x[0] is assigned new input value of
variable “in”. Due to the use of non-blocking assignments, all N variables
will be updated parallelly on the same positive edge of the clock “clk”.
Thus option (a) is correct, and options (b), (c) and (d) are not correct.
Answer: (b)
Here the UDP describes the state table of a sequential function having the
following characteristics:
i. The 1-bit sequential element can be set or reset
independent of clock “clk” by keeping the corresponding
“set” or “reset” signal active low.
ii. The state of the element toggles on the negative edge of the
“clk”.
iii. The positive edge of the “clk” is ignored.
Thus option (b) is correct whereas option (a), (c) and (d) are not correct.
10. Which of the following statements are true for user defined primitives in
Verilog?
a. Don’t care value is only allowed in specifying input where as no
change indicator can only appear as output.
b. The primitive can be used to specify sequential as well as
combination circuit.
c. The primitive can take as arguments any number of input and
output variables.
d. Input and output variables of type scalar and vector both are
allowed.
Answer: (a) and (b)
Option (a) and (b) state the design rules of UDP and are true. Since an
UPD can take any number of scalar input and only one scalar output,
option (c) and (d) are false.