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    MDAWAQAS

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    Waqas
    This document describes the configuration of an 8086 system trainer that includes: - An Intel 8086 CPU running at 14.7456 MHz - 64KB of ROM from F0000H-FFFFFH to store programs and data communication - 64KB of static RAM from 0000H-FFFFH to store user programs and data - A 16 character by 2 line LCD display - A 16 key hexadecimal keyboard and 8 function keys for input - A speaker for sound output - An RS-232 interface for serial communication with a PC - Other interfaces including an 8255 PPI, 8254 timer, 8259 interrupt controller, DAC0800 DAC, and ADCO804 ADC

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    MDAWAQAS

    Uploaded by

    Waqas
    67 views2 pages
    This document describes the configuration of an 8086 system trainer that includes: - An Intel 8086 CPU running at 14.7456 MHz - 64KB of ROM from F0000H-FFFFFH to store programs and data communication - 64KB of static RAM from 0000H-FFFFH to store user programs and data - A 16 character by 2 line LCD display - A 16 key hexadecimal keyboard and 8 function keys for input - A speaker for sound output - An RS-232 interface for serial communication with a PC - Other interfaces including an 8255 PPI, 8254 timer, 8259 interrupt controller, DAC0800 DAC, and ADCO804 ADC

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    This document describes the configuration of an 8086 system trainer that includes: - An Intel 8086 CPU running at 14.7456 MHz - 64KB of ROM from F0000H-FFFFFH to store programs and data communication - 64KB of static RAM from 0000H-FFFFH to store user programs and data - A 16 character by 2 line LCD display - A 16 key hexadecimal keyboard and 8 function keys for input - A speaker for sound output - An RS-232 interface for serial communication with a PC - Other interfaces including an 8255 PPI, 8254 timer, 8259 interrupt controller, DAC0800 DAC, and ADCO804 ADC

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    67 views2 pages

    MDAWAQAS

    Uploaded by

    Waqas
    This document describes the configuration of an 8086 system trainer that includes: - An Intel 8086 CPU running at 14.7456 MHz - 64KB of ROM from F0000H-FFFFFH to store programs and data communication - 64KB of static RAM from 0000H-FFFFH to store user programs and data - A 16 character by 2 line LCD display - A 16 key hexadecimal keyboard and 8 function keys for input - A speaker for sound output - An RS-232 interface for serial communication with a PC - Other interfaces including an 8255 PPI, 8254 timer, 8259 interrupt controller, DAC0800 DAC, and ADCO804 ADC

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    LAB # 8

    MDA – 8086 SYSTEM CONFIGURATION


    (TRAINER)
    CPU: Using Intel 8086 , using 14.7456 MHz.
    ROM: It has program to control users key input , Lcd display users program 64kb , it has data
    communication program . Range of ROM address Is F0000H – FFFFFH .
    STATIC RANDOM ACCESS MEMORY : Input’s users program and data . Address of memory is
    0000H - FFFFH , totally 64 KB.
    DISPLAY : Text LCD module , 16 character into 2 lines.
    KEYBOARD: IT is used to input machine language . There are 16 hexadecimal keys and 8
    Functions keys.
    SPEAKER : sound test.
    RS-232C : Serial communication with IBM compatable PC.
    DOT MATRIX LED : To understand and test the dot matrix structure and principle of display. It
    is interface 8255A (PPI)
    A/D CONVERTER: AD c0804 to convert analog to digital.
    D/A Converter : DA c0800 (8bit D/A converter) to convert digital to analog signal and to
    control the level meter.
    STEPPING MOTOR INTERFACE : Stepping motor driver circuit is design .
    POWER : AC 110-220v , DC +5v 3A, 12 v 1A , -12v 0.5A.

    OPERATIONAL INTRODUCTION:
    FUNCTION OF KEYS :
    MDA 8086 has high performance 64 KB monitor
    program . It is design for easy function. After power is on the monitor program begins to work .
    In addition to all the keys function the monitor has a memory checking routine.

    RES system reset.


    AD Set memory address.
    DA Update segment and offset and input data to memory.
    : Offset.
    + Segment and offset +1 increament , register display increament.
    _ Segment and offset -1increament register display decreament.
    STP Execute users program , a single step.
    GO Goto users program or execute monitor functions.
    MON immediately break users program and non maskable interrupt.
    REG Register display.

    CE09-144
    |
    IC’s CONFIGURATION
    ICL232
    Description
    The ICL232 is a dual RS-232 transmitter/receiver interface circuit that meets all ElA RS-
    232C and V.28 specifications. It requires a single +5V power supply, and features two
    onboard charge pump voltage converters which generate +10V and -10V supplies from
    the 5V supply.

    DAC0800
    The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog
    converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying
    DAC, monotonic performance over a 40 to 1 reference current range is possible. The
    DAC0800 series also features high compliance complementary current outputs to allow
    differential output voltages of 20 Vp-p with simple resistor loads. The reference-to-full-
    scale current matching of better than ±1 LSB eliminates the need for full-scale trims in
    most applications while the nonlinearities of better than ±0.1% over temperature
    minimizes system error accumulations.

    8259A
    Y 8086, 8088 Compatible
    Y MCS-80, MCS-85 Compatible
    Y Eight-Level Priority Controller
    Y Expandable to 64 Levels
    Y Programmable Interrupt Modes
    Y Individual Request Mask Capability
    Y Single a5V Supply (No Clocks)
    Y Available in 28-Pin DIP and 28-Lead
    PLCC Package
    (See Packaging Spec., Order Ý231369)
    Y Availablein EXPRESS
    ÐStandard Temperature Range
    ÐExtended Temperature Range
    DM74121
    General Description
    The DM74121 is a monostable multivibrator featuring both positive and negative edge
    triggering with complementary outputs. An internal 2ktiming resistor is provided for
    design convenience minimizing component count and layout problems. this device can
    be used with a single external capacitor. Inputs (A) are active-LOW trigger transition
    inputs and input (B) is and active-HIGH transition Schmitttrigger input that allows jitter-
    free triggering from inputs with transition rates as slow as 1 volt/second. A high
    immunity to VCC noise of typically 1.5V is also provided by internal circuitry at the input
    stage.
    CE09-144
    |

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