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Post Cts

The document discusses performing timing analysis on a synthesized design. It saves the design checkpoint, generates reports on clock skew, clock tree structure and timing, and fixes hold violations. If timing violations remain, it attempts physical optimization to improve timing. Finally it reports on various timing, power and voltage group aspects of the optimized design.

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mayur
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0% found this document useful (0 votes)
339 views18 pages

Post Cts

The document discusses performing timing analysis on a synthesized design. It saves the design checkpoint, generates reports on clock skew, clock tree structure and timing, and fixes hold violations. If timing violations remain, it attempts physical optimization to improve timing. Finally it reports on various timing, power and voltage group aspects of the optimized design.

Uploaded by

mayur
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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clock_opt

save_mw_cel -as CTS_1

#REPORTING The DESIGN for ANalysis

report_clock -skew -attributes >>


/home/praveenvg/labs/temp/valcano_design/post_cts.rpt/clockreport.rpt

report_clock_tree -summary -local_skew >>


/home/praveenvg/labs/temp/valcano_design/post_cts.rpt/CTreport.rpt

report_clock_timing -type skew significant_digits 3 >>


/home/praveenvg/labs/temp/valcano_design/post_cts.rpt/ClockTiming.rpt

report_timing -delay_type max

report_timing -delay_type min

# If any hold violations try fix using following commands

set_fix_hold [all_clocks]

set_max_area 0

set physopt area_critical_range 0.1

psynopt -area_recovery

# Again try reporting the design for violation

report_timing -delay_type min

report_threshold_voltage_group >
/home/praveenvg/labs/temp/valcano_design/post_cts.rpt/cts_voltage_groups.rpt

report_power > /home/praveenvg/labs/temp/valcano_design/post_cts.rpt/cts_power.rpt

report_clock -skew –attributes:

Attributes:

d - dont_touch_network

f - fix_hold

p - propagated_clock

G - generated_clock

g - lib_generated_clock
Clock Period Waveform Attrs Sources

--------------------------------------------------------------------------------

PCI_CLK 7.50 {0 3.75} {pclk}

SDRAM_CLK 4.10 {0 2.05} {sdram_clk}

SD_DDR_CLK 4.10 {0 2.05} G {sd_CK}

SD_DDR_CLKn 4.10 {2.05 4.1} G {sd_CKn}

SYS_2x_CLK 2.40 {0 1.2} {sys_2x_clk}

SYS_CLK 4.80 {0 2.4} G {I_CLOCKING/sys_clk_in_reg/Q}

v_PCI_CLK 7.50 {0 3.75} {}

v_SDRAM_CLK 4.10 {0 2.05} {}

--------------------------------------------------------------------------------

Generated Master Generated Master Waveform

Clock Source Source Clock Modification

--------------------------------------------------------------------------------

SD_DDR_CLK sdram_clk {sd_CK} SDRAM_CLK divide_by(1), combinational

SD_DDR_CLKn sdram_clk {sd_CKn} SDRAM_CLK divide_by(1), combinational

SYS_CLK sys_2x_clk {I_CLOCKING/sys_clk_in_reg/Q}

SYS_2x_CLK divide_by(2)

--------------------------------------------------------------------------------

****************************************

Report : clock_skew

Design : volcano

Version: M-2016.12-SP5-1

Date : Fri May 18 15:26:50 2018

****************************************

Rise Fall Min Rise Min fall Uncertainty

Object Delay Delay Delay Delay Plus Minus


--------------------------------------------------------------------------------

SD_DDR_CLKn - - - - 0.05 0.10

SD_DDR_CLK - - - - 0.05 0.10

SDRAM_CLK - - - - 0.10 0.20

SYS_CLK - - - - 0.10 0.20

SYS_2x_CLK - - - - 0.10 0.20

v_PCI_CLK 0.50 0.50 0.50 0.50 - -

PCI_CLK - - - - 0.10 0.30

Max Source Latency Min Source Latency

Early Early Late Late Early Early Late Late

Object Rise Fall Rise Fall Rise Fall Rise Fall

--------------------------------------------------------------------------------

SD_DDR_CLK

0.81 0.79 0.81 0.79 0.74 0.73 0.74 0.73

SD_DDR_CLKn

0.98 1.01 0.98 1.01 0.90 0.93 0.90 0.93

SYS_CLK 0.41 0.43 0.41 0.43 0.39 0.41 0.39 0.41

****************************************

Report : clock tree

Design : volcano

Version: M-2016.12-SP5-1

Date : Fri May 18 15:31:11 2018

****************************************

Information: Float pin scale factor for the 'max' operating condition of scenario 'default' is set to
1.000 (CTS-375)

Collecting setup paths:

... 20% ... 40% ... 60% ... 80% ... 100%

Generating the collection of data dependent pin-pairs Done


============ Local Skew Report ================

Clock: PCI_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock Pin Latency Skew

-----------------------------------------------------------------------------------

I_PCI_TOP/I_PCI_CORE/mega_enable_reg/CLK

0.7859 (L)

I_PCI_TOP/I_PCI_CORE/clk_gate_pad_out_buf_reg/latch/CLK (I)

0.3852 (S) 0.4007

Clock: v_PCI_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock: SYS_2x_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock Pin Latency Skew

-----------------------------------------------------------------------------------

I_RISC_CORE/I_PRGRM_CNT_TOP/I_PRGRM_FSM/Current_State_reg[1]/CLK

1.0754 (L)

I_RISC_CORE/I_INSTRN_LAT/clk_gate_Crnt_Instrn_2_reg/latch/CLK (I)

0.6580 (S) 0.4174

Clock: SYS_CLK

(I: ICG cell pin, N: non-stop pin)


(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock Pin Latency Skew

-----------------------------------------------------------------------------------

I_PARSER/r_pcmd_reg[2]/CLK 1.1126 (L)

I_BLENDER_1/clk_gate_rem_green_reg/latch/CLK (I)

0.6968 (S) 0.4158

Clock: SDRAM_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock Pin Latency Skew

-----------------------------------------------------------------------------------

I_SDRAM_TOP/I_SDRAM_READ_FIFO/SD_FIFO_CTL/U1/full_int_reg/CLK

0.9224 (L)

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_0_reg[0]/latch/CLK (I)

0.4010 (S) 0.5213

Clock: v_SDRAM_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock: SD_DDR_CLK

(I: ICG cell pin, N: non-stop pin)

(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

Clock: SD_DDR_CLKn

(I: ICG cell pin, N: non-stop pin)


(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)

Clock arrival time is calculated from the source(s) of the master clock.

======================= Clock Tree Summary ========================

Clock Sinks CTBuffers ClkCells Skew LongestPath TotalDRC BufferArea LocalSkew


LLatency SLatency

-----------------------------------------------------------------------------------------------------------------------------

PCI_CLK 503 26 30 0.0689 0.8161 2 114.1106 0.4007 0.7859


0.3852

SYS_2x_CLK 2037 71 99 0.0929 1.1392 2 369.0170 0.4174 1.0754


0.6580

SYS_CLK 1812 47 54 0.0929 0.7259 1 298.1109 0.4158 1.1126


0.6968

SDRAM_CLK 2899 63 73 0.0532 0.9270 2 392.6523 0.5213 0.9224


0.4010

SD_DDR_CLK 0 0 0 0.0000 0.0000 0 0.0000 NA NA NA

SD_DDR_CLKn 0 0 0 0.0000 0.0000 0 0.0000 NA NA NA

****************************************

Report : clock timing

-type skew

-nworst 1

-setup

Design : volcano

Version: M-2016.12-SP5-1

Date : Fri May 18 15:37:55 2018

****************************************

Clock: PCI_CLK

Clock Pin Latency Skew

----------------------------------------------------------------------------

snps_clk_chain_0/U_shftreg_0/ff_0/q_reg/CLK
0.816 wfp-+

snps_OCC_controller/U_clk_control_i_3/pipeline_or_tree_l_reg/CLK

0.787 0.029 wrp-+

----------------------------------------------------------------------------

Clock: SDRAM_CLK

Clock Pin Latency Skew

----------------------------------------------------------------------------

I_SDRAM_TOP/I_SDRAM_IF/mega_shift_1_reg[6][9]/CLK

0.914 wfp-+

I_SDRAM_TOP/I_SDRAM_IF/mega_shift_1_reg[5][0]/CLK

0.874 0.040 wfp-+

----------------------------------------------------------------------------

Clock: SD_DDR_CLK

No local skews.

Clock: SD_DDR_CLKn

No local skews.

Clock: SYS_2x_CLK

Clock Pin Latency Skew

----------------------------------------------------------------------------

I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[9]/CLK

1.139 wrp-+

I_RISC_CORE/R_31/CLK 1.054 0.084 wrp-+

----------------------------------------------------------------------------

Clock: SYS_CLK

Clock Pin Latency Skew

----------------------------------------------------------------------------

I_BLENDER_0/result_reg[21]/CLK 1.127 wrp-+


I_PCI_TOP/I_PCI_WRITE_FIFO/PCI_FIFO_RAM_6/CE1

1.049 0.078 wrp-+

----------------------------------------------------------------------------

****************************************

Report : timing

-path full

-delay max

-max_paths 1

Design : volcano

Version: M-2016.12-SP5-1

Date : Fri May 18 15:40:45 2018

****************************************

* Some/all delay information is back-annotated.

Operating Conditions: ss0p95v125c Library: saed32hvt_ss0p95v125c

Parasitic source : LPE

Parasitic mode : RealRVirtualC

Extraction mode : MIN_MAX

Extraction derating : 125/125/125

Information: Percent of Arnoldi-based delays = 2.82%

Startpoint: pidsel (input port clocked by v_PCI_CLK)

Endpoint: I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]

(rising edge-triggered flip-flop clocked by PCI_CLK)

Path Group: PCI_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock v_PCI_CLK (rise edge) 0.00 0.00


clock network delay (ideal) 0.50 0.50

input external delay 4.00 4.50 r

pidsel (in) 0.00 4.50 r

io_buff_195_0/Y (NBUFFX4_RVT) 0.07 * 4.58 r

I_PCI_TOP/pidsel (PCI_TOP) 0.00 4.58 r

I_PCI_TOP/U710/Y (NBUFFX4_HVT) 0.13 * 4.71 r

I_PCI_TOP/U893/Y (INVX1_HVT) 0.05 * 4.76 f

I_PCI_TOP/U452/Y (NAND2X0_HVT) 0.07 * 4.83 r

I_PCI_TOP/U1845/Y (OR2X1_HVT) 0.10 * 4.93 r

I_PCI_TOP/U443/Y (OR2X1_LVT) 0.06 * 4.98 r

I_PCI_TOP/U1851/Y (NAND3X0_HVT) 0.12 * 5.10 f

I_PCI_TOP/U884/Y (OAI21X2_HVT) 0.24 * 5.34 r

I_PCI_TOP/U835/Y (AO21X2_HVT) 0.20 * 5.54 r

I_PCI_TOP/U650/Y (NBUFFX2_HVT) 0.14 * 5.68 r

I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/D (SDFFARX1_LVT)

0.00 * 5.68 r

data arrival time 5.68

clock PCI_CLK (rise edge) 7.50 7.50

clock network delay (propagated) 0.81 8.31

clock uncertainty -0.30 8.01

I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/CLK (SDFFARX1_LVT)

0.00 8.01 r

library setup time -0.11 7.89

data required time 7.89

--------------------------------------------------------------------------

data required time 7.89

data arrival time -5.68


--------------------------------------------------------------------------

slack (MET) 2.21

Startpoint: I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]

(rising edge-triggered flip-flop clocked by SDRAM_CLK)

Endpoint: I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch

(gating element for clock SDRAM_CLK)

Path Group: SDRAM_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SDRAM_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 0.90 0.90

I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/CLK (SDFFX2_HVT)

0.00 0.90 r

I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/Q (SDFFX2_HVT)

0.29 1.19 r

I_SDRAM_TOP/I_SDRAM_IF/U3968/Y (AND2X1_LVT) 0.04 * 1.23 r

I_SDRAM_TOP/I_SDRAM_IF/U87/Y (AND4X1_LVT) 0.05 * 1.29 r

I_SDRAM_TOP/I_SDRAM_IF/U86/Y (NAND4X0_LVT) 0.08 * 1.37 f

I_SDRAM_TOP/I_SDRAM_IF/U3714/Y (OR2X1_HVT) 0.15 * 1.52 f

I_SDRAM_TOP/I_SDRAM_IF/U20113/Y (AND3X1_LVT) 0.07 * 1.59 f

I_SDRAM_TOP/I_SDRAM_IF/U90/Y (OA21X1_HVT) 0.10 * 1.68 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/EN
(SNPS_CLOCK_GATE_LOW_SDRAM_IF)

0.00 1.68 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/U1/Y (NBUFFX8_HVT)

0.11 * 1.80 f

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/EN (CGLNPRX2_HVT)
0.02 * 1.82 f

data arrival time 1.82

clock SDRAM_CLK (fall edge) 2.05 2.05

clock network delay (propagated) 0.40 2.45

clock uncertainty -0.20 2.25

I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/CLK (CGLNPRX2_HVT)

0.00 2.25 f

clock gating setup time -0.11 2.14

data required time 2.14

--------------------------------------------------------------------------

data required time 2.14

data arrival time -1.82

--------------------------------------------------------------------------

slack (MET) 0.32

Startpoint: I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]

(rising edge-triggered flip-flop clocked by SDRAM_CLK)

Endpoint: sd_DQ_out[17]

(output port clocked by SD_DDR_CLK)

Path Group: SD_DDR_CLK

Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SDRAM_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 0.90 0.90

I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/CLK (SDFFARX1_HVT)

0.00 0.90 r

I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/Q (SDFFARX1_HVT)
0.28 1.18 r

I_SDRAM_TOP/I_SDRAM_IF/U29/Y (NBUFFX4_HVT) 0.10 * 1.28 r

I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_17/Y (MUX21X1_HVT)

0.15 * 1.43 r

I_SDRAM_TOP/I_SDRAM_IF/sd_DQ_out[17] (SDRAM_IF) 0.00 1.43 r

I_SDRAM_TOP/sd_DQ_out[17] (SDRAM_TOP) 0.00 1.43 r

U92/Y (NBUFFX8_HVT) 0.11 * 1.54 r

io_buff_93_0/Y (NBUFFX4_RVT) 0.08 * 1.62 r

sd_DQ_out[17] (out) 0.00 * 1.62 r

data arrival time 1.62

clock SD_DDR_CLK (fall edge) 2.05 2.05

clock network delay (ideal) 0.79 2.84

clock uncertainty -0.10 2.74

output external delay -0.75 1.99

data required time 1.99

--------------------------------------------------------------------------

data required time 1.99

data arrival time -1.62

--------------------------------------------------------------------------

slack (MET) 0.37

Startpoint: I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]

(rising edge-triggered flip-flop clocked by SYS_2x_CLK)

Endpoint: I_RISC_CORE/R_31

(rising edge-triggered flip-flop clocked by SYS_2x_CLK)

Path Group: SYS_2x_CLK

Path Type: max

Point Incr Path


--------------------------------------------------------------------------

clock SYS_2x_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 1.13 1.13

I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/CLK (SDFFARX1_LVT)

0.00 1.13 r

I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/Q (SDFFARX1_LVT)

0.18 1.31 r

I_RISC_CORE/U855/Y (NBUFFX16_LVT) 0.05 * 1.36 r

I_RISC_CORE/U781/Y (INVX2_HVT) 0.05 * 1.41 f

I_RISC_CORE/U109/Y (AND2X1_LVT) 0.06 * 1.47 f

I_RISC_CORE/U112/Y (AND4X1_LVT) 0.07 * 1.53 f

I_RISC_CORE/U130/Y (MUX21X2_LVT) 0.08 * 1.61 f

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_3_1/CO (FADDX1_LVT)

0.07 * 1.68 f

I_RISC_CORE/U111/Y (AND3X1_LVT) 0.06 * 1.74 f

I_RISC_CORE/U131/Y (MUX21X1_HVT) 0.15 * 1.89 f

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_2_2/CO (FADDX1_LVT)

0.08 * 1.97 f

I_RISC_CORE/U110/Y (AND2X2_LVT) 0.06 * 2.03 f

I_RISC_CORE/U137/Y (MUX21X1_HVT) 0.14 * 2.17 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_2/CO (FADDX2_LVT)

0.08 * 2.26 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_3/CO (FADDX1_LVT)

0.06 * 2.32 r

I_RISC_CORE/U948/Y (AND2X2_LVT) 0.06 * 2.38 r

I_RISC_CORE/U113/Y (MUX21X1_HVT) 0.14 * 2.52 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_1/CO (FADDX1_HVT)
0.17 * 2.69 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_2/CO (FADDX1_HVT)

0.15 * 2.83 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_3/CO (FADDX1_LVT)

0.08 * 2.91 r

I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_4/CO (FADDX1_LVT)

0.06 * 2.97 r

I_RISC_CORE/U653/Y (AO21X1_HVT) 0.11 * 3.09 r

I_RISC_CORE/U652/Y (NOR4X0_LVT) 0.08 * 3.17 f

I_RISC_CORE/R_31/D (SDFFARX1_LVT) 0.00 * 3.17 f

data arrival time 3.17

clock SYS_2x_CLK (rise edge) 2.40 2.40

clock network delay (propagated) 1.05 3.45

clock uncertainty -0.20 3.25

I_RISC_CORE/R_31/CLK (SDFFARX1_LVT) 0.00 3.25 r

library setup time -0.08 3.17

data required time 3.17

--------------------------------------------------------------------------

data required time 3.17

data arrival time -3.17

--------------------------------------------------------------------------

slack (MET) 0.00

Startpoint: I_BLENDER_0/s3_op2_reg[18]

(rising edge-triggered flip-flop clocked by SYS_CLK)

Endpoint: I_BLENDER_0/s4_op2_reg[28]

(rising edge-triggered flip-flop clocked by SYS_CLK)

Path Group: SYS_CLK


Path Type: max

Point Incr Path

--------------------------------------------------------------------------

clock SYS_CLK (rise edge) 0.00 0.00

clock network delay (propagated) 1.14 1.14

I_BLENDER_0/s3_op2_reg[18]/CLK (SDFFARX2_HVT) 0.00 1.14 r

I_BLENDER_0/s3_op2_reg[18]/QN (SDFFARX2_HVT) 0.25 1.39 r

I_BLENDER_0/U447/Y (INVX2_HVT) 0.12 * 1.50 f

I_BLENDER_0/sub_x_26/U137/Y (NAND2X0_LVT) 0.10 * 1.60 r

I_BLENDER_0/sub_x_26/U127/Y (OAI21X1_HVT) 0.18 * 1.78 f

I_BLENDER_0/U6644/Y (AO21X1_HVT) 0.13 * 1.91 f

I_BLENDER_0/U6480/Y (NAND4X0_LVT) 0.07 * 1.98 r

I_BLENDER_0/U1505/Y (NAND3X0_HVT) 0.30 * 2.28 f

I_BLENDER_0/U6647/Y (AO21X1_LVT) 0.13 * 2.41 f

I_BLENDER_0/U948/Y (XNOR2X1_HVT) 0.19 * 2.60 r

I_BLENDER_0/U1834/Y (INVX4_HVT) 0.08 * 2.68 f

I_BLENDER_0/U1159/Y (OR2X1_LVT) 0.05 * 2.73 f

I_BLENDER_0/U1158/Y (INVX1_LVT) 0.03 * 2.76 r

I_BLENDER_0/U1402/Y (XOR3X1_HVT) 0.31 * 3.07 f

I_BLENDER_0/U734/Y (XOR3X1_HVT) 0.31 * 3.38 f

I_BLENDER_0/U723/Y (XOR3X1_HVT) 0.29 * 3.67 f

I_BLENDER_0/U582/Y (XOR3X1_HVT) 0.31 * 3.98 f

I_BLENDER_0/U1390/Y (OR2X1_HVT) 0.12 * 4.10 f

I_BLENDER_0/U1213/Y (NAND3X0_LVT) 0.05 * 4.15 r

I_BLENDER_0/U1212/Y (NAND2X0_LVT) 0.03 * 4.18 f

I_BLENDER_0/U4989/Y (AND3X1_HVT) 0.14 * 4.32 f

I_BLENDER_0/U575/Y (OR2X1_HVT) 0.17 * 4.49 f


I_BLENDER_0/U4792/Y (INVX1_HVT) 0.06 * 4.54 r

I_BLENDER_0/U2263/Y (OR2X1_LVT) 0.04 * 4.59 r

I_BLENDER_0/U2257/Y (NAND3X0_LVT) 0.03 * 4.62 f

I_BLENDER_0/U2654/Y (NAND4X0_LVT) 0.06 * 4.68 r

I_BLENDER_0/U1727/Y (NAND3X0_HVT) 0.28 * 4.96 f

I_BLENDER_0/s4_op2_reg[28]/D (SDFFX1_LVT) 0.00 * 4.96 f

data arrival time 4.96

clock SYS_CLK (rise edge) 4.80 4.80

clock network delay (propagated) 1.14 5.94

clock uncertainty -0.20 5.74

I_BLENDER_0/s4_op2_reg[28]/CLK (SDFFX1_LVT) 0.00 5.74 r

library setup time -0.19 5.55

data required time 5.55

--------------------------------------------------------------------------

data required time 5.55

data arrival time -4.96

--------------------------------------------------------------------------

slack (MET) 0.59

Startpoint: I_PCI_TOP/R_687

(rising edge-triggered flip-flop clocked by PCI_CLK)

Endpoint: pserr_n_out

(output port clocked by v_PCI_CLK)

Path Group: v_PCI_CLK

Path Type: max

Point Incr Path

-----------------------------------------------------------

clock PCI_CLK (rise edge) 0.00 0.00


clock network delay (propagated) 0.79 0.79

I_PCI_TOP/R_687/CLK (SDFFASX1_LVT) 0.00 0.79 r

I_PCI_TOP/R_687/Q (SDFFASX1_LVT) 0.15 0.94 r

I_PCI_TOP/U614/Y (NAND3X0_HVT) 0.31 * 1.25 f

I_PCI_TOP/pserr_n_out (PCI_TOP) 0.00 1.25 f

U744/Y (INVX4_HVT) 0.17 * 1.42 r

U743/Y (INVX8_HVT) 0.15 * 1.57 f

io_buff_158_0/Y (NBUFFX4_RVT) 0.11 * 1.69 f

U32/Y (NBUFFX32_HVT) 0.10 * 1.78 f

pserr_n_out (out) 0.00 * 1.78 f

data arrival time 1.78

clock v_PCI_CLK (rise edge) 7.50 7.50

clock network delay (ideal) 0.50 8.00

output external delay -3.00 5.00

data required time 5.00

-----------------------------------------------------------

data required time 5.00

data arrival time -1.78

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slack (MET) 3.22

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Threshold Voltage Group Report

Vth Group All Blackbox Non-blackbox

Name cells cells cells

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saed32cell_hvt 25067 (48.63%) 0 (0.00%) 25067 (48.63%)

saed32cell_lvt 26203 (50.83%) 0 (0.00%) 26203 (50.83%)


saed32cell_svt 277 (0.54%) 0 (0.00%) 277 (0.54%)

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Total 51547 (100.00%) 0 (0.00%) 51547 (100.00%)

Vth Group All Blackbox Non-blackbox

Name cell area cell area cell area

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saed32cell_hvt 73788.42 (16.79%) 0.00 (0.00%) 73788.42 (16.79%)

saed32cell_lvt 100166.28 (22.79%) 0.00 (0.00%) 100166.28 (22.79%)

saed32cell_svt 265486.59 (60.41%) 0.00 (0.00%) 265486.59 (60.41%)

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Total 439441.30 (100.00%) 0.00 (0.00%) 439441.30 (100.00%)

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