IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.

6, NOVEMBER 2008 2867

Power Stage Design of Fourth-Order DC–DC

Converters by Means of Principal
Components Analysis
Antonietta De Nardo, Nicola Femia, Marco Nicolò, Giovanni Petrone, and Giovanni Spagnuolo, Member, IEEE

Abstract—The design of fourth-order dc-dc converters is dis-

cussed in this paper. The Principal Components Analysis is applied
to find the set of passive components which allows to avoid double
resonance in the control-to-output transfer function. The design
of a synchronous SEPIC converter has been studied as an applica-
tion of the proposed design methodology by using a database of real
passive components. The performances of the SEPIC converter de-
signed with the proposed methodology are verified through both
time domain and frequency domain simulations and they are com- Fig. 1. SEPIC converter.
pared with those ones achieved by standard ripple-based design
procedures.
Index Terms—Fourth-order converters, power stage design,
principal components analysis, SEPIC converter. to improve the battery life. The need for very low parasitic
resistances in a fourth-order converter results in a system
with two possible high resonance peaks. Unfortunately, the
I. INTRODUCTION double resonance phenomenon makes the design of a Voltage
Mode compensation network more involved and prevents from
WITCH-MODE dc–dc converters operation is based on the obtaining high cross-over frequencies, thus resulting in a low
S temporary storage of the energy inside reactive elements
which is taken from the source and then transferred to the load
bandwidth system. This is made worse by the very high-quality
factors1 which lower the gain margin of the closed-loop transfer
through switching devices. The total number of inductors and function.
capacitors determines the order of the overall system dynamics In the last years many efforts have been made in order to
in terms of its poles and zeroes. provide optimized design of power converters: minimization of
The use of fourth-order converters, such as SEPIC and Cuk the converter weight as well as the optimization of efficiency
ones, is often unwelcome because of the possibility to have two and switching frequency is obtained using Lagrangian penalty
resonance peaks in the control-to-output transfer function, but in [7]–[9], while a design procedure oriented to power elec-
also because of a larger number of components as well as a tronics circuits based on an evolutionary algorithm is introduced
higher complexity with respect to the most common second- in [10]. The aim of this paper is to present a novel technique
order converters (e.g. flyback, buck-boost) [1]–[5]. for selecting the passive components for the power stage of
Nevertheless, fourth-order converters often exhibit higher fourth-order dc-dc converters. The proposed approach is not
performances with respect to second-order ones [1]–[3]. For only based on classical design constraints purely expressing the
instance, the noninverting step-up-down output to input ratio voltages and currents ripples limitation [11]–[13], but it is also
of the SEPIC converter shown in Fig. 1 makes it quite suitable aimed at the optimization of the system frequency response. By
for LEDs and portable power applications [6] (cell phones, following a modern approach to converters design [14], [15],
the optimization technique presented in this paper is able to pro-
PDA, and notebook battery interfaces and chargers). This
kind of applications requires very efficient power conversion vide a set of solutions, selected within all the possible combina-
in order to avoid the overheating of the portable devices and tions in a database of real components available on the market,
that are suitable for good trade-offs in terms of efficiency, com-
ponents sizes, quality factor as well as dynamics order2 exhib-
Manuscript received November 02, 2007; revised February 13, 2008. Current
ited by the control-to-output frequency response. As usual in
version published December 09, 2008. Recommended for publication by Asso- Multi-Objective optimization procedures [17], a set of objec-
ciate Editor J. Cobos. tive functions for evaluating the goodness of any design solu-
A. De Nardo, N. Femia, G. Petrone, and G. Spagnuolo are with the DIIIE-
University of Salerno, 84084 Fisciano (SA), Italy (e-mail: [email protected];
tion is defined: the Principal Components Analysis (PCA) [18]
[email protected]; [email protected]; [email protected]). is useful in evaluating the quality of the solutions in terms of
M. Nicolò is with the National Semiconductor GmbH, Livry-Gargan-Strasse
1In the frequency response, represents the height of the resonance peak ex-
10, 82256 Fürstenfeldbruck, Germany.
Color versions of one or more of the figures in this paper are available online pressed in dB.
at http://ieeexplore.ieee.org. 2Meanwhile the system has basically a fourth-order dynamics, under certain
Digital Object Identifier 10.1109/TPEL.2008.2001914 conditions it can present a reduced order behavior, see also [16].

0885-8993/$25.00 © 2008 IEEE

2868 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 2. Voltage mode control scheme. Fig. 3. Power losses budget distribution.

their control-to-output frequency response shape through an an-

alytical manipulation of the state space representation.
The proposed approach allows to obtain a converter dynamic
behaviour that is very similar to that one of a second-order
system: this makes it simpler the design of a voltage mode
compensation network so that a current mode one is no longer
needed.
The paper is organized as follows. Section II describes the
application example that is used in order to illustrate the design
procedure. Section III introduces some basic elements of the
PCA-based approach in order to define the main figures of merit
adopted in the design and optimization approach. In Section IV
the three performance functions are collected, the design space
is defined and the results of the optimization are presented. Fi-
nally, in Section V the best solutions are compared and the im-
provements with respect to solutions obtained by standard de-
sign techniques are highlighted. Conclusions end the paper. Fig. 4. Control-to-output transfer function.

II. THE SEPIC CASE STUDY

In order to illustrate the design procedure introduced in this • , ;
paper, a pilot example consisting in a typical PDA battery inter- • , ;
face application is considered: • , .
• down to 2.7 V; These real values have been retrieved from Coilcraft and
• ; Kemet databases; furthermore, by employing two Renesas
• up to 0.25 A. MOSFET devices with and ,
The change is due to a 4.2-V Li-ion battery discharge the overall efficiency will hit 91.9%. The unwanted outcome
characteristic while the variation can be ascribed to abrupt is represented by the open-loop control-to-output transfer
changes of the PDA state, from standby to full performances function which exhibits two high resonance peaks, as shown
condition and vice-versa. Low-voltage and high-efficiency re- in Fig. 4, where Q factor is 12 at frequency (see also
quirements need of a synchronous rectifier in order to eliminate [22]–[24]).
the inconvenient diode drop losses; besides, slow line transient In practical designs, such problem is overcome by adopting
added to fast load transient requirements induce to choose the the Current-Mode Control method [25]–[27], through a separa-
voltage mode control (see Fig. 2). tion of the complex poles and zeroes that cancels out the reso-
The converter power stage is usually designed according to nance peak, but necessarily leads to an increase in the overall
a set of typical specifications regarding current and voltage rip- system complexity. This means that, regardless of the feedback
ples. The well known ripple-based design [19]–[21] is expressed network design (the Gc(s) in Fig. 2), the crossover frequency
as cannot be placed between and [21]. In fact,
• ; if a minimum gain margin of 10 dB is needed, the must be
• ; placed one decade before . On the other hand, if is
• ; pushed between and , the input voltage changes and
• ; the tolerances of the passive components values lead to an un-
• (Efficiency). certainty on the right side of the zero crossing, where the phase
At the same time, the losses budget distribution, usually repre- value changes suddenly. Consequently, by using the factor
sented by means of a pie plot as in Fig. 3, is accounted for. technique [28], in order to place at 1 kHz, 10 kHz and 50
By assuming a value of the switching frequency kHz, the following solutions are obtained:
, the following passive components specifications are • , ;
find out: • unstable system;
• , ; • , ;
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2869

Fig. 5. Closed loop TF with (a) f = 1 kHz, (b) f = 50 kHz.

where and represent the phase margin and gain margin if the system is asymptotically stable, the following matrices can
respectively, as in Fig. 5. The third solution seems to be the be defined:
suitable in terms of dynamic performances but, as can be de-
duced from Fig. 5(b), there is a dangerous approaching of the
loop gain to the 0 dB line which can cause multiple crossover
(2)
points. Since the frequency response is susceptible of parame-
ters values variations due to tolerances and drifts and also de-
pends on the varying working conditions through the duty cycle
value, the presence of multiple crossover points can lead to the (3)
system instability.
The goal of this paper is to show how to select an optimal as the Controllability and Observabilty Gramian matrices
combination of passive components in order to avoid the which respectively generate the subspaces of controllable and
problem of double crossover and to make the voltage mode observable states [29], [30].
control design easier and effective. Any Gramian matrix defined as
(4)
III. PCA IN SYSTEM ANALYSIS
has the following properties:
The PCA [18] is a mathematical theory inherited from statis- 1) is symmetric and positive semidefinite;
tics and used to obtain low-dimensional approximate descrip- 2) the eigenvelues are real, nonnegative and sorted in de-
tions for multidimensional systems. PCA is mathematically de- creasing order ;
fined as an orthogonal linear transformation that transforms the 3) the eigenvectors are orthonormal ;
data to a new coordinate system such that the greatest variance 4) the eigenvalues are given by
by any projection of the data comes to lie on the first coordi-
nate (called the first principal component), the second greatest
variance on the second coordinate, and so on. It involves the
where is the -row of the matrix .
computation of the eigenvalue decomposition or Singular value
Since the Gramian is symmetric it is also diagonalizable
decomposition of a data set. Such a theory can be adapted to the
Linear Systems (LS) [18] in order to find a new representation (5)
useful for the order reduction. Let it be considered a -order
system Input-State-Output (I-S-O) model: and
(1) (6)

Furthermore, by considering: .. .. .. .. (7)

• state transition matrix; . . . .
• impulse response matrix;
• output transition matrix; where are called principal components values.
2870 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

If, for example, the new coordinate system based on the the system shows the same behavior of a second-order converter,
transformation matrix , which diagonalizes the controlla- thus eliminating all the undesired effects of a double resonance
bility gramian : peak. Let it be considered the model of a SEPIC converter ob-
(8) tained through the Averaging State Space technique

(9) (14)
where
where
(10)

is defined, the eigenvalues represent the power densities re-

lated to each impulsive response included in the set, while (15)
the eigenvectors represent the associated natural directions.
In this way the new state variables projections are propor-
tional to the energies of state impulsive responses. Now if for a In (15) represents the duty cycle of the SEPIC converter
certain it happens that the first are dominant: and the matrices matrices have been obtained by
applying Kirchhoff current and voltage laws to the circuit.
(11) Using the Matlab function BALREAL [31], the internally bal-
anced representation and the matrix related to the system are
then it means that the first dimensions of the z-space are most obtained. Finally, by defining:
solicited by an impulsive set of inputs. On the other hand if the
same reasoning with the observability gramian is done (16)
(12) as the separation threshold value between the dominant prin-
it can be highlighted that in the new coordinate system if the cipal components values and weak ones, the designer can estab-
(12) is verified then the first k dimensions of the z-space are lish how much the system approaches a second-order behavior
dominant in soliciting the output. Combining the two results in based on how much is greater than one:
a unified internally balanced3 representation means second-order dynamics. (17)
(13) In this way, the optimization of the overall system frequency
response can be redirected to the power stage optimization in-
it can be found out that the dimensions in the new z-space which stead of stressing a compensation network only to patch up a
are dominant because contemporarily most affected by an im- bad power design. This means that the solution of the problem
pulsive set of inputs and most determining on the output vari- is made easier by choosing the passive components smartly. The
ables. With this final transformation, if a dominant subset of idea is to build two sets of components, capacitors and induc-
is determined, the first dimensions of the State Space are tors, taken from the same series of the previously selected ones
much more controllable and observable then the other ones, in and with values close to the ripple-based design ones. Then the
this way the system will practically show a reduced -order dy- circuit performances can be evaluated for all possible combina-
namics. tions of the four reactive elements among the components in the
In conclusion, in a -order system it can be found a transfor- database through the figures of merit defined as follows:
mation such that in the new state space the diagonal values of • separation Threshold ;
the transformed gramian matrix stand for the weights of each • efficiency4;
state space dimension in determining the system dynamics, as • damping factor.5 (defined as 1/Q)
for the gramian properties are in decreasing order, if the first Such figures of merit have been considered as the objective
are much higher then the remaining , the system be- functions of the optimization procedure aimed at their concur-
havior is close to a -order dynamics. rent maximization.
The space of parameters that has been considered for the opti-
IV. PCA APPLIED TO DC-DC CONVERTERS DESIGN mization is discretized, in order to account for real components
PCA is often used in order to obtain a simplification in system values allowable on the market. The database of real values
analysis with lower order approximations of the data set or of taken from producers’ catalogues and shown in Table I has been
the system representation. In switching converters analysis and considered.
design an approximation of the model is not needed, but the de- Consequently, the total number of combinations is
signer can take advantage of this theory strength in evaluating
(18)
if, under certain conditions, the converter shows a reduced order
dynamics. In other words, considering a fourth-order dc-dc con- 4Efficiency has been evaluated in Matlab for each combination of parame-

verter, one could understand for which values of the parameters ters considering the losses of all passive components as well as the losses of
switching devices according to [32].
3The existence of the internally balanced representation is demonstrated. The 5Damping factor was obtained directly extracting and inverting the value of
transformation matrix P can be obtained through different algorithms, see [31]. the Q factor from the control-to-output transfer function evaluated in Matlab.
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2871

Fig. 6. Solutions set: (a) V , (b) V . Sidebar PCA log(Th)

Fig. 7. Optimal solutions set: (a) V and (b) V . Sidebar gives the efficiency value.

TABLE I
DATABASE OF THE COMMERCIALLY AVAILABLE PARAMETERS solutions at , together with all the 4096 possible solu-
tions have been plotted in Fig. 6. In order to have a simpler inter-
pretation, the solution sets shown in Fig. 6 in the three-dimen-
sional space have been represented by using two bidimensional
plots, shown in Fig. 7, wherein the “Efficiency” dimension was
compressed and shown in the gray-scale palette.
The Pareto front is [17] the set of design solutions that are
nondominated, in the sense that no other solutions exhibit an
improvement of at least one performance figure without wors-
ening the others.
In Fig. 7 the ripple-based design solution introduced in
Section II is compared with the Pareto-optimal ones at both
The solutions can be laid out in the three-dimensional the input voltage values. The Pareto front obtained at
space of the performances or into the four-dimensional space consists of four solutions, while eight solutions give the Pareto
of parameters. front at . As can be deduced from Fig. 7 and Table II,
The design procedure has been conducted at both the extreme solutions in the upper left sides of the fronts are suitable for
values of the input voltage fixed at the beginning of Section II small Q factor, and therefore maximum damping factor, while
for the SEPIC case study, namely, 2.7 and 4.2 V, in the sequel solutions in the lower right sides show the best dynamic be-
referred to as and . havior because their higher Th factor make their corresponding
After the exhaustive search, the two Pareto-optimal fronts Bode diagram of the open loop transfer function closer to
[17], composed of a total of four solutions at and eight that one typical of a second-order circuit. It is worth noting
2872 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

TABLE II TABLE III

(a) FIGURES OF MERIT OF THE SOLUTIONS BELONGING TO THE PARETO FRONT (a) COMPONENTS VALUES OF THE SOLUTIONS BELONGING TO THE PARETO
@V . (b) FIGURES OF MERIT OF THE SOLUTIONS BELONGING TO THE FRONT @ V . (b) COMPONENTS VALUES OF THE SOLUTIONS BELONGING
PARETO FRONT @ V TO THE PARETO FRONT @ V

four solutions (shaded in Table III(a)) of the Pareto front de-

picted in Fig. 7(a), in particular in the left high side, coincide
with three solutions (shaded in Table III(b)), even in this case in
the left high side, of the Pareto front in Fig. 7(b). Such remark
suggests that such solutions represent the tradeoff, because they
exhibit best performances for both values of the input voltage.
On the other hand, if the designer looks at the best solution in
terms of damping, solution #4 in Fig. 7(a) gives the best result
at and solution #8 in Fig. 7(b) gives the best result at
. Solution #3 appears to be a good tradeoff of the three
figures of merit at both voltages. Furthermore, it shows an evi-
dent improvement with respect to the solution obtained by the
classical approach. Better solutions exist, especially if the de-
signer looks at one voltage value only, but they do not show a
Fig. 8. Comparison among the solutions belonging to the two Pareto fronts in high average quality at both low and high input voltages.
the space of parameters (C = 4:7 F for all of them): triangles = solutions
@V , circles = solutions @ V . The global best solution should be determined even by means
of an optimization procedure that does not account for a single
value of at a time, but checking the values of the figures of
merit at and at simultaneously.
that Fig. 7(a) and 7(b) show the same 4096 possible design
solutions which have different values of the figures of merit
because of the different value of the input voltage considered V. RESULTS
in the two figures. Such a different working condition of the In this section, a comparison between the solutions belonging
SEPIC converter leads to almost different values of the damping to both the Pareto fronts at different input voltages and the clas-
factor—solutions of the Pareto front at show a damping sical design is introduced by means of frequency domain and
factor that is almost doubled with respect to that one of the time domain analyses.
solutions of the Pareto front at —but similar values of By looking at Tables IV(a) and IV(b) it results that at
the separation threshold Th and of the efficiency. the current ripple affecting the two inductors is smaller than at at
Fig. 7 and Table II show the comparison among the solutions , but the opposite conclusion holds as far as the voltage
belonging to the two Pareto fronts in the space of performance ripples on the capacitors is concerned.
functions; Fig. 8 and Table III propose the same comparison in Tables II, III and IV show that all the solutions belonging
the space of parameters. This makes it evident that three out of to the Pareto fronts have quality factor values (Table II) that
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2873

Fig. 9. (a) PCA Threshold (sidebar) vs. ripples ratios @ V , (b) damping Factor (sidebar) vs. ripples ratios @ V .

TABLE IV
(a) RIPPLES VALUES CORRESPONDING TO THE SOLUTIONS BELONGING TO THE
PARETO FRONT @ V . (b) RIPPLES VALUES CORRESPONDING TO THE
SOLUTIONS BELONGING TO THE PARETO FRONT @ V

are better than the one obtained by the ripple based design and
this is obtained with lower values of inductances (Table III). Fig. 10. (a) Open-loop frequency response of the four selected solutions and
An important issue is that in order to get low values of and (b) magnification to highlight the differences.
high values of (lower order behavior) the values of C1 and
C2 tend to reach the minimum and the maximum capacitance
respectively, meanwhile the inductance values L1 and L2 tend , it can be put in evidence that equalization of the values
to be equalized. Looking at the pictures in Figs. 8, 9, referred to of the current ripples leads the system to
2874 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

Fig. 11. (a) Open-loop frequency response of four (#1,#4,#6,#8) selected solutions @ V and (b) magnification to highlight the differences.

Fig. 12. Bode diagrams of the best solutions in terms of Th value: (a) @ V , (b) V .

Fig. 13. Bode diagrams corresponding to the solution #3: (a) @ V , (b) @ V .

approach better Th values, while an increased value of the ratio The previous analysis helps the designer in understanding the
gives better values of the damping factor. behavioral dependence from the ripples values as well as from
the components values: this is usually not possible by a simple
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2875

Fig. 14. Bode diagrams corresponding to the solution #3 in presence of a 610% tolerance affecting the four reactive parameters: black = upper and lower
boundaries, gray = nominal solution (a) @ V , (b) @ V .

Fig. 15. Load step-up transient Vo response, Io = 25 mA ! 250 mA, @

V .

analysis of the transfer function in terms of its poles and zeroes Fig. 16. Load step-up transient Vo response, comparison among selected solu-
especially because of its involved symbolic form. tions @ V .
The features of the best solutions in frequency domain can be
also analyzed by looking at Figs. 10 and 11 for both values.
In order to distinguish the different curves corresponding to the , even if such solutions show a higher quality factor (see
solutions of the Pareto front, only four out of eight of them have Fig. 7). The best solutions in terms of values obtained at
been depicted in Fig. 11 for . and at , thus the solutions #8 and #4 respec-
As it can be seen in Fig. 10, the transfer functions corre- tively, have been also compared in the frequency domain with
sponding to the four solutions at show a much better the ripple based design solutions.
shape with respect to those ones depicted in Fig. 4 and refer- Diagrams shown in Fig. 12 confirm that each solution opti-
ring to ripple-based designed solutions. There are no high res- mized for a given input voltage value (#4 @ and #8 @
onance peaks and the dynamics is very similar to that one of a ) exhibits the best behavior at that input voltage value
second-order system. By looking at the sequence of solutions, (#8 in Fig. 12(a) and #4 in Fig. 12(b)). Nevertheless, even if
from #1 to #4, a slight increase in the first resonance peak is they deteriorate at the value different with respect to that
observed, which is related to the increasing efficiency (as evi- one for which they are optimized (#8 in Fig. 12(b) and #4 in
denced in Table II), while the second resonance peak tends to Fig. 12(a)), they keep better than those ones obtained by means
disappear, as it was expected due to the higher PCA threshold of the ripple based approach. Figs. 13 and 14 show that solu-
value. The same comments can be referred to the solutions at tion #3 in both Pareto fronts (see Fig. 7), corresponding to the
2876 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 6, NOVEMBER 2008

same set of parameters at both and , represents [4] J. Betten and R. Kollman, Underutilized SEPIC Outperforms the Fly-
a good compromise and exhibits a small sensitivity with respect back Topology Courtesy of PlanetAnalog 07/05/2005.
[5] L. H. Dixon, High Power Factor Preregulator Using the SEPIC Con-
to large uncertainties, e.g., 10%, affecting inductance and ca- verter Unitrode seminar SEM900, Topic 6, 1993.
pacitance values. [6] A. Huang, The Power Management of PDA—The Application of
SEPIC Circuit Analog Integrations Corporation Application Note,
The four solutions at have been also compared in the AN020, Apr. 2001.
time domain by using PSIM software: a control loop ensuring a [7] S. Rahman and F. C. Lee, “Nonlinear program based optimization
30-kHz crossover frequency and 52 of phase margin for each of boost and buck-boost converter designs,” in Proc. PESC 81-IEEE
Power Elec. Spec. Conf., Boulder, CO, 1981, pp. 180–191.
one of them [28] has been designed. A load step from 25 to [8] S. Balachandran and F. C. Lee, “Algorithms for power converter design
250 mA has been applied and in Fig. 15 the transient response optimization,” IEEE Trans. Aerosp. Electron. Syst., vol. AES-17, no. 3,
given by the Pareto-optimal combinations is compared that one pp. 422–432, 1981.
[9] C. J. Wu, F. C. Lee, S. Balachandran, and H. L. Goin, “Design opti-
corresponding to the traditional design. The higher cross-over mization for a half-bridge dc-dc converter,” IEEE Trans. Aerosp. Elec-
frequency shown by the four solutions improves the settling tron. Syst., vol. AES-18, no. 4, pp. 497–508, 1982.
time during the transient, while the higher resonance peak of [10] S. Busquets-Monge, G. Sormekun, and E. Hertz, “Power converter de-
sign optimization: A GA-based design approach to optimization of
the ripple-based solution has a detrimental effect on the corre- power electronics circuits,” IEEE Ind. Applicat. Mag., Jan./Feb. 2004.
sponding response even if has a 12 dB attenuation (Fig. 5(a)). [11] J. M. Kwon, W. Y. Choi, J. J. Lee, E. H. Kimand, and B. H. Kwon,
A final look to solutions #1 to #4 at evidences a “Continuous-conduction-mode SEPIC converter with low reverse-re-
covery loss for power factor correction,” IEE Proc. Electr. Power Appl.,
reduction of the voltage ripple due to the increasing value of vol. 153, no. 5, September 2006.
the inductance and the reduced effect of the second resonance [12] G. Spiazzi and P. Mattavelli, “Design criteria for power factor prereg-
peak in terms of the pseudo-oscillation inspired by the transient ulators based on SEPIC and Cuk converters in continuous conduction
mode,” in Proc. IEEE IAS Conf, 1994, pp. 1084–1089.
(Fig. 16), while the total voltage undershoot remains almost the [13] N. D. Muhamad, M. R. Sahid, A. H. M. Yatim, N. R. N. Idris, and M.
same. S. Ayob, Design of Power Stage and Controller for DC-DC Converter
In conclusion the fourth solution shows a better frequency Systems Using PSPICE 0-7803-9296-5/05 2005 © IEEE, pp. 903–908.
[14] N. Femia, M. L. Cruoglio, G. Lisi, A. DeNardo, M. Slocchi, and W.
response and a higher efficiency than the others, but this is ob- Berns, “Novel design approach for POL buck DC-DC converters,” in
tained with higher inductance values of the two inductors, PCIM 2006.
and , whilst the first solution still guarantee good perfor- [15] N. Femia and M. Slocchi, “Novel mathematical approach for exploring
point of load converter design,” in Proc. PCIM 2006.
mances by using the lowest values of inductance. The solutions [16] N. Femia and G. Spagnuolo, “State-space models and order reduction
between the first one and the fourth one represent different trade- for DC-DC switching converters in discontinuous modes,” IEEE Trans.
offs. Power Electronics, vol. 10, no. 6, Nov. 1995.
[17] K. Deb, Multi-Objective Optimization Using Evolutionary Algo-
rithms. New York: Wiley, 2001.
VI. CONCLUSION [18] B. C. Moore, “Principal component analysis in linear systems: Control-
lability, observability, and model reduction,” IEEE Trans. Automatic
In this paper, the problem of the selection of passive compo- Contr., vol. AC-26, 1981.
nents of the power stage of fourth-order dc-to-dc converters is [19] D. Schelle and J. Castorena, Buck-Converter Design Demystified. :
Power Electronics Technology, June 2006, pp. 46–53.
addressed. A novel design procedure based on Principal Com- [20] N. Mohan, T. Undeland, and W. Robbins, Power Electronics: Con-
ponents Analysis has been introduced, which improves the con- verters, Applications and Design. New York: Wiley, 2003, pp.
trol-to-output transfer function of the converter. Passive com- 195–196.
[21] R. W. Erickson and D. Maksimović, Fundamentals of Power Elec-
ponents are selected by PCA-based design so that the frequency tronics, 2nd ed. New York: Kluwer Academic, 2001.
responses of the fourth-order converter, which exhibit couples of [22] R. B. Ridley, Analyzing the Sepic Converter. : Power Systems Design
complex poles and zeroes and complicated dependencies on cir- Europe, Nov. 2006, pp. 14–18.
[23] S. B. Yaakov, D. Adar, and G. Rahav, A SPICE Compatible Behav-
cuit parameters, is made similar to a second-order system. The ioral Model of SEPIC Converters 0-7803-3500-7/96, 1996 © IEEE,
PCA-based design method is supported by a multiobjective op- pp. 1668–1674.
timization algorithm which works on a database of real compo- [24] D. Adar, G. Rahav, and S. B. Yaakov, “Behavioral average model of
SEPIC converters with coupled inductors,” Electron. Lett., vol. 32, no.
nents taken from manufacturers’ components lists. PCA-based 17, pp. 1525–1526, Aug. 15, 1996.
design solutions obtained for SEPIC converter result to be much [25] R. B. Ridley, “A new, continuous-time model for current-mode con-
better compared with those ones given by the usual ripple-based trol,” IEEE Trans. Power Electron., vol. 8, pp. 271–280, Apr. 1991.
[26] L. H. Dixon, Control Loop Design, SEPIC Preregulator Example Uni-
design approach, both in time and frequency domains. trode Seminar SEM900, Topic 7, 1993.
[27] W. Gu, Small Signal Modeling for Current Mode Controlled Cuk and
SEPIC Converters 0-7803-8975-1/05, IEEE PEDC 2005, pp. 906–910.
REFERENCES [28] Venable and H. Dean, “The K factor: A new mathematical tool for
[1] L. C. Gomes de Freitas, M. G. Simoes, C. A. Canesin, and L. C. de stability analysis and synthesis,” in Proc. Powercon 10, San Diego, CA,
Freitas, “Programmable PFC based hybrid multipulse power rectifier 1983, pp. H1-1–H1-12.
for ultra clean power application,” IEEE Trans. Power Electron., vol. [29] R. E. Kalman, “Irreducible realizations and the degree of a rational
21, no. 4, pp. 959–966, July 2006. matrix,” SIAM J. Appl. Math., vol. 13, no. 2, pp. 520–544, 1965.
[2] M. Chen and J. Sun, “Reduced-order averaged modeling of active- [30] E. Kreindler and P. E. Sarachik, “On the concept of controllability
clamp converters,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. and observability of linear systems,” IEEE Trans. Automat. Contr., vol.
487–494, March 2006. AC-9, pp. 129–136, 1964.
[3] S. Chakraborty, A. K. Jain, and N. Mohan, “A novel converter topology [31] A. J. Laub, “Computation of system balancing transformations and
for multiple individually regulated outputs,” IEEE Trans. Power Elec- other applications of simultaneous diagonalization algorithms,” IEEE
tron., vol. 21, no. 2, pp. 361–369, March 2006. Trans. Automatic Contr., vol. AC-32, no. 2, Feb. 1987.
DE NARDO et al.: POWER STAGE DESIGN OF FOURTH-ORDER DC–DC CONVERTERS BY MEANS OF PCA 2877

[32] J. Klein, Synchronous Buck MOSFET Loss Calculation With Excel Marco Nicolò received the M.E. degree in electrical
Model Fairchild Semiconductor Application Note, AN-6005, 2006. engineering from the University of Salerno, Italy, in
the 2005.
In 2007 he joined National Semiconductor Corpo-
ration, Fuerstenfeldbruck, Germany, as Design Engi-
neer. Currently, he is working in the NSC Application
Design Center and his main interest is in power elec-
tronics.

Giovanni Petrone was born in Salerno, Italy, in

1975. He received the “Laurea” degree in electronic
engineering from the University of Salerno, Italy, in
2001 and the Ph.D. degree in electrical engineering
Antonietta De Nardo was born in Salerno, Italy, in from the University of Napoli “Federico II”, Italy, in
1980. She received the M.S. degree in electronic en- 2004.
gineering from University of Salerno in September Since January 2005, he has been an Assistant Pro-
2005 and she is working towards the Ph.D. degree in fessor of Electrotechnics at the University of Salerno.
electronic engineering. His main research interests are in the analysis and de-
Her main research interests are analysis and design sign of switching converters for telecommunication
of switching converters. applications, renewable energy sources in distributed
power systems, and tolerance analysis of electronic circuits.

Giovanni Spagnuolo (M’98) was born in Salerno,

Italy, in 1967. He received the “Laurea” Degree
Nicola Femia (M’94) was born in Salerno, Italy, in electronic engineering from the University of
in 1963. He received the Doctor degree (honors) Salerno, Italy, in 1993 and the Ph.D. degree in
in engineering of industrial technologies (section electrical engineering from the University of Napoli
Electronics) from the University of Salerno, Italy, in “Federico II”, Italy, in 1997.
1988. In 1993, he joined the Dipartimento di Ingegneria
From 1990 to 1998, he was an Assistant Professor, dell’Informazione ed Ingegneria Elettrica of the
from 1998 to 2001 an Associate Professor and since University of Salerno, Italy, where he was a Post-
2001 he is a Full Professor of Electrotechnics at the doctoral Fellow (1998/99), an Assistant Professor
Faculty of Engineering, the University of Salerno. of Electrotechnics (1999/2003) and, since January
His main scientific interests are in the fields of circuit 2004, he has been an Associate Professor. His main research interests are in
theory and applications and power electronics. He the analysis and simulation of switching converters, in circuit and systems for
is coauthor of about 80 scientific papers published in the proceedings of renewable energy sources and in tolerance analysis and design of electronic
international symposia and in international journals. He has been Associate circuits. He is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRIAL
Editor of IEEE TRANSACTIONS ON POWER ELECTRONICS from 1995 to 2003. ELECTRONICS.