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Design of Burst Based Transactions in AMBA AXI Protocol For SoC Integration

The brochure outlines an 80 hour post graduate course in VLSI design that covers topics such as digital design, Verilog and VHDL coding, finite state machines, testbenches, synthesis, FPGA design and implementation. Students will learn design methodologies and work on mini and major projects to design and implement circuits onto an FPGA board. The course aims to provide hands-on experience in digital design, hardware description languages, and FPGA implementation.

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Smile Selva Kumar
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72 views

Design of Burst Based Transactions in AMBA AXI Protocol For SoC Integration

The brochure outlines an 80 hour post graduate course in VLSI design that covers topics such as digital design, Verilog and VHDL coding, finite state machines, testbenches, synthesis, FPGA design and implementation. Students will learn design methodologies and work on mini and major projects to design and implement circuits onto an FPGA board. The course aims to provide hands-on experience in digital design, hardware description languages, and FPGA implementation.

Uploaded by

Smile Selva Kumar
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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VLSI DESIGN COURSE BROCHURE - 2018

POST GRADUATE COURSE IN VLSI DESIGN 80 Hours

Introduction to VLSI 1 hour

VLSI Design Flow

ASIC vs FPGA

RTL Design Methodologies

Advanced Digital Design 4 hours

Introduction to Digital Electronics

Arithmetic Circuits

Data Processing Circuits

Combinational Circuits

- Design and Analysis

Sequential Circuits

- Design and Analysis

Memories and PLD

Finite State Machine

Verilog HDL – RTL Coding and Synthesis


[1] Introduction to Verilog HDL 1 hour

Applications of Verilog HDL


Verilog HDL language concepts

Verilog language basics and constructs

Abstraction levels

[2] Data Types 1


hours

Type concept

Nets and registers

Non hardware equivalent variables

Arrays

[3] Verilog operators 10


hours

Logical operators

Bitwise and Reduction operators

Concatenation and Conditional operators

Relational and Arithmetic

Shift and Equality operators

Operator’s precedence

[4] Assignments 10
hours

Types of assignments

Continuous assignments

Timing references

Procedural assignments

Blocking and Non-Blocking assignments

Execution branching

Tasks and Functions


[5] Finite State Machine 4
hours

Basic FSM Structure

Moore vs Mealy

Common FSM coding styles

Registered outputs

[6] Testbench 4
hours

Introduction to Testbench

Combinational circuit testing

Sequential circuit testing

Testbench techniques

[7] Synthesis coding style 2


hours

Registers in Verilog

Unwanted latches

Operator synthesis

RTL coding style

VHDL HDL – RTL Coding and Synthesis


[8] Introduction to VHDL 1
hour

Applications of VHDL HDL

VHDL HDL language concepts

VHDL language basics and constructs

Abstraction levels

[9] Data Types


1 hour
Type concept

Nets and registers

Non hardware equivalent variables

Arrays

[10] VHDL operators 10


hours

Logical operators

Bitwise and Reduction operators

Concatenation and Conditional operators

Relational and Arithmetic

Shift and Equality operators

Operator’s precedence

[11] Finite State Machine


4 hours

Basic FSM Structure

Moore vs Mealy

Common FSM coding styles

Registered outputs

[12] Testbench
4 hours

Introduction to Testbench

Combinational circuit testing

Sequential circuit testing

Testbench techniques

[13] Synthesis coding style


2 hours

Registers in VHDL
Unwanted latches

Operator synthesis

RTL coding style

FPGA Design on Spartan 2


hours

Xilinx ISE EDA tools

Xilinx FPGA design flow

DIP switch, LED and Push button concepts


Peripherals Design 2
hours

Seven Segment Display

Alphanumeric LCD Display

Mini Project 6
hours

Project Specification Analysis

Understanding the architecture

Module level implementation and verification

Building the top level module

Implementation the design onto the FPGA board

Major Project 10
hours

Project Specification Analysis

Understanding the architecture

Module level implementation and verification

Building the top level module

Implementation the design onto the FPGA board

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