CSE211: COMPUTER ORGANIZATION AND

DESIGN
Objective of This Subject in Course

• To understand the generic principles that underlie the building of a digital computer.

• To review the structure and functioning of a digital computer and understand its overall
system architecture.

• To analyze the working of memory unit and study the examples of mapping techniques of
different memory systems.
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 CSE211: COMPUTER ORGANIZATION AND
DESIGN
Books Preferred

• By M. Morris Mano “COMPUTER SYSTEM ARCHITECTURE”, Published by PEARSON

Publication

• By HENNESSY,J.L,DAVID A PATTERSON, AND GOLDBERG ” COMPUTER ARCHITECTURE A

QUANTITATIVE APPROACH” Published by PEARSON Publication

• By P. PAL CHOUDHURI “COMPUTER ORGANISATION AND DESIGN” Published by

PRENTICE HALL
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 CSE211: COMPUTER ORGANIZATION AND
DESIGN
Unit I
Introduction to digital electronics : logic gate, introduction to combinational circuits,
introduction to sequential circuits

Introduction to basics of architecture : computer architecture, computer organization

Register Transfer and Micro Operations : Bus and Memory Transfer, Logic Micro
operations, Shift Micro Operations, Register transfer and register transfer language, Design
of arithmetic logic unit., arithmetic micro operations, arithmetic logic shift unit

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 Introduction to Digital Electronics
• Digital Systems are used in communication, business transactions, traffic control,
space guidance, medical treatments, weather monitoring, the internet and
many other commercial ,industrial and scientific enterprises.

• Digital System can manipulates a discreet element of information, such discreet

elements of information can be electric impulses, the decimal digits, the letter
of an alphabets, arithmetic operations or any other set of meaningful symbols.

• Discreet quantity of information arises either form the nature of the process or
may be quantized from a continuous process.

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 Basic Elements of Digital Electronics

• Logic Gates
• Decoder
• Encoder
• Multiplexer
• De-multiplexer
• Flip-flop

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 Logic Gates

Basic Logic Gates Universal Logic Gates

• AND Gate • NAND Gate

• NOR Gate
• OR Gate
• NOT Gate

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 Universal Logic Gates

• A universal gate is a gate which can implement any Boolean function

without need to use any other gate type.

• The NAND and NOR gates are universal gates.

• In practice, this is advantageous since NAND and NOR gates are

economical and easier to fabricate and are the basic gates used in all
IC digital logic families

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Basic Gates using NAND Gate
Basic Gates using NOR Gate
Decoder
Encoder (Priority Encoder)
 Multiplexers

• In the large-scale-digital systems, a single line is required to carry on two or more

digital signals – and, of course! At a time, one signal can be placed on the one
line. But, what is required is a device that will allow us to select; and, the signal
we wish to place on a common line, such a circuit is referred to as multiplexer.
 Applications of Multiplexers

Multiplexers are used in various applications wherein multiple-data need to be

transmitted by using single line.

• Communication System
A communication system has both a communication network and a
transmission system. By using a multiplexer, the efficiency of the communication
system can be increased by allowing the transmission of data, such as audio and
video data from different channels through single lines or cables.
 Applications of Multiplexers

• Computer Memory
Multiplexers are used in computer memory to maintain a huge amount of
memory in the computers, and also to reduce the number of copper lines required
to connect the memory to other parts of the computer.
• Telephone Network
In telephone networks, multiple audio signals are integrated on a single line
of transmission with the help of a multiplexer.
• Transmission from the Computer System of a Satellite
Multiplexer is used to transmit the data signals from the computer system
of a spacecraft or a satellite to the ground system by using a GSM satellite.
De-Multiplexers
 Applications of De multiplexer

De multiplexers are used to connect a single source to multiple

destinations. These applications include the following:

• Communication System
Mux and de-mux both are used in communication system to carry out the process of
data transmission. A De-multiplexer receives the output signals from the multiplexer
and at the receiver end it converts them back to the original form.
• Arithmetic Logic Unit
The output of the ALU is fed as an input to the De-multiplexer, and the output of the
de-multiplexer is connected to a multiple register. The output of the ALU can be stored
in multiple registers.
 Applications of De multiplexer

• Serial to Parallel Converter

This converter is used to reconstruct parallel data. In this technique, serial data
is given as an input to the De-multiplexer at a regular interval, and a counter is
attached to the de-multiplexer at the control input to detect the data signal at
the output of the de-multiplexer. When all data signals are stored, the output of
the de-mux can be read out in parallel.
 Combinational Circuits

• No feedback paths
• No memory
• Combinational circuit is a connected arrangement of logic gates with
set of inputs and outputs.
• Binary values of outputs are a function of binary combination of
inputs.
 Sequential Circuits

• Feedback paths exist

• Memory present
• 2 Types- Synchronous and Asynchronous
• Synchronous seq circuits employ signals that effect storage elements
only at discrete instants of time.
• Synchronization is achieved with help of device called clock
 Sequential Circuits
Latches Flip-Flops
• NAND Latch • S-R Flip Flop (Set-Reset)
• NOR Latch • D Flip Flop
• J-K Flip Flop (Jack-King)
• T Flip Flop
NAND Latch

S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
NOR Latch

S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 X
1 1 1 X
SR Flip Flop

CLK S R Q n Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 X
1 1 1 1 X
D Flip Flop

CLK D Qn Qn+1

0 X 0 0

0 X 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 1
JK Flip Flop

CLK J K Q n Qn+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
T Flip Flop

CLK T Qn Qn+1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0
Excitation Tables of FFs
Introduction to basics of Architecture
 Introduction to basics of Architecture

• All computer functions are:

• Data processing
• Data storage
• Data movement
• Control mechanism
 System Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication lines
 System Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
 System Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
 Bus Organization

• The CPU communicates with the other components via a bus. A bus is a
set of Wires (multiplexers) that acts as a shared but common data path to
connect multiple subsystems within the system. It consists of multiple
lines, allowing the parallel movement of bits.
• Buses are low cost but very versatile, and they make it easy to connect
new devices to each other and to the system. At any one time, only one
device (be it a register, the ALU, memory, or some other component) may
use the bus. However, this sharing often results in a communications
bottleneck. The speed of the bus is affected by its length as well as by the
number of devices sharing it.
 Common Bus configuration System

A more efficient scheme for transferring information between common bus

registers in a multiple-register configuration is a common bus system. A bus
structure consists of a set of common lines, one for each bit of a register,
through which binary information is transferred one at a time. Control
signals determine which register is selected by the bus during each
particular register transfer. Constructing a common bus system
a. Using multiplexers
b. Using three state buffers.
Bus Configuration using
Multiplexers
 Bus Configuration using
Multiplexers
The number of multiplexers needed to construct the bus is equal to n.
• The size of each multiplexer must be k x 1 since it multiplexes k data lines.
S1 S0 Register Selected
0 0 A
0 1 B
1 0 C
1 1 D
For example: A common bus for eight registers of 16 bits each requires 16
multiplexers , one for each line in the bus. So Each multiplexer must have eight
data input lines and three selection lines to multiplex one significant bit in the eight
registers.
 Bus Configuration using three State Buffer (Gate)

A three-state gate is a digital circuit that exhibits three states.

Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate. The third state is a high impedance state.
• The high-impedance state behaves like an open circuit, which
means that the output is disconnected and does not have
logic significance.
• Three-state gates may perform any conventional logic, such as
AND or NAND. However, the one most commonly used in the
design of a bus system is the buffer gate.
 Three State Buffer

Buffer

A B A B

C=0

Open Circuit
A B A B
 Construction of Bus by Three State Buffer
The outputs of four buffers are connected together to form a single bus
line. (It must be realized that this type of connection cannot be done
with gates that do not
have three-state outputs.) The control inputs to the buffers determine
which of the four normal inputs will communicate with the bus line.
• No more than one buffer may be in the active state at any given time.
The connected buffers must be controlled so that only one three-state
buffer has access to the bus line while all other buffers are maintained
in a high- impedance state.
• One way to ensure that no more than one control input is active at
any given time is to use a decoder, as shown in the diagram.
Bus Line with Three State Buffer
 REGISTER
• A register is a group of flip-flops. Each flip–flop is capable of storing
one bit of information. An n-bit register consists of a group of n flip-
flops capable of storing n bits of binary information.
• In addition to the flip flops, a register may have combinational gates
that perform certain data processing tasks. The flip-flops hold the
binary information and the gates determine how the information is
transferred into the register. Various types of registers are available
commercially.
• The simplest register is one that consists of only flip flops without
any gates.
THE INTERNAL HARDWARE ORGANIZATION OF A DIGITAL
COMPUTER IS BEST DEFINED BY SPECIFYING

1. The set of register it contains and their function.

2. The sequence of micro operations performed on the binary

information stored in the registers.

3. The control that initiates the sequence of micro operations.

Register made by D Flip Flops
Register with Combinational Circuits
Register Transfer Language (RTL)

• The symbolic notation used to describe the micro operation transfers

among register is called a register transfer language.

• A programming language is a procedure for writing symbols to specify

a given computational process.

• A register transfer language is a system for expressing in symbolic

form the micro operation sequences among the register of a digital
module.
Register Transfer Language (RTL)
Register Transfer Language (RTL)
• Information transfer from one register to another is designated in symbolic form by
means of a replacement operator. The statement
R2 ← R1
denotes a transfer of the content of register R1
into register R2. It designates a replacement of the content of R2 by the content of R1.

• By definition, the content of the source register R1 does not change after the
transfer. Normally, we want the transfer to occur only under a predetermined
control condition. This can be shown by means of an if-then statement.
If (P = 1) then (R2 ← R1)
Where P is a control signal generated in the
control section. It is sometimes convenient to separate the control variables from the
register transfer operation by specifying a control function.
Register Transfer Language (RTL)
Even though the control condition such as P becomes
active just after time t, the actual transfer does not occur
until the register is triggered by the next positive
transition of the clock at time t + 1.this is shown in figure
Below:
Transfer from R1 to R2 when K1=1
Register Transfer Language (RTL)
• The register that holds an address for the memory unit is called a
memory address register and is designated by the name MAR or AR. As
for registers are PC (for program counter), IR (for instruction register)
and R1 (for processor register).
• The individual flip-flops in an n-bit register are numbered in sequence
from 0 through n-1, starting from 0 in the rightmost position and
increasing the numbers toward the left.
• The most common way to represent a register is by a rectangular box
with the name of the register inside .
• The name of the 16-bit register is PC. The symbol PC(O—7) or PC(L)
refers to the low-order byte and PC(8—15) or PC(H) to the high-order
byte.
Register Transfer Language (RTL)
• A control function is a Boolean variable that is equal to I or 0. The control function is
included in the statement as follows:
P: R2 ← R1 The control condition is terminated
with a colon. It symbolizes the requirement that the transfer operation be
executed by the hardware only if P= 1.
• Every statement written in a register transfer notation implies a hardware
construction for implementing the transfer.
Register Transfer Language (RTL)
MEMORY TRANSFER
• A memory word will be symbolized by the letter M.
• The particular memory word among the many available is selected by the memory
address during the transfer. This will be done by enclosing the address in square
brackets following the letter M .Consider a memory unit that receives the address
from a register, called the address register, symbolized by AR. The data are
transferred to another register, called the data register, symbolized by DR Then:
Register Transfer Language (RTL)

Memory Read Operation: A read operation: the transfer of information

from a memory word to the outside environment.
Read: DR ← M[AR]

This causes a transfer of information into DR from the memory word M

selected by the address in AR. The write operation transfers the content
of a data register to a memory word M selected by the address. Assume
that the input data are in register R1 and the address is in AR.
Register Transfer Language (RTL)

Memory write operation: the transfer of new information to be stored

into the memory.
Write: M[AR] ← R1
This causes a transfer of information from R1 into the memory word M
selected by the address in AR.
Micro operations

Computer system micro operations are of four types:

➢ Register transfer micro operations (RTL)
➢ Arithmetic micro operations
➢ Logic micro operations
➢ Shift micro operations
Arithmetic Micro operations
•The basic arithmetic micro operations are
• Addition R3 ←R1+R2
• Subtraction R3 ←R1-R2 or R3 ←R1+R2+1
• Increment R2 ←R2+1
• Decrement R2 ←R2-1

•The additional arithmetic micro operations are

• Add with carry
• Subtract with borrow
• Transfer/Load
 Half Adder & Full Adder
Half Adder x y c s
0 0 0 0 c = xy s = xy’ + x’y
0 1 0 1 =x  y x
c
1 0 0 1 y
1 1 1 0 s
Full Adder
y y
x y cn-1 cn s
0 0 0 0 0 0 0 0 1
0 0 1 0 1 0 1 cn-1 1 0 cn-1
0 1 0 0 1 x 1 1 x 0 1
0 1 1 1 0 0 1 1 0
1 0 0 0 1 cn s
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

x
y cn = xy + xcn-1+ ycn-1
S
= xy + (x  y)cn-1
cn-1
cn s = x’y’cn-1+x’yc’n-1+xy’c’n-1+xycn-1
= x  y  cn-1 = (x  y)  cn-1
Binary incrementer
A3 A2 A1 A0 1

x y x y x y x y
HA HA HA HA
C S C S C S C S

C4 S3 S2 S1 S0
4-bit Binary Incrementer
Binary Adder Subtractor

➢Mode input M controls the operation

➢ M=0 ---- adder
➢ M=1 ---- Subtractor
Binary Adder Subtractor

➢Mode input M controls the operation

➢ M=0 ---- adder
➢ M=1 ---- Subtractor
Binary Arithmetic Operations
Logical Micro operations
Logical Micro operations
Hardware Implementation Of Logical Operations
 Applications of Logic Micro operations
➢ Logic micro operations can be used to manipulate individual bits or a portions of a
word in a register

➢ Consider the data in a register A. In another register, B, is bit data that will be used to
modify the contents of A

➢Selective-set AA+B
➢Selective-complement AAB
➢Selective-clear A  A • B’
➢Mask (Delete) AA•B
➢Clear AAB
➢Insert A  (A • B) + C
➢Compare AAB
 Applications of Logic Micro operations
1. In a selective set operation, the bit pattern in B is used to set certain bits in A

1 1 0 0 At
1010 B
1 1 1 0 At+1 (A  A + B)
If a bit in B is set to 1, that same position in A gets set to 1, otherwise that bit in A keeps
its previous value.

2. In a selective complement operation, the bit pattern in B is used to complement certain

bits in A
1 1 0 0 At
1010 B
0 1 1 0 At+1 (A A  B)
If a bit in B is set to 1, that same position in A gets complemented from its original
value, otherwise it is unchanged.
 Applications of Logic Micro operations
3. In a selective clear operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At
1010 B
0 1 0 0 At+1 (A  A  B’)
If a bit in B is set to 1, that same position in A gets set to 0, otherwise it is unchanged

4. In a mask operation, the bit pattern in B is used to clear certain bits in A

1 1 0 0 At
1010 B
1 0 0 0 At+1 (A  A  B)
If a bit in B is set to 0, that same position in A gets set to 0, otherwise it is unchanged
 Applications of Logic Micro operations
5. In a clear operation, if the bits in the same position in A and B are the same, they are
cleared in A, otherwise they are set in A
1 1 0 0 At
1010 B
0 1 1 0 At+1 (A  A  B)
 Applications of Logic Micro operations
6. An insert operation is used to introduce a specific bit pattern into A register, leaving the
other bit positions unchanged
This is done as
–A mask operation to clear the desired bit positions, followed by
–An OR operation to introduce the new bits into the desired positions
–Example: Suppose you wanted to introduce 1010 into the low order four bits of A:
1101 1000 1011 0001 A (Original)
1101 1000 1011 1010 A (Desired)
1101 1000 1011 0001 A (Original)
1111 1111 1111 0000 Mask
1101 1000 1011 0000 A (Intermediate)
0000 0000 0000 1010 Added bits
1101 1000 1011 1010 A (Desired)
Shift Micro operations
 Shift Micro operations

•In a Register Transfer Language, the following notation is used

shl for a logical shift left
shr for a logical shift right
Examples:
•R2  shr R2
•R3  shl R3
Shift Micro operations
 Shift Micro operations
• An arithmetic shift is meant for signed binary numbers (integer)
• An arithmetic left shift multiplies a signed number by two
• An arithmetic right shift divides a signed number by two
• Sign bit : 0 for positive and 1 for negative
• The main distinction of an arithmetic shift is that it must keep the sign of
the number the same as it performs the multiplication or division

• A right arithmetic shift operation

• A left arithmetic shift operation

Shift Micro operations
Shift Micro operations RTL
Hard ware for shift operations
Overflow handling in shift operations
• An overflow flip-flop Vs can be used to detect an arithmetic shift-left
overflow

Vs = Rn-1  Rn-2

Rn-1
1 → overflow
Vs=
0 → no overflow
Rn-2
Overflow Condition of Arithmetic Shift Registers
Overflow Condition of Arithmetic Shift Registers
Arithmetic Logic Shift Unit

Instead of having individual registers

performing the micro-operations directly,
computer systems employ a number of
storage registers connected to a common
operational unit called an Arithmetic Logic
Unit (ALU).
Arithmetic Logic Shift Unit

S2
S1 Ci
S0

One stage of Di
arithmetic
circuit (Fig.A) Select

Ci+1 0 4×1
1 MUX
One stage of Ei 2
logic circuit 3
Bi
(Fig.B)
Ai
shr
Ai+1
shl
Ai-1
Arithmetic Logic Shift Unit Function Table