ASIC Physical Design

CMOS Processes

Smith Text: Chapters 2 & 3

 Physical design process overview
„ CMOS transistor structure and fabrication
steps
„ Standard cell layouts
„ Creation, verification & characterization of
a standard-cell based logic circuit block
„ Creation of a chip from circuit blocks
 IC/ASIC Design Flow
Behavioral Verify
Design Function

DFT/BIST Gate-Level Verify

& ATPG Netlist Function

Transistor-Level Verify Function

Netlist & Timing

DRC & LVS Physical Verify

Verification Layout Timing

Mask Data
ASIC Design Flow
Cell-Based IC
Cell-Based Block
Basic standard
Cell layout

Source: Weste “CMOS VLSI Design”

 N-channel MOS transistor

drain

gate bulk
+ + + +
VGS L
VGS so urce VDS
W VDS

gate T ox

n-type n-type bulk

so urce electrons drain
GND or
depletion VSS
Ex region
p-type mob ile ch annel charge fixed depletion charge

02.03
CMOS Inverter Cross-Section

Source: Weste “CMOS VLSI Design”

Inverter cross-section with well and
substrate contacts

Source: Weste “CMOS VLSI Design”

 IC fabrication process
2 4
1 hour
3 5
1 fu rn ace sp in
wa fer resist

grow crystal sa w grow oxid e

etch
resist As +
oxid e
mask

6 7 8 9 10 11 12

4. Grow oxide SiO2 8. Etch exposed oxide

5. Apply photoresist 9-10. Implant ions in exposed substrate
6. UV light exposes resist 11. Strip resist
7. Remove exposed resist 12. Etch oxide
 P-substrate
CMOS
SiO2 layer
Process
steps Photoresist

Expose and etch

Etch SiO2

Remove photoresist

Implant n-well

Remove SiO2
Source: Weste “CMOS VLSI Design”
 Deposit poly
CMOS
Process Etch
steps
Deposit SiO2

Etch

Diffusion

Remove SiO2

Source: Weste “CMOS VLSI Design”

CMOS Process steps

Source: Weste “CMOS VLSI Design”

CMOS n-well process transistor

Source: Weste “CMOS VLSI Design”

Inverter
mask set N-well

Poly

N+ diffusion

P+ diffusion

Contacts

Metal

Source: Weste “CMOS VLSI Design”

Standard
Cell
Mask Set

Submit mask
info to fab.

Source: Smith, Figure 2.7

 MOSIS fab processes
(http://www.mosis.org)

ASIC Design Kit

Source: Weste “CMOS VLSI Design”

CMOS process design rules
1.
1 well 2.
2 active 3.
3 pol y
1 0 (1 .1 ) 3 (2 .1 ) 5 (2 .3 ) 3 (2 .4 ) n we ll 1 (3 .5 )
n we ll 3 0 or 4 p d iff
(2 .2 ) (2 . 5 )
n we ll 3 (3 .4 )
p d iff p d iff n d iff n we ll
0 (1 .4 ) 9 (1 .2 ) 2 (3 .3 )
n d iff 3 n d iff p d if f
hot 0 or 4 2 (3 .2 )
p we ll (2 .2 ) (2 . 5 )
p we ll 0 o r 6 (1 .3 ) p o ly
3 (2 .1 ) 5 (2 .3 ) 3 (2 .4 ) p we ll
2 (3 .1 )
4.
4 select
p we ll n we ll 5 pol y
5. 2 (5 .3 a )
1.5
p -se le ct n -se le ct contact (5 .2 a )
p o ly
p d if f
n d iff 2 2 (5 .1 a )
6.
6 active
1 (4 .3 ) 3 (4 .1 ) contact 2 (6 .3 a ) n we ll
p o ly
1 . 5 (6 . 2 a ) 2 (6 .4 a )
n d if f p d if f
2 (4 .2 )
n -se le ct p -se le ct
p o ly
2 2 1.5
77. metal1 8.
8 via1 (6 .1 a ) (6 .2 a )
1 (7 .3 )
p d iff p o ly 2 (8 .4 )
3 (7 .1 )
p o ly 2 (8 .5 ) via 1
3 1 (8 .3 )
m e t a l2 co n ta c t
(7 .2 a )
m1 m2
a c tiv e m1 2 (8 .5 )
co n ta c t 2 p o ly 2 2 (8 .1 )
(7 .2 b ) 3 (8 .2 ) n d iff
1 (7 .4 )
99. metal2 1 4 via2 15.
1 5 metal3 10.
1 0 o ver glass (micr ons)
14.
6 (1 0 .3 ) 3 0 (1 0 .4 )
3 (9 .1 ) 2 2 (1 4 .1 ) 2 (1 4 .4 ) m3
6 m3
m2 m2 1 (1 5 .1 )
via 2 (1 4 .3 ) m2
via 1
4 (1 5 .2 )
m3 15
1 3 (1 0 .5 )
3 (1 4 .2 ) via 1 g la s s
(9 .2 b ) 4 (9 .3 ) via 2
(9 .2 a ) m3 m1
m1 m2
2 (1 5 .3 ) 100 1 0 0 (1 0 .1 )

Source: Smith, Figure 2.11

MOSIS
Design
Rules

Smith text:
Tables 2.7-2.9
MOSIS
Design
Rules

Smith text:
Tables 2.7-2.9
MOSIS
Design
Rules
MOSIS Design Rules