PIC18F2455/2550/4455/4550

17.0 UNIVERSAL SERIAL BUS The SIE can be interfaced directly to the USB, utilizing
the internal transceiver, or it can be connected through
(USB) an external transceiver. An internal 3.3V regulator is
This section describes the details of the USB also available to power the internal transceiver in 5V
peripheral. Because of the very specific nature of the applications.
module, knowledge of USB is expected. Some Some special hardware features have been included to
high-level USB information is provided in improve performance. Dual port memory in the
Section 17.10 “Overview of USB” only for application device’s data memory space (USB RAM) has been
design reference. Designers are encouraged to refer to supplied to share direct memory access between the
the official specification published by the USB Imple- microcontroller core and the SIE. Buffer descriptors are
menters Forum (USB-IF) for the latest information. also provided, allowing users to freely program end-
USB specification Revision 2.0 is the most current point memory usage within the USB RAM space. A
specification at the time of publication of this document. Streaming Parallel Port has been provided to support
the uninterrupted transfer of large volumes of data,
17.1 Overview of the USB Peripheral such as isochronous data, to external memory buffers.
The PIC18FX455/X550 device family contains a Figure 17-1 presents a general overview of the USB
full-speed and low-speed compatible USB Serial Inter- peripheral and its features.
face Engine (SIE) that allows fast communication
between any USB host and the PIC® microcontroller.

FIGURE 17-1: USB PERIPHERAL AND OPTIONS

PIC18FX455/X550 Family

3.3V Regulator External 3.3V

VUSB
Supply(3)
VREGEN EN
Optional
P External
Pull-ups(2)
FSEN P
UPUEN
Internal Pull-ups (Full (Low
UTRDIS Speed) Speed)
Transceiver
USB Bus
USB Clock from the FS
D+
Oscillator Module
UOE D-

External
UOE(1) Transceiver
USB Control and VM(1) USB Bus
Configuration VP(1)
RCV(1)
USB VMO(1)
SIE VPO(1)

SPP7:SPP0
1 Kbyte CK1SPP
USB RAM CK2SPP
CSSPP
OESPP

Note 1: This signal is only available if the internal transceiver is disabled (UTRDIS = 1).
2: The internal pull-up resistors should be disabled (UPUEN = 0) if external pull-up resistors are used.
3: Do not enable the internal regulator when using an external 3.3V supply.

© 2009 Microchip Technology Inc. DS39632E-page 165

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17.2 USB Status and Control In addition, the USB Control register contains a status bit,
SE0 (UCON<5>), which is used to indicate the occur-
The operation of the USB module is configured and rence of a single-ended zero on the bus. When the USB
managed through three control registers. In addition, a module is enabled, this bit should be monitored to deter-
total of 22 registers are used to manage the actual USB mine whether the differential data lines have come out of
transactions. The registers are: a single-ended zero condition. This helps to differentiate
• USB Control register (UCON) the initial power-up state from the USB Reset signal.
• USB Configuration register (UCFG) The overall operation of the USB module is controlled by
• USB Transfer Status register (USTAT) the USBEN bit (UCON<3>). Setting this bit activates the
• USB Device Address register (UADDR) module and resets all of the PPBI bits in the Buffer
• Frame Number registers (UFRMH:UFRML) Descriptor Table to ‘0’. This bit also activates the on-chip
• Endpoint Enable registers 0 through 15 (UEPn) voltage regulator (if the VREGEN Configuration bit is
set) and connects internal pull-up resistors, if they are
17.2.1 USB CONTROL REGISTER (UCON) enabled. Thus, this bit can be used as a soft
attach/detach to the USB. Although all status and control
The USB Control register (Register 17-1) contains bits
bits are ignored when this bit is clear, the module needs
needed to control the module behavior during transfers.
to be fully preconfigured prior to setting this bit.
The register contains bits that control the following:
• Main USB Peripheral Enable Note: When disabling the USB module, make
• Ping-Pong Buffer Pointer Reset sure the SUSPND bit (UCON<1>) is clear
prior to clearing the USBEN bit. Clearing
• Control of the Suspend mode
the USBEN bit when the module is in the
• Packet Transfer Disable
suspended state may prevent the module
from fully powering down.

REGISTER 17-1: UCON: USB CONTROL REGISTER

U-0 R/W-0 R-x R/C-0 R/W-0 R/W-0 R/W-0 U-0
— PPBRST SE0 PKTDIS USBEN RESUME SUSPND —
bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Ping-Pong Buffer Pointers to the Even Buffer Descriptor (BD) banks
0 = Ping-Pong Buffer Pointers not being reset
bit 5 SE0: Live Single-Ended Zero Flag bit
1 = Single-ended zero active on the USB bus
0 = No single-ended zero detected
bit 4 PKTDIS: Packet Transfer Disable bit
1 = SIE token and packet processing disabled, automatically set when a SETUP token is received
0 = SIE token and packet processing enabled
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0 = USB module and supporting circuitry disabled (device detached)
bit 2 RESUME: Resume Signaling Enable bit
1 = Resume signaling activated
0 = Resume signaling disabled
bit 1 SUSPND: Suspend USB bit
1 = USB module and supporting circuitry in Power Conserve mode, SIE clock inactive
0 = USB module and supporting circuitry in normal operation, SIE clock clocked at the configured rate
bit 0 Unimplemented: Read as ‘0’

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The PPBRST bit (UCON<6>) controls the Reset status The UCFG register also contains two bits which aid in
when Double-Buffering mode (ping-pong buffering) is module testing, debugging and USB certifications.
used. When the PPBRST bit is set, all Ping-Pong Buf- These bits control output enable state monitoring and
fer Pointers are set to the Even buffers. PPBRST has eye pattern generation.
to be cleared by firmware. This bit is ignored in buffer-
Note: The USB speed, transceiver and pull-up
ing modes not using ping-pong buffering.
should only be configured during the mod-
The PKTDIS bit (UCON<4>) is a flag indicating that the ule setup phase. It is not recommended to
SIE has disabled packet transmission and reception. switch these settings while the module is
This bit is set by the SIE when a SETUP token is enabled.
received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared; clearing it 17.2.2.1 Internal Transceiver
allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer The USB peripheral has a built-in, USB 2.0, full-speed
Descriptor Table will still be available, indicated within and low-speed compliant transceiver, internally con-
the USTAT register’s FIFO buffer. nected to the SIE. This feature is useful for low-cost
single chip applications. The UTRDIS bit (UCFG<3>)
The RESUME bit (UCON<2>) allows the peripheral to controls the transceiver; it is enabled by default
perform a remote wake-up by executing Resume (UTRDIS = 0). The FSEN bit (UCFG<2>) controls the
signaling. To generate a valid remote wake-up, transceiver speed; setting the bit enables full-speed
firmware must set RESUME for 10 ms and then clear operation.
the bit. For more information on Resume signaling, see
Sections 7.1.7.5, 11.4.4 and 11.9 in the USB 2.0 The on-chip USB pull-up resistors are controlled by the
specification. UPUEN bit (UCFG<4>). They can only be selected
when the on-chip transceiver is enabled.
The SUSPND bit (UCON<1>) places the module and
supporting circuitry (i.e., voltage regulator) in a The USB specification requires 3.3V operation for
low-power mode. The input clock to the SIE is also communications; however, the rest of the chip may be
disabled. This bit should be set by the software in running at a higher voltage. Thus, the transceiver is
response to an IDLEIF interrupt. It should be reset by supplied power from a separate source, VUSB.
the microcontroller firmware after an ACTVIF interrupt
17.2.2.2 External Transceiver
is observed. When this bit is active, the device remains
attached to the bus but the transceiver outputs remain This module provides support for use with an off-chip
Idle. The voltage on the VUSB pin may vary depending transceiver. The off-chip transceiver is intended for
on the value of this bit. Setting this bit before a IDLEIF applications where physical conditions dictate the
request will result in unpredictable bus behavior. location of the transceiver to be away from the SIE.
External transceiver operation is enabled by setting the
Note: While in Suspend mode, a typical bus UTRDIS bit.
powered USB device is limited to 2.5 mA
of current. Care should be taken to assure
FIGURE 17-2: TYPICAL EXTERNAL
minimum current draw when the device
enters Suspend mode. TRANSCEIVER WITH
ISOLATION
17.2.2 USB CONFIGURATION REGISTER PIC®
VDD Isolated 3.3V Derived
(UCFG) Microcontroller from USB from USB

Prior to communicating over USB, the module’s VDD

VUSB
associated internal and/or external hardware must be 1.5 kΩ
configured. Most of the configuration is performed with VM Isolation Transceiver
VP
the UCFG register (Register 17-2). The separate USB RCV D+
voltage regulator (see Section 17.2.2.8 “Internal VMO
D-
Regulator”) is controlled through the Configuration VPO
UOE
registers.
The UFCG register contains most of the bits that
Note: The above setting shows a simplified schematic
control the system level behavior of the USB module.
for a full-speed configuration using an external
These include: transceiver with isolation.
• Bus Speed (full speed versus low speed)
• On-Chip Pull-up Resistor Enable
• On-Chip Transceiver Enable
• Ping-Pong Buffer Usage

© 2009 Microchip Technology Inc. DS39632E-page 167

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REGISTER 17-2: UCFG: USB CONFIGURATION REGISTER
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UTEYE UOEMON(1) — UPUEN(2,3) UTRDIS(2) FSEN(2) PPB1 PPB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UTEYE: USB Eye Pattern Test Enable bit

1 = Eye pattern test enabled
0 = Eye pattern test disabled
bit 6 UOEMON: USB OE Monitor Enable bit(1)
1 = UOE signal active; it indicates intervals during which the D+/D- lines are driving
0 = UOE signal inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 UPUEN: USB On-Chip Pull-up Enable bit(2,3)
1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with FSEN = 0)
0 = On-chip pull-up disabled
bit 3 UTRDIS: On-Chip Transceiver Disable bit(2)
1 = On-chip transceiver disabled; digital transceiver interface enabled
0 = On-chip transceiver active
bit 2 FSEN: Full-Speed Enable bit(2)
1 = Full-speed device: controls transceiver edge rates; requires input clock at 48 MHz
0 = Low-speed device: controls transceiver edge rates; requires input clock at 6 MHz
bit 1-0 PPB1:PPB0: Ping-Pong Buffers Configuration bits
11 = Even/Odd ping-pong buffers enabled for Endpoints 1 to 15
10 = Even/Odd ping-pong buffers enabled for all endpoints
01 = Even/Odd ping-pong buffer enabled for OUT Endpoint 0
00 = Even/Odd ping-pong buffers disabled

Note 1: If UTRDIS is set, the UOE signal will be active independent of the UOEMON bit setting.
2: The UPUEN, UTRDIS and FSEN bits should never be changed while the USB module is enabled. These
values must be preconfigured prior to enabling the module.
3: This bit is only valid when the on-chip transceiver is active (UTRDIS = 0); otherwise, it is ignored.

There are 6 signals from the module to communicate The VPO and VMO signals are outputs from the SIE to
with and control an external transceiver: the external transceiver. The RCV signal is the output
• VM: Input from the single-ended D- line from the external transceiver to the SIE; it represents
the differential signals from the serial bus translated
• VP: Input from the single-ended D+ line
into a single pulse train. The VM and VP signals are
• RCV: Input from the differential receiver used to report conditions on the serial bus to the SIE
• VMO: Output to the differential line driver that can’t be captured with the RCV signal. The
• VPO: Output to the differential line driver combinations of states of these signals and their
• UOE: Output enable interpretation are listed in Table 17-1 and Table 17-2.

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TABLE 17-1: DIFFERENTIAL OUTPUTS TO 17.2.2.5 Ping-Pong Buffer Configuration
TRANSCEIVER The usage of ping-pong buffers is configured using the
VPO VMO Bus State PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong
Buffering” for a complete explanation of the ping-pong
0 0 Single-Ended Zero buffers.
0 1 Differential ‘0’
17.2.2.6 USB Output Enable Monitor
1 0 Differential ‘1’
The USB OE monitor provides indication as to whether
1 1 Illegal Condition
the SIE is listening to the bus or actively driving the bus.
This is enabled by default when using an external
TABLE 17-2: SINGLE-ENDED INPUTS transceiver or when UCFG<6> = 1.
FROM TRANSCEIVER The USB OE monitoring is useful for initial system
VP VM Bus State debugging, as well as scope triggering during eye
pattern generation tests.
0 0 Single-Ended Zero
0 1 Low Speed 17.2.2.7 Eye Pattern Test Enable
1 0 High Speed An automatic eye pattern test can be generated by the
1 1 Error module when the UCFG<7> bit is set. The eye pattern
output will be observable based on module settings,
The UOE signal toggles the state of the external trans- meaning that the user is first responsible for configuring
ceiver. This line is pulled low by the device to enable the SIE clock settings, pull-up resistor and Transceiver
the transmission of data from the SIE to an external mode. In addition, the module has to be enabled.
device.
Once UTEYE is set, the module emulates a switch from
a receive to transmit state and will start transmitting a
17.2.2.3 Internal Pull-up Resistors
J-K-J-K bit sequence (K-J-K-J for full speed). The
The PIC18FX455/X550 devices have built-in pull-up sequence will be repeated indefinitely while the Eye
resistors designed to meet the requirements for Pattern Test mode is enabled.
low-speed and full-speed USB. The UPUEN bit
Note that this bit should never be set while the module
(UCFG<4>) enables the internal pull-ups. Figure 17-1
is connected to an actual USB system. This test mode
shows the pull-ups and their control.
is intended for board verification to aid with USB certi-
fication tests. It is intended to show a system developer
17.2.2.4 External Pull-up Resistors
the noise integrity of the USB signals which can be
External pull-up may also be used if the internal resis- affected by board traces, impedance mismatches and
tors are not used. The VUSB pin may be used to pull up proximity to other system components. It does not
D+ or D-. The pull-up resistor must be 1.5 kΩ (±5%) as properly test the transition from a receive to a transmit
required by the USB specifications. Figure 17-3 shows state. Although the eye pattern is not meant to replace
an example. the more complex USB certification test, it should aid
during first order system debugging.
FIGURE 17-3: EXTERNAL CIRCUITRY
PIC® Host
Microcontroller Controller/HUB

VUSB

1.5 kΩ
D+

D-

Note: The above setting shows a typical connection

for a full-speed configuration using an on-chip
regulator and an external pull-up resistor.

© 2009 Microchip Technology Inc. DS39632E-page 169

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17.2.2.8 Internal Regulator SIE processes additional endpoints (Figure 17-4).
When the SIE completes using a buffer for reading or
The PIC18FX455/X550 devices have a built-in 3.3V reg-
writing data, it updates the USTAT register. If another
ulator to provide power to the internal transceiver and
provide a source for the internal/external pull-ups. An USB transfer is performed before a transaction
external 220 nF (±20%) capacitor is required for stability. complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Note: The drive from VUSB is sufficient to only
Clearing the transfer complete flag bit, TRNIF, causes
drive an external pull-up in addition to the
the SIE to advance the FIFO. If the next data in the
internal transceiver.
FIFO holding register is valid, the SIE will reassert the
The regulator can be enabled or disabled through the interrupt within 5 TCY of clearing TRNIF. If no additional
VREGEN Configuration bit. When enabled, the voltage data is present, TRNIF will remain clear; USTAT data
is visible on pin VUSB whenever the USBEN bit is also will no longer be reliable.
set. When the regulator is disabled (VREGEN = 0), a
3.3V source must be provided through the VUSB pin for Note: If an endpoint request is received while the
the internal transceiver. USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
Note 1: Do not enable the internal regulator if an host.
external regulator is connected to VUSB.
2: VDD must be equal to or greater than FIGURE 17-4: USTAT FIFO
VUSB at all times, even with the regulator
disabled. USTAT from SIE

17.2.3 USB STATUS REGISTER (USTAT)

The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
4-byte FIFO Clearing TRNIF
complete interrupt, USTAT should be read to determine
for USTAT Advances FIFO
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
Data Bus
Note: The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the

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REGISTER 17-3: USTAT: USB STATUS REGISTER
U-0 R-x R-x R-x R-x R-x R-x U-0
— ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI(1) —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111 = Endpoint 15
1110 = Endpoint 14
....
0001 = Endpoint 1
0000 = Endpoint 0
bit 2 DIR: Last BD Direction Indicator bit
1 = The last transaction was an IN token
0 = The last transaction was an OUT or SETUP token
bit 1 PPBI: Ping-Pong BD Pointer Indicator bit(1)
1 = The last transaction was to the Odd BD bank
0 = The last transaction was to the Even BD bank
bit 0 Unimplemented: Read as ‘0’

Note 1: This bit is only valid for endpoints with available Even and Odd BD registers.

© 2009 Microchip Technology Inc. DS39632E-page 171

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17.2.4 USB ENDPOINT CONTROL transactions. For Endpoint 0, this bit should always be
cleared since the USB specifications identify
Each of the 16 possible bidirectional endpoints has its
Endpoint 0 as the default control endpoint.
own independent control register, UEPn (where ‘n’ rep-
resents the endpoint number). Each register has an The EPOUTEN bit (UEPn<2>) is used to enable or dis-
identical complement of control bits. The prototype is able USB OUT transactions from the host. Setting this
shown in Register 17-4. bit enables OUT transactions. Similarly, the EPINEN bit
(UEPn<1>) enables or disables USB IN transactions
The EPHSHK bit (UEPn<4>) controls handshaking for
from the host.
the endpoint; setting this bit enables USB handshaking.
Typically, this bit is always set except when using The EPSTALL bit (UEPn<0>) is used to indicate a
isochronous endpoints. STALL condition for the endpoint. If a STALL is issued
on a particular endpoint, the EPSTALL bit for that end-
The EPCONDIS bit (UEPn<3>) is used to enable or
point pair will be set by the SIE. This bit remains set
disable USB control operations (SETUP) through the
until it is cleared through firmware, or until the SIE is
endpoint. Clearing this bit enables SETUP transac-
reset.
tions. Note that the corresponding EPINEN and
EPOUTEN bits must be set to enable IN and OUT

REGISTER 17-4: UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0 THROUGH UEP15)
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint handshake enabled
0 = Endpoint handshake disabled (typically used for isochronous endpoints)
bit 3 EPCONDIS: Bidirectional Endpoint Control bit
If EPOUTEN = 1 and EPINEN = 1:
1 = Disable Endpoint n from control transfers; only IN and OUT transfers allowed
0 = Enable Endpoint n for control (SETUP) transfers; IN and OUT transfers also allowed
bit 2 EPOUTEN: Endpoint Output Enable bit
1 = Endpoint n output enabled
0 = Endpoint n output disabled
bit 1 EPINEN: Endpoint Input Enable bit
1 = Endpoint n input enabled
0 = Endpoint n input disabled
bit 0 EPSTALL: Endpoint Stall Indicator bit
1 = Endpoint n has issued one or more STALL packets
0 = Endpoint n has not issued any STALL packets

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17.2.5 USB ADDRESS REGISTER FIGURE 17-5: IMPLEMENTATION OF
(UADDR) USB RAM IN DATA
The USB Address register contains the unique USB MEMORY SPACE
address that the peripheral will decode when active.
UADDR is reset to 00h when a USB Reset is received, 000h
indicated by URSTIF, or when a Reset is received from
the microcontroller. The USB address must be written Banks 0 User Data
by the microcontroller during the USB setup phase to 3
(enumeration) as part of the Microchip USB firmware
support.
3FFh
Buffer Descriptors, 400h
17.2.6 USB FRAME NUMBER REGISTERS
USB Data or User Data 4FFh
(UFRMH:UFRML) 500h
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML, Banks 4 USB Data or
while the three high-order bits are contained in User Data
to 7
UFRMH. The register pair is updated with the current
(USB RAM)
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number register is primarily used for 7FFh
isochronous transfers. 800h

17.3 USB RAM

USB data moves between the microcontroller core and
the SIE through a memory space known as the USB
RAM. This is a special dual port memory that is
Banks 8 Unused
mapped into the normal data memory space in Banks 4
to 14
through 7 (400h to 7FFh) for a total of 1 Kbyte
(Figure 17-5).
Bank 4 (400h through 4FFh) is used specifically for
endpoint buffer control, while Banks 5 through 7 are
available for USB data. Depending on the type of
buffering being used, all but 8 bytes of Bank 4 may also
F00h
be available for use as USB buffer space. F60h
Bank15
SFRs
Although USB RAM is available to the microcontroller FFFh
as data memory, the sections that are being accessed
by the SIE should not be accessed by the
microcontroller. A semaphore mechanism is used to
determine the access to a particular buffer at any given
time. This is discussed in Section 17.4.1.1 “Buffer
Ownership”.

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17.4 Buffer Descriptors and the Buffer FIGURE 17-6: EXAMPLE OF A BUFFER
Descriptor Table DESCRIPTOR
Address Registers Contents
The registers in Bank 4 are used specifically for end-
point buffer control in a structure known as the Buffer 400h BD0STAT (xxh)
Descriptor Table (BDT). This provides a flexible method Buffer 401h BD0CNT 40h Size of Block
for users to construct and control endpoint buffers of Descriptor 402h BD0ADRL 00h
various lengths and configuration. Starting
403h BD0ADRH 05h Address
The BDT is composed of Buffer Descriptors (BD) which
are used to define and control the actual buffers in the 500h
USB RAM space. Each BD, in turn, consists of four reg-
isters, where n represents one of the 64 possible BDs
(range of 0 to 63): Buffer USB Data

• BDnSTAT: BD Status register

• BDnCNT: BD Byte Count register 53Fh
• BDnADRL: BD Address Low register
Note: Memory regions not to scale.
• BDnADRH: BD Address High register
BDs always occur as a four-byte block in the sequence, Unlike other control registers, the bit configuration for
BDnSTAT:BDnCNT:BDnADRL:BDnADRH. The address the BDnSTAT register is context sensitive. There are
of BDnSTAT is always an offset of (4n – 1) (in hexa- two distinct configurations, depending on whether the
decimal) from 400h, with n being the buffer descriptor microcontroller or the USB module is modifying the BD
number. and buffer at a particular time. Only three bit definitions
Depending on the buffering configuration used are shared between the two.
(Section 17.4.4 “Ping-Pong Buffering”), there are up
to 32, 33 or 64 sets of buffer descriptors. At a minimum, 17.4.1.1 Buffer Ownership
the BDT must be at least 8 bytes long. This is because Because the buffers and their BDs are shared between
the USB specification mandates that every device must the CPU and the USB module, a simple semaphore
have Endpoint 0 with both input and output for initial mechanism is used to distinguish which is allowed to
setup. Depending on the endpoint and buffering update the BD and associated buffers in memory.
configuration, the BDT can be as long as 256 bytes.
This is done by using the UOWN bit (BDnSTAT<7>) as
Although they can be thought of as Special Function a semaphore to distinguish which is allowed to update
Registers, the Buffer Descriptor Status and Address the BD and associated buffers in memory. UOWN is the
registers are not hardware mapped, as conventional only bit that is shared between the two configurations
microcontroller SFRs in Bank 15 are. If the endpoint cor- of BDnSTAT.
responding to a particular BD is not enabled, its registers
When UOWN is clear, the BD entry is “owned” by the
are not used. Instead of appearing as unimplemented
microcontroller core. When the UOWN bit is set, the BD
addresses, however, they appear as available RAM.
entry and the buffer memory are “owned” by the USB
Only when an endpoint is enabled by setting the
peripheral. The core should not modify the BD or its
UEPn<1> bit does the memory at those addresses
corresponding data buffer during this time. Note that
become functional as BD registers. As with any address
the microcontroller core can still read BDnSTAT while
in the data memory space, the BD registers have an
the SIE owns the buffer and vice versa.
indeterminate value on any device Reset.
The buffer descriptors have a different meaning based
An example of a BD for a 64-byte buffer, starting at
on the source of the register update. Prior to placing
500h, is shown in Figure 17-6. A particular set of BD
ownership with the USB peripheral, the user can con-
registers is only valid if the corresponding endpoint has
figure the basic operation of the peripheral through the
been enabled using the UEPn register. All BD registers
BDnSTAT bits. During this time, the byte count and buf-
are available in USB RAM. The BD for each endpoint
fer location registers can also be set.
should be set up prior to enabling the endpoint.
When UOWN is set, the user can no longer depend on
17.4.1 BD STATUS AND CONFIGURATION the values that were written to the BDs. From this point,
the SIE updates the BDs as necessary, overwriting the
Buffer descriptors not only define the size of an end-
original BD values. The BDnSTAT register is updated
point buffer, but also determine its configuration and
by the SIE with the token PID and the transfer count,
control. Most of the configuration is done with the BD
BDnCNT, is updated.
Status register, BDnSTAT. Each BD has its own unique
and correspondingly numbered BDnSTAT register.

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The BDnSTAT byte of the BDT should always be the the SIE. When enabled, it checks the data packet’s par-
last byte updated when preparing to arm an endpoint. ity against the value of DTS (BDnSTAT<6>). If a packet
The SIE will clear the UOWN bit when a transaction arrives with an incorrect synchronization, the data will
has completed. The only exception to this is when KEN essentially be ignored. It will not be written to the USB
is enabled and/or BSTALL is enabled. RAM and the USB transfer complete interrupt flag will
No hardware mechanism exists to block access when not be set. The SIE will send an ACK token back to the
the UOWN bit is set. Thus, unexpected behavior can host to Acknowledge receipt, however. The effects of
occur if the microcontroller attempts to modify memory the DTSEN bit on the SIE are summarized in
when the SIE owns it. Similarly, reading such memory Table 17-3.
may produce inaccurate data until the USB peripheral The Buffer Stall bit, BSTALL (BDnSTAT<2>), provides
returns ownership to the microcontroller. support for control transfers, usually one-time stalls on
Endpoint 0. It also provides support for the
17.4.1.2 BDnSTAT Register (CPU Mode) SET_FEATURE/CLEAR_FEATURE commands speci-
When UOWN = 0, the microcontroller core owns the fied in Chapter 9 of the USB specification; typically,
BD. At this point, the other seven bits of the register continuous STALLs to any endpoint other than the
take on control functions. default control endpoint.
The Keep Enable bit, KEN (BDnSTAT<5>), determines The BSTALL bit enables buffer stalls. Setting BSTALL
if a BD stays enabled. If the bit is set, once the UOWN causes the SIE to return a STALL token to the host if a
bit is set, it will remain owned by the SIE independent received token would use the BD in that location. The
of the endpoint activity. This prevents the USTAT FIFO EPSTALL bit in the corresponding UEPn control regis-
from being updated, as well as the transaction ter is set and a STALL interrupt is generated when a
complete interrupt from being set for the endpoint. This STALL is issued to the host. The UOWN bit remains set
feature should only be enabled when the Streaming and the BDs are not changed unless a SETUP token is
Parallel Port is selected as the data I/O channel instead received. In this case, the STALL condition is cleared
of USB RAM. and the ownership of the BD is returned to the
microcontroller core.
The Address Increment Disable bit, INCDIS
(BDnSTAT<4>), controls the SIE’s automatic address The BD9:BD8 bits (BDnSTAT<1:0>) store the two most
increment function. Setting INCDIS disables the significant digits of the SIE byte count; the lower 8 digits
auto-increment of the buffer address by the SIE for are stored in the corresponding BDnCNT register. See
each byte transmitted or received. This feature should Section 17.4.2 “BD Byte Count” for more
only be enabled when using the Streaming Parallel information.
Port, where each data byte is processed to or from the
same memory location.
The Data Toggle Sync Enable bit, DTSEN
(BDnSTAT<3>), controls data toggle parity checking.
Setting DTSEN enables data toggle synchronization by

TABLE 17-3: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION

OUT Packet BDnSTAT Settings Device Response after Receiving Packet
from Host DTSEN DTS Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0 1 0 ACK 0 1 Updated
DATA1 1 0 ACK 1 0 Not Updated
DATA1 1 1 ACK 0 1 Updated
DATA0 1 1 ACK 1 0 Not Updated
Either 0 x ACK 0 1 Updated
Either, with error x x NAK 1 0 Not Updated
Legend: x = don’t care

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REGISTER 17-5: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH
BD63STAT), CPU MODE (DATA IS WRITTEN TO THE SIDE)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN(1) DTS(2) KEN INCDIS DTSEN BSTALL BC9 BC8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit(1)

0 = The microcontroller core owns the BD and its corresponding buffer
bit 6 DTS: Data Toggle Synchronization bit(2)
1 = Data 1 packet
0 = Data 0 packet
bit 5 KEN: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set (required for SPP endpoint configuration)
0 = USB will hand back the BD once a token has been processed
bit 4 INCDIS: Address Increment Disable bit
1 = Address increment disabled (required for SPP endpoint configuration)
0 = Address increment enabled
bit 3 DTSEN: Data Toggle Synchronization Enable bit
1 = Data toggle synchronization is enabled; data packets with incorrect Sync value will be ignored
except for a SETUP transaction, which is accepted even if the data toggle bits do not match
0 = No data toggle synchronization is performed
bit 2 BSTALL: Buffer Stall Enable bit
1 = Buffer stall enabled; STALL handshake issued if a token is received that would use the BD in the
given location (UOWN bit remains set, BD value is unchanged)
0 = Buffer stall disabled
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
The byte count bits represent the number of bytes that will be transmitted for an IN token or received
during an OUT token. Together with BC<7:0>, the valid byte counts are 0-1023.

Note 1: This bit must be initialized by the user to the desired value prior to enabling the USB module.
2: This bit is ignored unless DTSEN = 1.

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17.4.1.3 BDnSTAT Register (SIE Mode) The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT
When the BD and its buffer are owned by the SIE, most
register. The upper two bits reside in BDnSTAT<1:0>.
of the bits in BDnSTAT take on a different meaning. The
This represents a valid byte range of 0 to 1023.
configuration is shown in Register 17-6. Once UOWN
is set, any data or control settings previously written
17.4.3 BD ADDRESS VALIDATION
there by the user will be overwritten with data from the
SIE. The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
The BDnSTAT register is updated by the SIE with the
For an endpoint starting location to be valid, it must fall
token Packet Identifier (PID) which is stored in
in the range of the USB RAM, 400h to 7FFh. No
BDnSTAT<5:3>. The transfer count in the correspond-
mechanism is available in hardware to validate the BD
ing BDnCNT register is updated. Values that overflow
address.
the 8-bit register carry over to the two most significant
digits of the count, stored in BDnSTAT<1:0>. If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
17.4.2 BD BYTE COUNT within another endpoint’s buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
The byte count represents the total number of bytes
(OUT endpoint) with a BD location in use can yield
that will be transmitted during an IN transfer. After an IN
unexpected results. When developing USB
transfer, the SIE will return the number of bytes sent to
applications, the user may want to consider the
the host.
inclusion of software-based address validation in their
For an OUT transfer, the byte count represents the code.
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.

REGISTER 17-6: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER (BD0STAT THROUGH

BD63STAT), SIE MODE (DATA RETURNED BY THE SIDE TO THE
MICROCONTROLLER)
R/W-x U-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
UOWN — PID3 PID2 PID1 PID0 BC9 BC8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 UOWN: USB Own bit

1 = The SIE owns the BD and its corresponding buffer
bit 6 Reserved: Not written by the SIE
bit 5-2 PID3:PID0: Packet Identifier bits
The received token PID value of the last transfer (IN, OUT or SETUP transactions only).
bit 1-0 BC9:BC8: Byte Count 9 and 8 bits
These bits are updated by the SIE to reflect the actual number of bytes received on an OUT transfer
and the actual number of bytes transmitted on an IN transfer.

© 2009 Microchip Technology Inc. DS39632E-page 177

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17.4.4 PING-PONG BUFFERING the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
An endpoint is defined to have a ping-pong buffer when
completion of the next transaction, the pointer is
it has two sets of BD entries: one set for an Even
toggled back to the Even BD and so on.
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the The Even/Odd status of the last transaction is stored in
other BD. Double-buffering BDs in this way allows for the PPBI bit of the USTAT register. The user can reset
maximum throughput to/from the USB. all Ping-Pong Pointers to Even using the PPBRST bit.
The USB module supports four modes of operation: Figure 17-7 shows the four different modes of
operation and how USB RAM is filled with the BDs.
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
• Ping-pong buffer support for all endpoints
of BDs to endpoints is detailed in Table 17-4. This
• Ping-pong buffer support for all other Endpoints relationship also means that gaps may occur in the
except Endpoint 0 BDT if endpoints are not enabled contiguously. This
The ping-pong buffer settings are configured using the theoretically means that the BDs for disabled endpoints
PPB1:PPB0 bits in the UCFG register. could be used as buffer space. In practice, users
The USB module keeps track of the Ping-Pong Pointer should avoid using such spaces in the BDT unless a
individually for each endpoint. All pointers are initially method of validating BD addresses is implemented.
reset to the Even BD when the module is enabled. After

FIGURE 17-7: BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES

PPB1:PPB0 = 00 PPB1:PPB0 = 01 PPB1:PPB0 = 10 PPB1:PPB0 = 11
No Ping-Pong Ping-Pong Buffer Ping-Pong Buffers Ping-Pong Buffers
Buffers on EP0 OUT on all EPs on all other EPs
except EP0
400h 400h 400h 400h
EP0 OUT EP0 OUT Even EP0 OUT Even EP0 OUT
Descriptor Descriptor Descriptor Descriptor

EP0 IN EP0 OUT Odd EP0 OUT Odd EP0 IN

Descriptor Descriptor Descriptor Descriptor

EP1 OUT EP0 IN Even EP1 OUT Even

Descriptor EP0 IN Descriptor Descriptor
Descriptor
EP1 IN EP0 IN Odd EP1 OUT Odd
Descriptor EP1 OUT Descriptor Descriptor
Descriptor
EP1 OUT Even EP1 IN Even
EP1 IN Descriptor Descriptor
Descriptor
EP1 OUT Odd EP1 IN Odd
EP15 IN
Descriptor Descriptor
Descriptor
47Fh
EP1 IN Even
EP15 IN Descriptor
483h Descriptor
EP1 IN Odd
Descriptor
Available
as
Available
Data RAM EP15 IN Odd
as
Data RAM Descriptor
4F7h

Available
as
EP15 IN Odd Data RAM
Descriptor
4FFh 4FFh 4FFh 4FFh
Maximum Memory Maximum Memory Maximum Memory Maximum Memory
Used: 128 bytes Used: 132 bytes Used: 256 bytes Used: 248 bytes
Maximum BDs: Maximum BDs: Maximum BDs: Maximum BDs:
32 (BD0 to BD31) 33 (BD0 to BD32) 64 (BD0 to BD63) 62 (BD0 to BD61)

Note: Memory area not shown to scale.

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TABLE 17-4: ASSIGNMENT OF BUFFER DESCRIPTORS FOR THE DIFFERENT
BUFFERING MODES
BDs Assigned to Endpoint

Mode 3
Mode 0 Mode 1 Mode 2
Endpoint (Ping-Pong on all other EPs,
(No Ping-Pong) (Ping-Pong on EP0 OUT) (Ping-Pong on all EPs)
except EP0)

Out In Out In Out In Out In

0 0 1 0 (E), 1 (O) 2 0 (E), 1 (O) 2 (E), 3 (O) 0 1

1 2 3 3 4 4 (E), 5 (O) 6 (E), 7 (O) 2 (E), 3 (O) 4 (E), 5 (O)
2 4 5 5 6 8 (E), 9 (O) 10 (E), 11 (O) 6 (E), 7 (O) 8 (E), 9 (O)
3 6 7 7 8 12 (E), 13 (O) 14 (E), 15 (O) 10 (E), 11 (O) 12 (E), 13 (O)
4 8 9 9 10 16 (E), 17 (O) 18 (E), 19 (O) 14 (E), 15 (O) 16 (E), 17 (O)
5 10 11 11 12 20 (E), 21 (O) 22 (E), 23 (O) 18 (E), 19 (O) 20 (E), 21 (O)
6 12 13 13 14 24 (E), 25 (O) 26 (E), 27 (O) 22 (E), 23 (O) 24 (E), 25 (O)
7 14 15 15 16 28 (E), 29 (O) 30 (E), 31 (O) 26 (E), 27 (O) 28 (E), 29 (O)
8 16 17 17 18 32 (E), 33 (O) 34 (E), 35 (O) 30 (E), 31 (O) 32 (E), 33 (O)
9 18 19 19 20 36 (E), 37 (O) 38 (E), 39 (O) 34 (E), 35 (O) 36 (E), 37 (O)
10 20 21 21 22 40 (E), 41 (O) 42 (E), 43 (O) 38 (E), 39 (O) 40 (E), 41 (O)
11 22 23 23 24 44 (E), 45 (O) 46 (E), 47 (O) 42 (E), 43 (O) 44 (E), 45 (O)
12 24 25 25 26 48 (E), 49 (O) 50 (E), 51 (O) 46 (E), 47 (O) 48 (E), 49 (O)
13 26 27 27 28 52 (E), 53 (O) 54 (E), 55 (O) 50 (E), 51 (O) 52 (E), 53 (O)
14 28 29 29 30 56 (E), 57 (O) 58 (E), 59 (O) 54 (E), 55 (O) 56 (E), 57 (O)
15 30 31 31 32 60 (E), 61 (O) 62 (E), 63 (O) 58 (E), 59 (O) 60 (E), 61 (O)
Legend: (E) = Even transaction buffer, (O) = Odd transaction buffer

TABLE 17-5: SUMMARY OF USB BUFFER DESCRIPTOR TABLE REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
(1)
BDnSTAT UOWN DTS(4) PID3(2) PID2(2) PID1(2) PID0(2) BC9 BC8
KEN(3) INCDIS(3) DTSEN(3) BSTALL(3)
BDnCNT(1) Byte Count
(1)
BDnADRL Buffer Address Low
(1)
BDnADRH Buffer Address High
Note 1: For buffer descriptor registers, n may have a value of 0 to 63. For the sake of brevity, all 64 registers are
shown as one generic prototype. All registers have indeterminate Reset values (xxxx xxxx).
2: Bits 5 through 2 of the BDnSTAT register are used by the SIE to return PID3:PID0 values once the register
is turned over to the SIE (UOWN bit is set). Once the registers have been under SIE control, the values
written for KEN, INCDIS, DTSEN and BSTALL are no longer valid.
3: Prior to turning the buffer descriptor over to the SIE (UOWN bit is cleared), bits 5 through 2 of the
BDnSTAT register are used to configure the KEN, INCDIS, DTSEN and BSTALL settings.
4: This bit is ignored unless DTSEN = 1.

© 2009 Microchip Technology Inc. DS39632E-page 179

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17.5 USB Interrupts Figure 17-8 shows the interrupt logic for the USB
module. There are two layers of interrupt registers in
The USB module can generate multiple interrupt con- the USB module. The top level consists of overall USB
ditions. To accommodate all of these interrupt sources, status interrupts; these are enabled and flagged in the
the module is provided with its own interrupt logic UIE and UIR registers, respectively. The second level
structure, similar to that of the microcontroller. USB consists of USB error conditions, which are enabled
interrupts are enabled with one set of control registers and flagged in the UEIR and UEIE registers. An
and trapped with a separate set of flag registers. All interrupt condition in any of these triggers a USB Error
sources are funneled into a single USB interrupt Interrupt Flag (UERRIF) in the top level.
request, USBIF (PIR2<5>), in the microcontroller’s
interrupt logic. Interrupts may be used to trap routine events in a USB
transaction. Figure 17-9 shows some common events
within a USB frame and their corresponding interrupts.

FIGURE 17-8: USB INTERRUPT LOGIC FUNNEL

Second Level USB Interrupts Top Level USB Interrupts
(USB Error Conditions) (USB Status Interrupts)
UEIR (Flag) and UEIE (Enable) Registers UIR (Flag) and UIE (Enable) Registers

SOFIF
SOFIE
BTSEF
BTSEE TRNIF USBIF
TRNIE
BTOEF
BTOEE
IDLEIF
DFN8EF IDLEIE
DFN8EE UERRIF
CRC16EF UERRIE
CRC16EE

CRC5EF STALLIF
STALLIE
CRC5EE
PIDEF
PIDEE ACTVIF
ACTVIE

URSTIF
URSTIE

FIGURE 17-9: EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS

From Host From Host To Host
SETUP Token Data ACK Set TRNIF

From Host To Host From Host

IN Token Data ACK Set TRNIF
USB Reset
URSTIF
From Host From Host To Host
Start-Of-Frame Set TRNIF
OUT Token Empty Data ACK
SOFIF
Transaction
Transaction
Complete

RESET SOF SETUP DATA STATUS SOF

Differential Data

Control Transfer(1)
1 ms Frame

Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.

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17.5.1 USB INTERRUPT STATUS When the USB module is in the Low-Power Suspend
REGISTER (UIR) mode (UCON<1> = 1), the SIE does not get clocked.
When in this state, the SIE cannot process packets,
The USB Interrupt Status register (Register 17-7) con-
and therefore, cannot detect new interrupt conditions
tains the flag bits for each of the USB status interrupt
other than the Activity Detect Interrupt, ACTVIF. The
sources. Each of these sources has a corresponding
ACTVIF bit is typically used by USB firmware to detect
interrupt enable bit in the UIE register. All of the USB
when the microcontroller should bring the USB module
status flags are ORed together to generate the USBIF
out of the Low-Power Suspend mode (UCON<1> = 0).
interrupt flag for the microcontroller’s interrupt funnel.
Once an interrupt bit has been set by the SIE, it must
be cleared by software by writing a ‘0’. The flag bits
can also be set in software which can aid in firmware
debugging.

REGISTER 17-7: UIR: USB INTERRUPT STATUS REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0
— SOFIF STALLIF IDLEIF(1) TRNIF(2) ACTVIF(3) UERRIF(4) URSTIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIF: Start-Of-Frame Token Interrupt bit
1 = A Start-Of-Frame token received by the SIE
0 = No Start-Of-Frame token received by the SIE
bit 5 STALLIF: A STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the SIE
0 = A STALL handshake has not been sent
bit 4 IDLEIF: Idle Detect Interrupt bit(1)
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Transaction Complete Interrupt bit(2)
1 = Processing of pending transaction is complete; read USTAT register for endpoint information
0 = Processing of pending transaction is not complete or no transaction is pending
bit 2 ACTVIF: Bus Activity Detect Interrupt bit(3)
1 = Activity on the D+/D- lines was detected
0 = No activity detected on the D+/D- lines
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = An unmasked error condition has occurred
0 = No unmasked error condition has occurred.
bit 0 URSTIF: USB Reset Interrupt bit
1 = Valid USB Reset occurred; 00h is loaded into UADDR register
0 = No USB Reset has occurred

Note 1: Once an Idle state is detected, the user may want to place the USB module in Suspend mode.
2: Clearing this bit will cause the USTAT FIFO to advance (valid only for IN, OUT and SETUP tokens).
3: This bit is typically unmasked only following the detection of a UIDLE interrupt event.
4: Only error conditions enabled through the UEIE register will set this bit. This bit is a status bit only and
cannot be set or cleared by the user.

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17.5.1.1 Bus Activity Detect Interrupt Bit immediately operational while waiting for the 96 MHz
(ACTVIF) PLL to lock. The application code should clear the
ACTVIF flag as shown in Example 17-1.
The ACTVIF bit cannot be cleared immediately after
the USB module wakes up from Suspend or while the Note: Only one ACTVIF interrupt is generated
USB module is suspended. A few clock cycles are when resuming from the USB bus Idle
required to synchronize the internal hardware state condition. If user firmware clears the
machine before the ACTVIF bit can be cleared by ACTVIF bit, the bit will not immediately
firmware. Clearing the ACTVIF bit before the internal become set again, even when there is
hardware is synchronized may not have an effect on continuous bus traffic. Bus traffic must
the value of ACTVIF. Additionally, if the USB module cease long enough to generate another
uses the clock from the 96 MHz PLL source, then after IDLEIF condition before another ACTVIF
clearing the SUSPND bit, the USB module may not be interrupt can be generated.

EXAMPLE 17-1: CLEARING ACTVIF BIT (UIR<2>)

Assembly:
BCF UCON, SUSPND

Loop:
BCF UIR, ACTVIF
BTFSC UIR, ACTVIF
BRA Loop
Done:
C:
UCONbits.SUSPND = 0;
while (UIRbits.ACTVIF) { UIRbits.ACTVIF = 0; }

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17.5.2 USB INTERRUPT ENABLE The values in this register only affect the propagation
REGISTER (UIE) of an interrupt condition to the microcontroller’s inter-
rupt logic. The flag bits are still set by their interrupt
The USB Interrupt Enable register (Register 17-8)
conditions, allowing them to be polled and serviced
contains the enable bits for the USB status interrupt
without actually generating an interrupt.
sources. Setting any of these bits will enable the
respective interrupt source in the UIR register.

REGISTER 17-8: UIE: USB INTERRUPT ENABLE REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 SOFIE: Start-Of-Frame Token Interrupt Enable bit
1 = Start-Of-Frame token interrupt enabled
0 = Start-Of-Frame token interrupt disabled
bit 5 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt enabled
0 = STALL interrupt disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle detect interrupt enabled
0 = Idle detect interrupt disabled
bit 3 TRNIE: Transaction Complete Interrupt Enable bit
1 = Transaction interrupt enabled
0 = Transaction interrupt disabled
bit 2 ACTVIE: Bus Activity Detect Interrupt Enable bit
1 = Bus activity detect interrupt enabled
0 = Bus activity detect interrupt disabled
bit 1 UERRIE: USB Error Interrupt Enable bit
1 = USB error interrupt enabled
0 = USB error interrupt disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit
1 = USB Reset interrupt enabled
0 = USB Reset interrupt disabled

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17.5.3 USB ERROR INTERRUPT STATUS Each error bit is set as soon as the error condition is
REGISTER (UEIR) detected. Thus, the interrupt will typically not
correspond with the end of a token being processed.
The USB Error Interrupt Status register (Register 17-9)
contains the flag bits for each of the error sources Once an interrupt bit has been set by the SIE, it must
within the USB peripheral. Each of these sources is be cleared by software by writing a ‘0’.
controlled by a corresponding interrupt enable bit in
the UEIE register. All of the USB error flags are ORed
together to generate the USB Error Interrupt Flag
(UERRIF) at the top level of the interrupt logic.

REGISTER 17-9: UEIR: USB ERROR INTERRUPT STATUS REGISTER

R/C-0 U-0 U-0 R/C-0 R/C-0 R/C-0 R/C-0 R/C-0
BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF
bit 7 bit 0

Legend:
R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEF: Bit Stuff Error Flag bit

1 = A bit stuff error has been detected
0 = No bit stuff error
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit
1 = Bus turnaround time-out has occurred (more than 16 bit times of Idle from previous EOP elapsed)
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = The data field was not an integral number of bytes
0 = The data field was an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = The CRC16 failed
0 = The CRC16 passed
bit 1 CRC5EF: CRC5 Host Error Flag bit
1 = The token packet was rejected due to a CRC5 error
0 = The token packet was accepted
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check failed
0 = PID check passed

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17.5.4 USB ERROR INTERRUPT ENABLE As with the UIE register, the enable bits only affect the
REGISTER (UEIE) propagation of an interrupt condition to the micro-
controller’s interrupt logic. The flag bits are still set by
The USB Error Interrupt Enable register
their interrupt conditions, allowing them to be polled
(Register 17-10) contains the enable bits for each of
and serviced without actually generating an interrupt.
the USB error interrupt sources. Setting any of these
bits will enable the respective error interrupt source in
the UEIR register to propagate into the UERR bit at
the top level of the interrupt logic.

REGISTER 17-10: UEIE: USB ERROR INTERRUPT ENABLE REGISTER

R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit

1 = Bit stuff error interrupt enabled
0 = Bit stuff error interrupt disabled
bit 6-5 Unimplemented: Read as ‘0’
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = Bus turnaround time-out error interrupt enabled
0 = Bus turnaround time-out error interrupt disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = Data field size error interrupt enabled
0 = Data field size error interrupt disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16 failure interrupt enabled
0 = CRC16 failure interrupt disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit
1 = CRC5 host error interrupt enabled
0 = CRC5 host error interrupt disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PID check failure interrupt enabled
0 = PID check failure interrupt disabled

© 2009 Microchip Technology Inc. DS39632E-page 185

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17.6 USB Power Modes The application should never source any current onto
the 5V VBUS pin of the USB cable.
Many USB applications will likely have several different
sets of power requirements and configuration. The
most common power modes encountered are Bus FIGURE 17-11: SELF-POWER ONLY
Power Only, Self-Power Only and Dual Power with Attach Sense
Self-Power Dominance. The most common cases are VBUS I/O pin
presented here. ~5V
100 kΩ
VSELF VDD
17.6.1 BUS POWER ONLY ~5V
In Bus Power Only mode, all power for the application
is drawn from the USB (Figure 17-10). This is 100 kΩ VUSB
effectively the simplest power method for the device.
VSS
In order to meet the inrush current requirements of the
USB 2.0 specifications, the total effective capacitance
appearing across VBUS and ground must be no more
than 10 μF. If not, some kind of inrush limiting is
required. For more details, see Section 7.2.4 of the 17.6.3 DUAL POWER WITH SELF-POWER
USB 2.0 specification.
DOMINANCE
According to the USB 2.0 specification, all USB devices
Some applications may require a dual power option.
must also support a Low-Power Suspend mode. In the
This allows the application to use internal power pri-
USB Suspend mode, devices must consume no more
marily, but switch to power from the USB when no inter-
than 2.5 mA from the 5V VBUS line of the USB cable.
nal power is available. Figure 17-12 shows a simple
The host signals the USB device to enter the Suspend Dual Power with Self-Power Dominance example,
mode by stopping all USB traffic to that device for more which automatically switches between Self-Power Only
than 3 ms. This condition will cause the IDLEIF bit in and USB Bus Power Only modes.
the UIR register to become set.
Dual power devices also must meet all of the special
During the USB Suspend mode, the D+ or D- pull-up requirements for inrush current and Suspend mode
resistor must remain active, which will consume some current and must not enable the USB module until
of the allowed suspend current: 2.5 mA budget. VBUS is driven high. For descriptions of those require-
ments, see Section 17.6.1 “Bus Power Only” and
FIGURE 17-10: BUS POWER ONLY Section 17.6.2 “Self-Power Only”.
Additionally, dual power devices must never source
current onto the 5V VBUS pin of the USB cable.
VBUS VDD
~5V
FIGURE 17-12: DUAL POWER EXAMPLE
VUSB
100 kΩ Attach Sense
I/O pin
VSS
VBUS VDD
~5V

100 kΩ VUSB
17.6.2 SELF-POWER ONLY
VSELF VSS
In Self-Power Only mode, the USB application provides ~5V
its own power, with very little power being pulled from
the USB. Figure 17-11 shows an example. Note that an
attach indication is added to indicate when the USB
has been connected and the host is actively powering
VBUS.
In order to meet compliance specifications, the USB Note: Users should keep in mind the limits for
module (and the D+ or D- pull-up resistor) should not devices drawing power from the USB.
be enabled until the host actively drives VBUS high. One According to USB specification 2.0, this
of the I/O pins may be used for this purpose. cannot exceed 100 mA per low-power
device or 500 mA per high-power device.

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17.7 Streaming Parallel Port Refer to Section 18.0 “Streaming Parallel Port” for
more information about the SPP.
The Streaming Parallel Port (SPP) is an alternate route
option for data besides USB RAM. Using the SPP, an Note 1: If an endpoint is configured to use the
endpoint can be configured to send data to or receive SPP, the SPP module must also be
data directly from external hardware. configured to use the USB module.
Otherwise, unexpected operation may
This methodology presents design possibilities where
occur.
the microcontroller acts as a data manager, allowing
the SPP to pass large blocks of data without the micro- 2: In addition, if an endpoint is configured to
controller actually processing it. An application use the SPP, the data transfer type of that
example might include a data acquisition system, endpoint must be isochronous only.
where data is streamed from an external FIFO through
USB to the host computer. In this case, endpoint
control is managed by the microcontroller and raw data
movement is processed externally. 17.8 Oscillator
The SPP is enabled as a USB endpoint port through The USB module has specific clock requirements. For
the associated endpoint buffer descriptor. The endpoint full-speed operation, the clock source must be 48 MHz.
must be enabled as follows: Even so, the microcontroller core and other peripherals
1. Set BDnADRL:BDnADRH to point to FFFFh. are not required to run at that clock speed or even from
the same clock source. Available clocking options are
2. Set the KEN bit (BDnSTAT<5>) to let SIE keep
described in detail in Section 2.3 “Oscillator Settings
control of the buffer.
for USB”.
3. Set the INCDIS bit (BDnSTAT<4>) to disable
automatic address increment.

TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION(1)

Details on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 53

IPR2 OSCFIP CMIP USBIP EEIP BCLIP HLVDIP TMR3IP CCP2IP 56
PIR2 OSCFIF CMIF USBIF EEIF BCLIF HLVDIF TMR3IF CCP2IF 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.

© 2009 Microchip Technology Inc. DS39632E-page 187

PIC18F2455/2550/4455/4550
Details on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
page
PIE2 OSCFIE CMIE USBIE EEIE BCLIE HLVDIE TMR3IE CCP2IE 56
UCON — PPBRST SE0 PKTDIS USBEN RESUME SUSPND — 57
UCFG UTEYE UOEMON — UPUEN UTRDIS FSEN PPB1 PPB0 57
USTAT — ENDP3 ENDP2 ENDP1 ENDP0 DIR PPBI — 57
UADDR — ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 57
UFRML FRM7 FRM6 FRM5 FRM4 FRM3 FRM2 FRM1 FRM0 57
UFRMH — — — — — FRM10 FRM9 FRM8 57
UIR — SOFIF STALLIF IDLEIF TRNIF ACTVIF UERRIF URSTIF 57
UIE — SOFIE STALLIE IDLEIE TRNIE ACTVIE UERRIE URSTIE 57
UEIR BTSEF — — BTOEF DFN8EF CRC16EF CRC5EF PIDEF 57
UEIE BTSEE — — BTOEE DFN8EE CRC16EE CRC5EE PIDEE 57
UEP0 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP1 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP2 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP3 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP4 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP5 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP6 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP7 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP8 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP9 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP10 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP11 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP12 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP13 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP14 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
UEP15 — — — EPHSHK EPCONDIS EPOUTEN EPINEN EPSTALL 57
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
Note 1: This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.

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17.10 Overview of USB 17.10.3 TRANSFERS
This section presents some of the basic USB concepts There are four transfer types defined in the USB
and useful information necessary to design a USB specification.
device. Although much information is provided in this • Isochronous: This type provides a transfer
section, there is a plethora of information provided method for large amounts of data (up to
within the USB specifications and class specifications. 1023 bytes) with timely delivery ensured;
Thus, the reader is encouraged to refer to the USB however, the data integrity is not ensured. This is
specifications for more information (www.usb.org). If good for streaming applications where small data
you are very familiar with the details of USB, then this loss is not critical, such as audio.
section serves as a basic, high-level refresher of USB. • Bulk: This type of transfer method allows for large
amounts of data to be transferred with ensured
17.10.1 LAYERED FRAMEWORK data integrity; however, the delivery timeliness is
USB device functionality is structured into a layered not ensured.
framework graphically shown in Figure 17-13. Each • Interrupt: This type of transfer provides for
level is associated with a functional level within the ensured timely delivery for small blocks of data,
device. The highest layer, other than the device, is the plus data integrity is ensured.
configuration. A device may have multiple configura- • Control: This type provides for device setup
tions. For example, a particular device may have control.
multiple power requirements based on Self-Power Only
or Bus Power Only modes. While full-speed devices support all transfer types,
low-speed devices are limited to interrupt and control
For each configuration, there may be multiple transfers only.
interfaces. Each interface could support a particular
mode of that configuration. 17.10.4 POWER
Below the interface is the endpoint(s). Data is directly Power is available from the Universal Serial Bus. The
moved at this level. There can be as many as USB specification defines the bus power requirements.
16 bidirectional endpoints. Endpoint 0 is always a Devices may either be self-powered or bus powered.
control endpoint and by default, when the device is on Self-powered devices draw power from an external
the bus, Endpoint 0 must be available to configure the source, while bus powered devices use power supplied
device. from the bus.
17.10.2 FRAMES
Information communicated on the bus is grouped into
1 ms time slots, referred to as frames. Each frame can
contain many transactions to various devices and
endpoints. Figure 17-9 shows an example of a
transaction within a frame.

FIGURE 17-13: USB LAYERS

Device

To other Configurations (if any)

Configuration

To other Interfaces (if any)

Interface Interface

Endpoint Endpoint Endpoint Endpoint Endpoint

© 2009 Microchip Technology Inc. DS39632E-page 189

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The USB specification limits the power taken from the 17.10.6.2 Configuration Descriptor
bus. Each device is ensured 100 mA at approximately
The configuration descriptor provides information on
5V (one unit load). Additional power may be requested,
the power requirements of the device and how many
up to a maximum of 500 mA. Note that power above
different interfaces are supported when in this configu-
one unit load is a request and the host or hub is not
ration. There may be more than one configuration for a
obligated to provide the extra current. Thus, a device
device (i.e., low-power and high-power configurations).
capable of consuming more than one unit load must be
able to maintain a low-power configuration of a one unit 17.10.6.3 Interface Descriptor
load or less, if necessary.
The interface descriptor details the number of end-
The USB specification also defines a Suspend mode. points used in this interface, as well as the class of the
In this situation, current must be limited to 2.5 mA, interface. There may be more than one interface for a
averaged over 1 second. A device must enter a configuration.
Suspend state after 3 ms of inactivity (i.e., no SOF
tokens for 3 ms). A device entering Suspend mode 17.10.6.4 Endpoint Descriptor
must drop current consumption within 10 ms after
Suspend. Likewise, when signaling a wake-up, the The endpoint descriptor identifies the transfer type
device must signal a wake-up within 10 ms of drawing (Section 17.10.3 “Transfers”) and direction, as well
current above the Suspend limit. as some other specifics for the endpoint. There may be
many endpoints in a device and endpoints may be
17.10.5 ENUMERATION shared in different configurations.
When the device is initially attached to the bus, the host 17.10.6.5 String Descriptor
enters an enumeration process in an attempt to identify
the device. Essentially, the host interrogates the device, Many of the previous descriptors reference one or
gathering information such as power consumption, data more string descriptors. String descriptors provide
rates and sizes, protocol and other descriptive human readable information about the layer
information; descriptors contain this information. A (Section 17.10.1 “Layered Framework”) they
typical enumeration process would be as follows: describe. Often these strings show up in the host to
help the user identify the device. String descriptors are
1. USB Reset: Reset the device. Thus, the device generally optional to save memory and are encoded in
is not configured and does not have an address a unicode format.
(address 0).
2. Get Device Descriptor: The host requests a 17.10.7 BUS SPEED
small portion of the device descriptor. Each USB device must indicate its bus presence and
3. USB Reset: Reset the device again. speed to the host. This is accomplished through a
4. Set Address: The host assigns an address to the 1.5 kΩ resistor which is connected to the bus at the
device. time of the attachment event.
5. Get Device Descriptor: The host retrieves the Depending on the speed of the device, the resistor
device descriptor, gathering info such as either pulls up the D+ or D- line to 3.3V. For a
manufacturer, type of device, maximum control low-speed device, the pull-up resistor is connected to
packet size. the D- line. For a full-speed device, the pull-up resistor
6. Get configuration descriptors. is connected to the D+ line.
7. Get any other descriptors.
17.10.8 CLASS SPECIFICATIONS AND
8. Set a configuration.
DRIVERS
The exact enumeration process depends on the host.
USB specifications include class specifications which
17.10.6 DESCRIPTORS operating system vendors optionally support.
Examples of classes include Audio, Mass Storage,
There are eight different standard descriptor types of Communications and Human Interface (HID). In most
which five are most important for this device. cases, a driver is required at the host side to ‘talk’ to the
USB device. In custom applications, a driver may need
17.10.6.1 Device Descriptor
to be developed. Fortunately, drivers are available for
The device descriptor provides general information, most common host systems for the most common
such as manufacturer, product number, serial number, classes of devices. Thus, these drivers can be reused.
the class of the device and the number of configurations.
There is only one device descriptor.

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18.0 STREAMING PARALLEL PORT In addition, the SPP can provide time multiplexed
addressing information along with the data by using the
Note: The Streaming Parallel Port is only second strobe output. Thus, the USB endpoint number
available on 40/44-pin devices. can be written in conjunction with the data for that
endpoint.
PIC18F4455/4550 USB devices provide a Streaming
Parallel Port as a high-speed interface for moving data
to and from an external system. This parallel port
18.1 SPP Configuration
operates as a master port, complete with chip select The operation of the SPP is controlled by two registers:
and clock outputs to control the movement of data to SPPCON and SPPCFG. The SPPCON register
slave devices. Data can be channelled either directly to (Register 18-1) controls the overall operation of the
the USB SIE or to the microprocessor core. Figure 18-1 parallel port and determines if it operates under USB or
shows a block view of the SPP data path. microcontroller control. The SPPCFG register
(Register 18-2) controls timing configuration and pin
FIGURE 18-1: SPP DATA PATH outputs.
PIC18F4455/4550
18.1.1 ENABLING THE SPP
To enable the SPP, set the SPPEN bit (SPPCON<0>).
In addition, the TRIS bits for the corresponding SPP
USB
CK1SPP pins must be properly configured. At a minimum:
SIE
CK2SPP
SPP • Bits TRISD<7:0> must be set (= 1)
OESPP
Logic • Bits TRISE<2:1> must be cleared (= 0)
CSSPP
If CK1SPP is to be used:
CPU SPP<7:0>
• Bit TRISE<0> must be cleared (= 0)
If CSPP is to be used:
• Bit TRISB<4> must be cleared (= 0)

REGISTER 18-1: SPPCON: SPP CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPPOWN SPPEN
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Unimplemented: Read as ‘0’

bit 1 SPPOWN: SPP Ownership bit
1 = USB peripheral controls the SPP
0 = Microcontroller directly controls the SPP
bit 0 SPPEN: SPP Enable bit
1 = SPP is enabled
0 = SPP is disabled

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REGISTER 18-2: SPPCFG: SPP CONFIGURATION REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 CLKCFG1:CLKCFG0: SPP Clock Configuration bits

1x = CLK1 toggles on read or write of an Odd endpoint address;
CLK2 toggles on read or write of an Even endpoint address
01 = CLK1 toggles on write; CLK2 toggles on read
00 = CLK1 toggles only on endpoint address write; CLK2 toggles on data read or write
bit 5 CSEN: SPP Chip Select Pin Enable bit
1 = RB4 pin is controlled by the SPP module and functions as SPP CS output
0 = RB4 functions as a digital I/O port
bit 4 CLK1EN: SPP CLK1 Pin Enable bit
1 = RE0 pin is controlled by the SPP module and functions as SPP CLK1 output
0 = RE0 functions as a digital I/O port
bit 3-0 WS3:WS0: SPP Wait States bits
1111 = 30 additional wait states
1110 = 28 additional wait states
• •
• •
0001 = 2 additional wait states
0000 = 0 additional wait states

18.1.2 CLOCKING DATA 18.1.3 WAIT STATES

The SPP has four control outputs: The SPP is designed with the capability of adding wait
• Two separate clock outputs (CK1SPP and states to read and write operations. This allows access
CK2SPP) to parallel devices that require extra time for access.
• Output enable (OESPP) Wait state clocking is based on the data source clock.
• Chip select (CSSPP) If the SPP is configured to operate as a USB endpoint,
then wait states are based on the USB clock. Likewise,
Together, they allow for several different configurations if the SPP is configured to operate from the micro-
for controlling the flow of data to slave devices. When controller, then wait states are based on the instruction
all control outputs are used, the three main options are: rate (FOSC/4).
• CLK1 clocks endpoint address information while The WS3:WS0 bits set the wait states used by the SPP,
CLK2 clocks data with a range of no wait states to 30 wait states, in multi-
• CLK1 clocks write operations while CLK2 clocks ples of two. The wait states are added symmetrically to
reads all transactions, with one-half added following each of the
• CLK1 clocks Odd address data while CLK2 clocks two clock cycles normally required for the transaction.
Even address data Figure 18-3 and Figure 18-4 show signalling examples
with 4 wait states added to each transaction.
Additional control options are derived by disabling the
CK1SPP and CSSPP outputs. These are enabled or
18.1.4 SPP PULL-UPS
disabled with the CLK1EN and CSEN bits, respectively,
located in Register 18-2. The SPP data lines (SPP<7:0>) are equipped with
internal pull-ups for applications that may leave the port
in a high-impedance condition. The pull-ups are
enabled using the control bit, RDPU (PORTE<7>).

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FIGURE 18-2: TIMING FOR MICROCONTROLLER WRITE ADDRESS, WRITE DATA AND
READ DATA (NO WAIT STATES)

FOSC/4

OESPP

CSSPP

CK1SPP

CK2SPP

SPP<7:0> ADDR DATA DATA

Write Address Write Data Read Data

MOVWF SPPEPS MOVWF SPPDATA MOVF SPPDATA, W

FIGURE 18-3: TIMING FOR USB WRITE ADDRESS AND DATA (4 WAIT STATES)

USB Clock

OESPP

CSSPP

CK1SPP

CK2SPP

SPP<7:0> Write Address Write Data

2 Wait States 2 Wait States 2 Wait States 2 Wait States

FIGURE 18-4: TIMING FOR USB WRITE ADDRESS AND READ DATA (4 WAIT STATES)

USB Clock

OESPP

CSSPP

CK1SPP

CK2SPP

SPP<7:0> Write Address Read Data

2 Wait States 2 Wait States 2 Wait States 2 Wait States

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18.2 Setup for USB Control 18.3.1 SPP INTERRUPTS
When the SPP is configured for USB operation, data When owned by the microcontroller core, control can
can be clocked directly to and from the USB peripheral generate an interrupt to notify the application when
without intervention of the microcontroller; thus, no each read and write operation is completed. The
process time is required. Data is clocked into or out interrupt flag bit is SPPIF (PIR1<7>) and is enabled by
from the SPP with endpoint (address) information first, the SPPIE bit (PIE1<7>). Like all other microcontroller
followed by one or more bytes of data, as shown in level interrupts, it can be set to a low or high priority.
Figure 18-5. This is ideal for applications that require This is done with the SPPIP bit (IPR1<7>).
isochronous, large volume data movement.
18.3.2 WRITING TO THE SPP
The following steps are required to set up the SPP for
USB control: Once configured, writing to the SPP is performed by
writing to the SPPEPS and SPPDATA registers. If the
1. Configure the SPP as desired, including wait SPP is configured to clock out endpoint address infor-
states and clocks. mation with the data, writing to the SPPEPS register
2. Set the SPPOWN bit for USB ownership. initiates the address write cycle. Otherwise, the write is
3. Set the buffer descriptor starting address started by writing the data to the SPPDATA register.
(BDnADRL:BDnADRH) to FFFFh. The SPPBUSY bit indicates the status of the address
4. Set the KEN bit (BDnSTAT<5>) so the buffer and the data write cycles.
descriptor is kept indefinitely by the SIE. The following is an example write sequence:
5. Set the INCDIS bit (BDnSTAT<4>) to disable 1. Write the 4-bit address to the SPPEPS register.
automatic buffer address increment. The SPP automatically starts writing the
6. Set the SPPEN bit to enable the module. address. If address write is not used, then skip
to step 3.
Note: If a USB endpoint is configured to use the
2. Monitor the SPPBUSY bit to determine when the
SPP, the data transfer type of that
address has been sent. The duration depends
endpoint must be isochronous only.
on the wait states.
3. Write the data to the SPPDATA register. The
18.3 Setup for Microcontroller Control
SPP automatically starts writing the data.
The SPP can also act as a parallel port for the 4. Monitor the SPPBUSY bit to determine when the
microcontroller. In this mode, the SPPEPS register data has been sent. The duration depends on
(Register 18-3) provides status and address write the wait states.
control. Data is written to and read from the SPPDATA 5. Go back to steps 1 or 3 to write a new address
register. When the SPP is owned by the or data.
microcontroller, the SPP clock is driven by the
instruction clock (FOSC/4). Note: The SPPBUSY bit should be polled to
make certain that successive writes to the
The following steps are required to set up the SPP for SPPEPS or SPPDATA registers do not
microcontroller operation: overrun the wait time due to the wait state
1. Configure the SPP as desired, including wait setting.
states and clocks.
2. Clear the SPPOWN bit.
3. Set SPPEN to enable the module.

FIGURE 18-5: TRANSFER OF DATA BETWEEN USB SIE AND SPP

Write USB endpoint number to SPP

Write outbound USB data to SPP or

read inbound USB data from SPP

Endpoint
Byte 0 Byte 1 Byte 2 Byte 3 Byte n
Address

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18.3.3 READING FROM THE SPP 3. Read the data from the SPPDATA register; the
data from the previous read operation is
Reading from the SPP involves reading the SPPDATA
returned. The SPP automatically starts the read
register. Reading the register the first time initiates the
cycle for the next read.
read operation. When the read is finished, indicated by
the SPPBUSY bit, the SPPDATA will be loaded with the 4. Monitor the SPPBUSY bit to determine when the
current data. data has been read. The duration depends on
the wait states.
The following is an example read sequence:
5. Go back to step 3 to read the current byte from
1. Write the 4-bit address to the SPPEPS register. the SPP and start the next read cycle.
The SPP automatically starts writing the
address. If address write is not used then skip to
step 3.
2. Monitor the SPPBUSY bit to determine when the
address has been sent. The duration depends
on the wait states.

REGISTER 18-3: SPPEPS: SPP ENDPOINT ADDRESS AND STATUS REGISTER

R-0 R-0 U-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RDSPP: SPP Read Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a read from the SPP
0 = The last transaction was not a read from the SPP
bit 6 WRSPP: SPP Write Status bit (Valid when SPPCON<SPPOWN> = 1, USB)
1 = The last transaction was a write to the SPP
0 = The last transaction was not a write to the SPP
bit 5 Unimplemented: Read as ‘0’
bit 4 SPPBUSY: SPP Handshaking Override bit
1 = The SPP is busy
0 = The SPP is ready to accept another read or write request
bit 3-0 ADDR3:ADDR0: SPP Endpoint Address bits
1111 = Endpoint Address 15
• •
• •
0001
0000 = Endpoint Address 0

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TABLE 18-1: REGISTERS ASSOCIATED WITH THE STREAMING PARALLEL PORT
Reset
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Values
on page
SPPCON(3) — — — — — — SPPOWN SPPEN 57
(3)
SPPCFG CLKCFG1 CLKCFG0 CSEN CLK1EN WS3 WS2 WS1 WS0 57
SPPEPS(3) RDSPP WRSPP — SPPBUSY ADDR3 ADDR2 ADDR1 ADDR0 57
(3)
SPPDATA DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 57
PIR1 SPPIF(3) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 56
PIE1 SPPIE(3) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 56
IPR1 SPPIP(3) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 56
(3)
PORTE RDPU — — — RE3(1,2) RE2(3) RE1(3) RE0(3) 56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the Streaming Parallel Port.
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All other bits are
implemented only when PORTE is implemented (i.e., 40/44-pin devices).
3: These registers and/or bits are unimplemented on 28-pin devices.

DS39632E-page 196 © 2009 Microchip Technology Inc.