Real-Time Concepts for

Embedded Systems

Author: Qing Li with

Caroline Yao

ISBN: 1-57820-124-1
CMPBooks
Chapter 10
Exceptions and Interrupts
Outline
† 10.1 Introduction
† 10.2 What are Exceptions and Interrupts?
† 10.3 Applications of Exceptions and Interrupts
† 10.4 A Closer Look at Exceptions and Interrupts
† 10.5 Processing General Exceptions
† 10.6 The Nature of Spurious Interrupts
10.1 Introduction
† Exceptions and interrupts
„ Provided by most of the processor architectures to
allow for the disruption of the processor's normal
execution path
† Many operating systems provide wrapper
functions to handle exceptions and interrupts
„ To shield the embedded programmer from low-
level details
10.2 What are Exceptions and
Interrupts?
† Exception
„ Any event that disrupts the normal execution of
the processor and forces the processor into
execution of special instructions in a privileged
state
„ Two categories:
† Synchronous exceptions
† Asynchronous exceptions
What are Exceptions and Interrupts?
(Cont.)
† Synchronous exceptions (exception)
„ Raised by internal events, such as events generated by the
execution of processor instructions
„ For example, alignment exception, division by zero

† Asynchronous exceptions (interrupt)

„ Raised by external events that are associated with
hardware signals from external hardware devices
„ For example, system reset exception
10.3 Applications of Exceptions and
Interrupts
† Exceptions and interrupts help the embedded
engineer in three areas:
„ Internal errors and special conditions
management

„ Hardware concurrency

„ Service requests management

10.3.1 Internal Errors and Special
Conditions Management
† Exceptions are either
„ Error conditions that the processor detects while
executing instructions
„ Special conditions that the processor detects while
executing instructions.
† Error conditions:
„ Division by zero, over-flow, or other math error
„ Memory read or write failures
„ Attempts to access floating-point hardware when not
installed
„ ……
Internal Errors and Special
Conditions Management (Cont.)
† Special conditions
„ Exceptions generated by special instructions
† For example, TRAP instruction on the Motorola 68K
processor family, SWI in ARM series processor
† Allow a program to force the processor to move into
privileged execution mode, consequently gaining
access to a privileged instruction set
„ Trace exception generated by the break point
feature available on many processor architectures
† The debugger agent handles this exception, which
makes using a host debugger to perform software
break point and code stepping possible
10.3.2 Hardware Concurrency and
Service Request Management
† Use external interrupts for hardware concurrency
„ Many external hardware devices can perform device-
specific operations in parallel to the core processor
„ After one work is complete, the device triggers an
external interrupt to the core processor to indicate that the
device is now ready to accept more commands
† e.g., disk access or network packet transmit
† Use external interrupts for requesting service from
an external hardware device to an embedded
processor
„ e.g., preprogrammed time interval has expired
„ e.g., arrival of packets
10.4 A Closer Look at Exceptions
and Interrupts
† It is possible there exists another level of priorities
among the external interrupts
„ Imposed and enforced by the interrupt controller
† For properly installing general exception handlers
and to write correct general exception handlers, one
should understand
„ Hardware sources
„ How does hardware implement the transfer of control
„ Mechanisms for determining where control vectors reside
10.4.1 Programmable Interrupt
Controllers and External Interrupts
† Programmable interrupt controller (PIC)
„ Implementation-dependent
„ Provide two main functionalities:
† Prioritizing multiple interrupt sources
„ The highest priority interrupt is presented to the core CPU
for processing

† Offloading the core CPU with the processing required

to determine an interrupt's exact source
Programmable Interrupt Controller
† An external source generates interrupts by asserting a
physical signal on the interrupt request line.
† Each interrupt request line has a priority assigned to it.
 Specifies where in memory
the ISR must be installed
Interrupt table
Source Priority Vector IRQ Max Description
Address Freq.
Airbag Highest 14h 8 N/A Deploys airbag
Sensor
Break High 18h 7 N/A Deploys the
Sensor breaking system
Fuel Level Med 1Bh 6 20Hz Detects the level
Sensor of gasoline
Real-Time Low 1Dh 5 100Hz Clock runs at
Clock 10ms ticks
Programmable Interrupt Controller
(Cont.)
† Designing and implementing better ISRs that
allow for nested interrupts
„ The ability of a higher priority interrupt source to
preempt the processing of a lower priority
interrupt
10.4.2 Classification of General
Exceptions
† Most of the more recent processors have these types
of exceptions:
„ Asynchronous-non-maskable (non-maskable interrupts)
† e.g. hardware-reset exceptions
„ Asynchronous-maskable (maskable interrupts)
† Can be blocked or enabled by software
„ Synchronous-precise
† Processor's program counter points to the exact instruction that
caused the exception - offending instruction, where to resume
execution upon return from the exception
„ Synchronous-imprecise
Classification of General Exceptions
(Cont.)
† Many embedded processors have a dedicated
non-maskable interrupt (NMI) request line
„ Any device connected to the NMI request line is
allowed to generate an NMI
† Imprecise exception
„ If an embedded processor implements heavy
pipelining or pre-fetch algorithms, it can often be
impossible to determine the exact instruction and
associated data that caused an exception.
10.4.3 General Exception Priorities
† General exceptions are handled according to
the following priority
„ However, not every processor uses the same
order

Highest Asynchronous Non-maskable

Synchronous Precise
Synchronous Imprecise
Lowest Asynchronous Maskable
System-Wide Priority Scheme
10.5 Processing General Exceptions
† When an exception or an external interrupt is raised,
the processor takes the following steps :
„ Save the current processor state information
„ Load the exception or interrupt handling function into the
program counter
„ Transfer control to the handler function and begin
execution
„ Restore the processor state information after the handler
function completes
„ Return from the exception or interrupt and resume
previous execution
Processing General Exceptions
(Cont.)
† A typical handler function does the following:
„ Switch to an exception frame or an interrupt stack
„ Save additional processor state information
„ Mask the current interrupt level but allow higher
priority interrupts to occur
„ Perform a minimum amount of work so that a
dedicated task can complete the main processing
10.5.1 Installing Exception Handlers
† Install exception service routines (ESRs) and
interrupt service routines (ISRs) into general
exception table (also called vector table) before
exceptions and interrupts can be handled
„ ESRs: during system initialization time

„ ISRs: during driver initialization time

10.5.2 Saving Processor States
† To ensure a proper return of program
execution after the ESR/ISR is complete,
ESR/ISR should save processor states,
including
„ Status register (SR) - contains the current
processor execution status bits
„ Program counter (PC) - contains the returning
address for resuming execution after exception
Store Processor State Information
onto Stack
† Whose stack is used during the exception and
interrupt processing?
† In some embedded architectures, two separate
stacks are used:
„ user stack (USP): used when processor executes
in non-privileged mode
„ supervisor stack (SSP): used when the processor
executes in privileged mode
„ e.g., Motorola's 68000 microprocessors
Store processor state information
onto stack
Task TCB and stack
10.5.3 Loading and Invoking
Exception Handlers
† In many embedded processor architectures,
external interrupts can be disabled or enabled
through a processor control register.

† This control register directly controls the

operation of the PIC and determines which
interrupts the PIC raises to the processor.
Loading and Invoking Exception
Handlers (Cont.)
† A disabled interrupt is also called a masked
interrupt.
„ The PIC ignores a disabled interrupt.
† A pending interrupt is an unacknowledged
interrupt
„ Occurs when the processor is currently processing
a higher priority interrupt
† An active interrupt is the one that the
processor is acknowledging and processing.
Loading exception vector
10.5.4 Nested Exceptions and Stack
Overflow
† Nested exceptions
„ Refer to the ability for higher priority exceptions
to preempt the processing of lower priority
exceptions
„ Application stack must be large enough to
accommodate
† The maximum requirements for the application's own
nested function invocation
† And the possible maximum exceptions or interrupt
nesting
Interrupt Nesting
Nested Exceptions and Stack
Overflow
† However, if not enough stack space is allocated,
stack overflow would occur
„ Note that without a MMU, no bounds checking is
performed when using a stack as a storage medium
† Two solutions to stack overflow :
„ Increasing application's stack size
† To accommodate all possibilities and the deepest levels of
exception and interrupt nesting
„ ESR or ISR switch to its own exception stack, called an
exception frame
† Requires far less total memory than increasing every task stack
by the necessary amount
Nested Interrupts and Stack Overflow
10.5.5 Exception Handlers
† Usually the exception handler has two parts:
„ The first part executes in the exception or
interrupt context
„ The second half executes in a task context

† Exception frame
„ also called the interrupt stack in the context of
asynchronous exceptions
Exception Frame
† Two main reasons exist for needing an
exception frame:
„ To handle nested exceptions
„ Pass parameters during function invocation in a
high-level programming language, such as C
† The common approach to the exception frame:
„ ESR or ISR allocates a block of memory, either
statically or dynamically, before installing itself
into the system
Switching SP to Exception Frame
Differences Between ESR and ISR
† An ESR in many cases cannot prevent other
exceptions from occurring

† While an ISR can prevent interrupts of the

same or lower priority from occurring
Three ways to mask interrupts
† Disable the device
„ So that it cannot assert additional interrupts
† Mask the interrupts of equal or lower priority levels
„ Allowing higher priority interrupts to occur
„ The device can continue to generate interrupts, but the
processor ignores them.
† Disable the global system-wide interrupt request line
to the processor (the line between PIC and core
processor)
„ Interrupts of any priority level do not reach the processor.
„ Equivalent to masking interrupts of the highest priority
level
Reasons for an ISR to Disable
Interrupts
† The ISR tries to reduce the total number of
interrupts raised by the device

† The ISR is non-reentrant

† The ISR needs to perform some atomic

operations
Storage for Interrupt Mask
† Which interrupts or interrupt levels are
disabled are kept in either
„ The system status register
„ An interrupt mask register (IMR)

† IMR only applies to maskable asynchronous

exceptions
Exception Timing
† Keeping the ESR or ISR short
† Hardware designer's job
„ Use the proper interrupt priority at the PIC level
† ISR programmer's responsibility
„ Know the timing requirements of each device when an
ISR runs with either the same level or all interrupts
disabled
„ Be aware of the interrupt frequency of each device that
can assert an interrupt
† The allowed duration for an ISR to execute with interrupts
disabled without affecting the system
Interrupt Miss
† Interrupt miss
„ The situation in which an interrupt is asserted but
the processor could not record the occurrence due
to some busy condition
† An ISR, when executing with interrupts
disabled, can cause the system to miss
interrupts if the ISR takes too long
† Real-time tasks that have stringent deadlines
can also be affected by a poorly designed ISR
Exception Timing
Exception timing (Cont.)
† TA: device interrupt frequency
† TB: Interrupt latency:
„ The interval between the time when the interrupt is raised
and the time when the ISR begins to execute
„ Interrupt latency is attributed to:
† Amount of time for the processor to acknowledge the interrupt
and perform initial housekeeping work
† A higher priority interrupt is active at the time.
† The interrupt is disabled and then later re-enabled by software
† Interrupt response time = interrupt latency +
interrupt processing time
Partition the ISR into Two Pieces
† It is inefficient for the entire processing to be
done with the context of the interrupt, i.e.,
interrupt disabled

† Thus, the interrupt processing is often divided

into two pieces
Partition the ISR into Two Pieces
† First section of ISR running in the context of the
interrupt
„ The service request is acknowledged and the device is put
into a known operational state so it can resume operation
„ Packages the device service request and sends it to the
remaining section of the ISR

† Another section running in the context of a task

„ Interrupt is enabled and often implemented as a daemon
process
Partition the ISR into two pieces
(Cont.)
† There are two main reasons why we partition
the ISR
„ Reduce the processing time within the interrupt
context
„ It might not the case that interrupt having higher
priority than a running task
† For example, a LED failure interrupt is less important
than a task sends a communication reply
† Thus, we must minimize the execution time in the
interrupt context
Interrupt Processing in Two Contexts
Benefits to Partition the ISR into
Two Pieces
† Lower priority interrupts can be handled with
less priority than more critical tasks running
in the system.
† Reduces the chance of missing interrupts
† Affords more concurrency
„ Because devices are being serviced minimally,
then they can continue their normal operations
Benefits to Partition the ISR into
Two Pieces
† However, the interrupt response time
increases
„ TD = TB + TC + TE + TF
General Guides
† General guides for architectures allow interrupt
nesting:
„ An ISR should disable interrupts of the same level if the
ISR is non-reentrant
„ An ISR should mask all interrupts if it needs to execute a
sequence of code as one atomic operation
„ An ISR should avoid calling non-reentrant functions.
† Some standard library functions are non-reentrant,
„ Such as many implementations of malloc and printf.
† E.g., tasks is in the midst of the "malloc" function and interrupts
occur, the resulting behavior can be catastrophic if the ISR calls
this same non-reentrant function
„ An SR must never make any blocking or suspend calls.
† Making such a call might halt the entire system.
10.6 The Nature of Spurious
Interrupts
† Spurious interrupt
„ A signal of very short duration on one of the
interrupt input lines, and it is likely caused by a
signal glitch
† An external device uses a triggering
mechanism to raise interrupts to the core
processor
„ Level triggering
„ Edge triggering (rising edge or falling edge)
Edge Triggering on Either Rising or
Falling edge
Level Triggering
Real Signals
Occurrence of Spurious Interrupts
† Signals, whether for interrupts or other inputs,
might not be as clean as a developer might
envision them
„ These signals can represent a potential source for
sporadic behavior
„ Due to unstableness of the interrupt signal.