Basic PMOS structure

p-channel device (n- and p-type regions reversed.)

n-type source
p-type substrate
& drain

gate oxide
e
gat e
i de d
o x oxi

wid
th (
W)

metal contacts

EE 230 PMOS – 1
Critical dimensions

oxide thickness: typical 1 - 10 nm.

oxide thickness (tox)

e
gat e
d
oxi

in
dra
( L )
gth
wid len
width
th ((W e
W)) u rc
s o
gate length (distance from source
to drain) – currently
width: typical L to 10 L as small as 20 nm.
(W/L ratio is important)

EE 230 PMOS – 2
 Will current flow?
Apply a voltage between drain and source (VDS) – there is always as
reverse-biased diode blocking current flow.
VDS

+
–
gate

p p
source drain
n

To make current flow, we need to create a hole inversion layer.

EE 230 PMOS – 3
 The PMOS capacitor
Same as the NMOS capacitor, but with n-type substrate.

body gate Cox

contact

– + – +
–
– + – – –
+ – – – –
– + –
+ – –
– – – – –
substrate (body)

In the substrate, there are lots of electrons (majority carriers), and

relatively few holes (minority carriers).

EE 230 PMOS – 4
 vGB > 0

+
–
body gate
Apply a positive voltage contact
to the gate – electron
– – – – – –+ – – – –
accumulation.
– – – – – – – –
– – +
+ + + ++

substrate (body)
vGB < 0

+
–
Apply a (smallish)
negative voltage to the body gate
contact
gate. Electrons are pushed
away and a few holes are + + + + + –
attracted – carrier – + – – –
+
– –
–
– – – – –
depletion. – – –
– – – –
substrate (body)
EE 230 PMOS – 5
 vGB < VT

+
–
body gate
contact
+ + + + + + +++ + + + + + + +
– – – – – – – –
– – – – –
– – – – –
– –
substrate (body)
Applying increasing negative voltages to the gate causes more and more
holes to pile up in a sheet underneath the oxide. At some particular
voltage, the hole concentration in the sheet will be just as big as the
electron concentration in the rest of the substrate. This is hole inversion
and the voltage needed to create the inversion layer is the threshold
voltage for the PMOS.
For PMOS, the threshold voltage is negative.

Making vGB even negative simply increases the hole concentration in the
sheet.
EE 230 PMOS – 6
 Summary of PMOS capacitor operation
Through the application of the gate voltage, we can control what is
happening with carriers under the gate.

vGB > 0 electron accumulation

VT < vGB < 0 carrier depletion

inversion –
vGB < VT hole sheet forms.
(Note: VT is negative.)

EE 230 PMOS – 7
 Creating a hole inversion layer connects the source to the drain. The
PMOS is “on”.

+
–
vGS < VT
gate

body p p
hole inversion layer
source electrons drain
iD
n

For now, we connect the source to the body and apply the controlling
voltage between the gate and the source. This is OK for the time
being, but we will have to revisit the issue of the body connection
later. With the drain also at ground, the inversion layer (channel) is
uniform between source and drain.
EE 230 PMOS – 8
 Drain current
With the hole inversion layer formed (vGS < VT), current can flow by
applying a negative voltage at the drain. This creates an electric field that
will push holes from the source, through the inversion layer channel, and
on into the drain. The moving holes represent a drain current flowing
from source to drain. (Opposite the current for an NMOS!)

vDS < 0

+
–
+
–
vGS < VT
gate

body p p
hole inversion layer
source drain
holes
iD
n

EE 230 PMOS – 9
 +
–
vDS < 0

+
–
vGS < VT
gate

body p p
hole inversion layer
source drain
holes
iD
n

If vDS is kept small, the current flow is

“ohmic” – like a resistor. RDS depends on
the how much gate voltage is applied
(determining the hole concentration in
the inversion layer) and the physical
dimensions of the PMOS.
vDS
iD
RDS
EE 230 PMOS – 10
 +
–
vDS < 0

+
–
vGS < VT
gate

body p p
hole inversion layer
source drain
holes
iD
n

But as vDS becomes more negative, the

hole concentration at the drain is reduced
– the channel is no longer uniform and it
is becoming more resistive. The i-v curve
becomes non-linear, becoming parabolic.

iD = K 2 (vGS VT ) vDS v2DS

1 W
K = μCox
2 L
EE 230 PMOS – 11
 +
–
vDS < 0

+
–
vGS < VT
gate

body p p
hole inversion layer
source drain
holes
iD
n

At sufficiently negative values for vDS,

the channel becomes “pinched down” to
its minimum possible value. Then the
current saturates. The pinch-down occurs
when vDS < vGS – VT. Then the current in
saturation is given by:
2
iD = K [vGS VT ]

EE 230 PMOS – 12
 Summary of PMOS equations

vGS > VT iD = 0 off

vGS < VT ohmic or

iD = K[2(vGS – VT)vDS – vDS 2]
vDS > vGS – VT linear

vGS < VT
iD = K[vGS – VT]2 saturation
vDS < vGS – VT

1 W
K = μCox
2 L

VT < 0

Note the equations are identical

to the NMOS equations. For a
PMOS, vGS and vDS are both
negative and the current flows
from source to drain.
EE 230 PMOS – 13