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Faculty: MD Ehtashamoul Haque Paper Code: Cse-306-F (Cao)

This document outlines a lecture plan for a Computer Architecture and Organization course. It is divided into 4 sections covering 37 total lecture periods. Section A (13 periods) covers basic digital logic, computer organization levels, CPU components, and performance metrics. Section B (11 periods) discusses CPU architecture types, datapath, pipelining, and memory hierarchy including caches. Section C (13 periods) focuses on parallelism including instruction level parallelism, multiprocessors, and basics of logic design. The final section D (8 periods) addresses instruction set classification, addressing modes, instruction sets, and 8086 simulation. Relevant reading is suggested from Computer System Architecture by M. Mano.

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63 views2 pages

Faculty: MD Ehtashamoul Haque Paper Code: Cse-306-F (Cao)

This document outlines a lecture plan for a Computer Architecture and Organization course. It is divided into 4 sections covering 37 total lecture periods. Section A (13 periods) covers basic digital logic, computer organization levels, CPU components, and performance metrics. Section B (11 periods) discusses CPU architecture types, datapath, pipelining, and memory hierarchy including caches. Section C (13 periods) focuses on parallelism including instruction level parallelism, multiprocessors, and basics of logic design. The final section D (8 periods) addresses instruction set classification, addressing modes, instruction sets, and 8086 simulation. Relevant reading is suggested from Computer System Architecture by M. Mano.

Uploaded by

Ehtasham
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Faculty: MD EHTASHAMOUL HAQUE Paper Code: CSE-306-F (CAO)

Lecture Plan for Even Semester for Computer Architecture & Organisation Paper Code CSE-306-F

Ref No Topics Planned No of Books and Relevant


Lectures Needed Page No
Section-A (Planned : 13 Periods )
1.1 Boolean algebra and Logic gates, 02
Combinational logic blocks(Adders,
Multiplexers, Encoders, de-coder),
1.2 Sequential logic blocks(Latches, Flip-Flops, 03
Registers, Counters) Store
1.3 program control concept, Flynn’s classification 02
Computer System
of computers (SISD, MISD, MIMD);
1.4 01
Architecture by M.
Multilevel viewpoint of a machine: digital
logic, micro architecture, ISA, Mano, 2001,
1.5 operating systems, high level language; 02 Prentice-Hall.
structured organization;
1.6 CPU, caches, main memory, secondary 02
memory units & I/O;
1.7 Performance metrics; MIPS, MFLOPS. 01
Section-B (Planned: 11 Periods )
2.1 CPU Architecture types (accumulator, register, 01
stack, memory/ register)
2.2 detailed data path of a typical register based 02
CPU, Fetch-Decode-Execute cycle (typically 3
to 5 stage);
2.3 microinstruction sequencing, implementation of 02
control unit,
2.4 Enhancing performance with pipelining. 01 Computer System
2.5 The need for a memory hierarchy (Locality of 01
Architecture by M.
reference principle, Memory hierarchy in
practice: Mano, 2001,
2.6 Cache, main memory and secondary memory, 02 Prentice-Hall.
Memory parameters: access/ cycle
time, cost per bit);
2.7 Main memory (Semiconductor RAM & ROM 01
organization, memory
expansion, Static & dynamic memory types);
2.8 Cache memory (Associative & direct mapped 01
cache organizations.
Section-C (Planned: 13 Periods)
3.1 Goals of parallelism (Exploitation of 01
concurrency, throughput enhancement);
3.2 Amdahl’s law; 01
3.3 Instruction level parallelism (pipelining, super 01
scaling –basic features); Processor level Computer System
parallelism (Multiprocessor systems overview). Architecture by M.
3.4 Instruction codes, computer register, computer 02 Mano, 2001,
instructions, timing and control, instruction Prentice-Hall.
cycle
3.5 Type of instructions, memory reference, 02
register reference. I/O reference,

Page 1 of 2
Faculty: MD EHTASHAMOUL HAQUE Paper Code: CSE-306-F (CAO)

3.6 Basics of Logic Design, accumulator logic, 2


Control memory,
3.7 Address sequencing, micro-instruction formats, 2
micro-program sequencer,
3.8 Stack Organization, Instruction Formats, Types 2
of interrupts; Memory Hierarchy.
Section-DNP Hard and NP Complete Problems: ( Planned: 08 Periods )
4.1 Instruction set based classification of 01
processors (RISC, CISC, and their
comparison);
4.2 Addressing modes: register, immediate, direct, 02 Computer System
indirect, indexed; Architecture by M.
4.3 Operations in the instruction 02 Mano, 2001,
set; Arithmetic and Logical, Data Transfer, Prentice-Hall.
Control Flow;
Instruction set formats (fixed, variable, 1
hybrid);
4.4 Language of the machine: 8086 ; simulation 02
using MSAM.

Book 1. Computer System Architecture by M. Mano, 2001, Prentice-Hall.


Book 2. Computer Organisation & Architecture: Designing for performance by W. Stallings,
4th edition, 1996, Prentice-Hall International edition.

Page 2 of 2

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