0% found this document useful (0 votes)
85 views12 pages

Chariya Assignment 5

This document contains Lakshan M.H.C's assignment for the course CS 2842 - Computer Systems. The assignment contains questions about computer memory management techniques including relocation, fixed and dynamic partitioning, paging, segmentation, hierarchical page tables, inverted page tables, transaction lookaside buffers, associative mapping, file types, indexed sequential files, and input/output methods like programmed I/O and interrupt driven I/O.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
85 views12 pages

Chariya Assignment 5

This document contains Lakshan M.H.C's assignment for the course CS 2842 - Computer Systems. The assignment contains questions about computer memory management techniques including relocation, fixed and dynamic partitioning, paging, segmentation, hierarchical page tables, inverted page tables, transaction lookaside buffers, associative mapping, file types, indexed sequential files, and input/output methods like programmed I/O and interrupt driven I/O.
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

ASSIGNMENT 5

CS 2842 – Computer Systems


Index No: 090288T
Name: Lakshan M.H.C
FIELD: ELECTRICAL ENG.
D.O.S: 08/19/2010
CS 2842 – Computer Systems

Assignment 5

Index No: 090288T

Name: Lakshan M.H.C

QUESTION 01

 Relocation

Assume that we want to initiate a program. Then the program should be loaded into memory and

the actual (absolute) memory locations are determined. A process may occupy different partitions

which means different absolute memory locations during execution

a. Swapping

b. Compaction

Some terms :

 Logical address: Reference to a memory location independent of the current assignment of

data to memory.

 Relative address: Address expressed as a location relative to some known point.

 Physical or Absolute address: The absolute address or actual location in main memory.
Base register is the starting address for the process.

Bounds register is the ending location address of the process.

Base register values and bound register values are set when the process is loaded or when the

process is swapped in.

Hardware Support for Relocation


Execution process of the Relocation (step by step)

I. The value of the base register is added to a relative address to produce an absolute

address

II. The resulting address is compared with the value in the bounds register

III. If the address is not within bounds, an interrupt is generated to the operating system

 Protection and sharing

Memory references are valid if pointing to locations that belong to the current process itself,
however usually prohibited if referring to locations in other processes, whether accidental or
intentional.

Any protection mechanism must allow several processes to access the same portion of main
memory. For example, multiple processes may use a same system library and it is natural to load
one copy of the library in main memory and let it shared by those processes.

QUESTION 02

 Fixed Partitioning
In fixed partitioning, partitioning is done with equal sizes. So any process whose size is less than or

equal to the partition size can be loaded into an available partition. If there is no ready or running

state process, the operating system can swap a process out of a partition.

Problems:

o The programmer must design the program with overlays relavant to the fixed partitioning

size, if a program may not fit in a partition, errors can be happened.

o Any program, no matter how small, occupies an entire partition. This results in internal

fragmentation. Therefore main memory use is inefficient.

o The number of active processes is limited by the system ( limited by the pre-determined

number of partitions)

 Dynamic Partitioning

Partitions can be variable length and number, process is allocated exactly as much memory as

required. In dynamic partitioning no Internal Fragmentation but External Fragmentation is happened

when new processes initiating and old processes are winded up or swpapped. This can be resolve

using compaction method as OS moves processes so that they are contiguous but this is time

consuming and wastes CPU time. Allocating free block to a process is done by the OS with some

algorithms such as Best-fit algorithm, First-fit algorithm, Next-fit, Buddy system.


 Simple Paging

Main memory is partitioned into small equal fixed-size chunks and divides each process into the

same size chunks this chunks of a process are called pages and he chunks of memory are called

frames. This method OS maintains a page table for each process

– Contains the frame location for each page in the process

– Memory address consist of a page number and offset within the page

There is no External Fragmentation or Internal Fragmentation.

Main Memory

Frame no 0
1
2
3
4

 Simple Segmentation

Segmentation is similar to dynamic partitioning except with segmentation a program may occupy

more than one partition, and these partitions need not be contiguous. Segmentation eliminates

Internal Fragmentation but suffers from External Fragmentation as dynamic partitioning. Segments

may vary in length but there is a maximum segment length. Segmentation address consists with

two parts as a segment number and off set. In this method a process is broken up into a number
of smaller pieces so the external fragmentation should be less. A simple segmentation scheme

would make use of a segment table for each process and a list of free blocks of main memory.

Each segment table entry would have to give

• The starting address in main memory of the corresponding segment.

• The length of the segment, to assure that invalid addresses are not used.

QUESTION 03

Address translation process for a hierarchical page table with two level paging

This can be described with an example as following.

Let assume 32-bit machine with 4K page size(212). Then virtual(logical) memory address has
- a page number consisting of 20 bits.
- a page offset consisting of 12 bits.

Since the page table is paged, the page number is further divided into:
- a 10-bit root page number.
- a 10-bit page table number .
-
The first 10 bits of the virtual address points to the root page table and both root page table and
second 10 bit address pointed the memory location.

Thus, a logical address is as follows:

Page table number

10-bit 10-bit 12-bit Page offset

Root Page number


First 10 bits of the logical address is added with the initial address of the page table which is in the

main memory. Then the result is a Root table table’s address and value contain in that address is

added with the next 10 bits of the logical address. This result value indicates the Page table address

and the value contains of that address is the frame address. Finally frame address and offset is

connected to get the main memory actual address.

QUESTION 04

a) Inverted page tables

This is an alternative page table. While using page table its size is proportional to the virtual

memory address. In inverted page tables, the page number portion of a virtual address mapped into

a hash value using a simple hashing function. The hash value is a pointer to the inverted page

table, which contains the page table entries. There is one entry in the inverted page table for each

real memory page frame rather than one per virtual page. Because more than one virtual address

may map into the same hash table entry, a chaining technique used for managing the overflow.

The page table’s structure is called inverted because it indexes page table entries by frame number

rather than by virtual page number.


b) Transaction lookaside buffer

This is a table in the processor’s memory (cache) that contains information about the pages in

memory the processor has accessed recently. The table cross-references a program’s virtual

addresses with the corresponding absolute addresses in physical memory that the program has

most recently used. The TLB enables faster computing because it allows the address processing to

take place independent of the normal address-translation pipeline.

c) Associative Mapping

A main memory block can load into any line of cache. In this the memory address is interpreted as

tag and word. Tag uniquely identifies block of memory. Every line’s tag is examined for a match.

d) File

This can be defined as a collection of similar records. The file is referenced by name and it can be

treated as a single entity by users and applications. A file may be created and deleted. Usually at

the file level, access control restrictions.Different types of files store different types of information.

For example, program files store programs, whereas text files store text.

e) Indexed sequential file


Records in indexed sequential files are stored in the order that they are written to the disk. Records

may be retrieved in sequential order or in random order using a numeric index to represent the

record number in the file. The record size, specified when the file is created, may range from 1 to

8000 bytes.

When an indexed sequential file is opened, the record pointer is positioned at the first record.
Subsequent I/O operations change the location of the pointer.

For example, to read all the records from an indexed sequential file in order, you would open the
file and read the records without specifying an index. This would move through the file in sequential
order and end when the last record was read.

Application note: Indexed sequential files are commonly used for transaction files because they take
less disk space than keyed files, and are faster to read from beginning to end than a keyed file.

f) Programmed I/O
Programmed input/output is a method of transferring data between the CPU and a peripheral such

as a network adapter or an ATA storage device. In this the processor directly controls the peripheral

device. In general, programmed I/O happens when software running on the CPU uses instructions

that access I/O address space to perform data transfers to or from an I/O device. This is contrast

to Direct Memory Access (DMA) transfers.

g) Interrupt driven I/O

Whenever a data transfer to or from the managed hardware might be delayed for any reason, the

driver writer should implement buffering. Data buffers help to detach data transmission and

reception from the write and read system calls, and overall system performance benefits.

A good buffering mechanism leads to interrupt-driven I/O, in which an input buffer is filled at

interrupt time and is emptied by processes that read the device; an output buffer is filled by

processes that write to the device and is emptied at interrupt time.

You might also like