UNIT IV SYNCHRONOUS SEQUENTIAL CIRCUITS

Classification of Models – Moore and Mealy Model – Representation of Sequential circuits -

Analysis of Synchronous Sequential Circuits – Design of Synchronous Sequential circuit – State
Reduction – State Assignment.

Synchronous Sequential Circuit Asynchronous Sequential Circuit

 It is easy to design.  It is difficult to design.
 An unclocked flip flop or time
 A clocked flip flop acts as memory
delay is used as memory
element.
element.
 They are comparatively faster as
 They are slower as clock is involved.
no clock is used here.
 The states of memory element are  The states of memory element
affected only at active edge of clock, will change any time as soon as
if input is changed. input is changed.

SYNCHRONOUS SEQUENTIAL CIRCUIT:-

There are two distinct models by which a synchronous sequential logic circuit can be designed.
 In Moore model, the output depends only on present state and not on input.
 In Mealy model, the output is derived from present state as well as input.
The option to include input in output generation logic gives certain advantage to Mealy
model. Usually it requires less number of states and thereby less hardware to solve any problem.
Also, the output is generated one clock cycle earlier. However, there is one important
disadvantage associated with such circuit. The input transients, glitches etc. (if any) are directly
conveyed to the output. Also if we want output transitions to be synchronized while input can
change any time Mealy model is not preferred. In Moore model, the output remains stable over
entire clock period and changes only when there occurs a state change at clock trigger based on
input available at that time.
 Moore model Mealy model

Difference between moore and mealy model

Moore model Mealy model
In Moore model circuit outputs, also called In Mealy model circuit inputs, also known as
primary outputs are generated solely from primary inputs combine with memory
secondary outputs or memory values. elements to generate circuit output.
The output depends only on present state and The output is derived from present state as
not on input well as input
it requires less number of states and thereby it requires more number of states and thereby
less hardware to solve any problem more hardware to solve any problem
the output is generated one clock cycle the output is generated one clock cycle after
earlier.
The output remains stable over entire clock The glitches occurs
period and changes only when there occurs a
state change at clock trigger based on input
available at that time.

Analysis of Clocked (Synchronous) Sequential Circuits

The analysis of a clocked sequential circuit consists of obtaining a table of a diagram of
the time sequences of inputs, outputs and states.
Analysis Procedure
The Synchronous sequential circuit is summarised as given below:
1. Assign a state variable to each Flip-Flop in the synchronous circuit.
2. Write the excitation input functions for each Flip-Flop and also write the
Moore/ Mealy output functions.
3. Substitute the excitation input functions into the bistable equations for the
Flip-Flops to obtain the next sate output equations.
4. Obtain the state table and reduced form of the state table.
5. Draw the state diagram by using the second form of the state table.
It is the state table and/or state diagram that specifies the behavior of the circuit.
Notes:

 The flip-flop input equations are sometimes called the excitation equations.
 The state table is sometimes called a transition table
Analysis of Mealy Model:
1. A Sequential Circuit has two JK Flip-Flops A and B , one input (x) and one output(y). The
flip-flop input functions are,
JA=B+x JB=A’+x’
KA=1 KB=1
and the circuit output function, Y=xA’B
a) Draw the logic diagram of the Mealy Cicuit,
b) Tabulate the state Table
c) Draw the state diagram.
Solution:

State Table:
To obtain the next-state values of a sequential circuit with JK Flip-Flops, Use the
JK Flip-Flop Characteristics table.
Present Input Flip-Flop Inputs Next State Output
State
A B C JA=B+x KA=1 JB=A’+B’ KB=1 A(t+1) B(t+1) Y=xA’B
0 0 0 0 1 1 1 0 1 0
0 0 1 1 1 1 1 1 1 0
0 1 0 1 1 1 1 1 0 0
0 1 1 1 1 1 1 1 0 1
1 0 0 0 1 1 1 0 1 0
 1 0 1 1 1 0 1 0 0 0
1 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 1 0 0 0

Second Form of State Table:

Present Next State Output
State
X=0 X=1 X=0 X=1
A B A B A B Y y
0 0 0 1 1 1 0 0
0 1 1 0 1 0 0 1
1 0 0 1 0 0 0 0
1 1 0 0 0 0 0 0

2. A sequential circuit with two ‘D’ Flip-Flops A and B , one input(x) and one output(y).
The Flip-Flop input functions are:
DA=Ax+Bx
DB=A’x
And the circuit output function is Y=(A+B)x’
a) Draw the logic diagram of the Mealy Cicuit,
b) Tabulate the state Table
c) Draw the state diagram.
State Table:

Present State Input Flip-Flop Input Next state Output

A B x DA=Ax+Bx DB=A’x A(t+1) B(t+1) Y=(A+B)x’
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0
 Second Form of State Table:

Present State Next State Output

x=0 x=1 x=0 x=1
A B A B A B A B
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0

State Diagram:

3. A sequential circuit has two JK Flip_Flop A and B. Flip_Flop input functions are
JA=B ` JB=X’
KA=Bx’ KB=A x.
a) Draw the logic diagram of the Circuit,
b) Tabulate the state Table
c) Draw the state diagram.
Solution:
Logic Diagram:

The output function is not given in the problem. The output of the Flip_Flops may be
considered as the output of the circuit.
State Table:
To obtain the next state values of a sequential circuit with JK Flip_Flop, use the
JK Flip_Flop Charateristics table:
Present State Input Flip_Flop input Next state
A B x JA=B KA=Bx’ ` JB=X’ KA=Bx’ A(t+1) B(t+1)
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1
 Second form of state table:

Present State Next State

X=0 X=1
A B A B A B
0 0 0 1 0 0
0 1 1 1 1 0
1 0 1 1 1 0
1 1 0 0 1 1

State Diagram:

4. A Sequential Circuit has two JK Flip_Flops A and B two inputs x and y and one output z.
The Flip_Flop input equation and circuit output equations are
JA=Bx+B’y’ KA=B’xy’
JB=A’x KB=A+xy’
Z=Ax’y’+Bx’y’
a) Draw the logic diagram of the Circuit,
b) Tabulate the state Table
c) Derive the state equation.
 Solution:
Logic diagram:

State Table:
To obtain the next-state values of a sequential circuit with JK Flip_Flop , use the
JK Flip_Flop Characteristic table,
Presen Inpu Flip_Flop Input Next state Output
t State t
A B X Y JA=Bx+B’y’ KA=B’xy’ JB=A’x KB=A+xy’ A(t+1) B(t+1) z
0 0 0 0 1 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 1 1 1 1 1 0
0 0 1 1 0 0 1 0 0 1 0
0 1 0 0 0 0 0 0 0 0 1
0 1 0 1 0 0 0 0 0 0 0
0 1 1 0 1 0 1 1 1 1 0
0 1 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 0 1 1 0 1
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 1 0 0 1 0 0 0
1 0 1 1 0 0 0 1 1 0 0
1 1 0 0 0 0 0 1 1 0 1
1 1 0 1 0 0 0 1 1 0 0
1 1 1 0 1 0 0 1 1 0 0
1 1 1 1 1 0 0 1 1 0 0

5. Analysis the synchronous Mealy Machine and obtain its state diagram.

Solution:
The given synchronous Mealy Machine consists of two D Flip_Flop, one inputs and one
output. The Flip_Flop input functions are
DA=Y1’Y2X’
DB=x+Y1’Y2
 The circuit output function is Z=Y1Y2X
State Table:

Present State Input Flip_Flop Input Next State Output

Y1 Y2 X DA=Y1’Y2X’ DB=x+Y1’Y2 Y1(t+1) Y2(t+1) Z=Y1Y2X
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0
1 0 1 0 1 1 1 0
1 1 0 0 0 0 0 0
1 1 1 0 1 1 1 1

Second for of State table:

Present State Next State Output

X=0 X=1 X=0 X=1
Y1 Y2 Y1 Y2 Y1 Y2 Z1 Z2
0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 0
1 1 0 0 0 1 0 0
 State Diagram:

Analysis Of Moore Model

6. Analyze the synchronous Moore circuit and obtain its state diagram.

Solution:
Using the assigned variable Y1 and Y2 for the two JK Flip_Flops, we can write the
four excitation input equations and the Moore output equation as follows:
JA=Y2X KA=Y2’
JB=X KB=X” and output function Z=Y1Y2’

Present Input Flip_Flop inputs Next State Output

State
Y1 Y2 X JA=Y2X KA=Y2’ JB=X KB=X” Y1(t+1) Y2(t+1) Z=Y1Y2’
0 0 0 0 1 0 1 0 0 0
0 0 1 0 1 1 0 0 1 0
 0 1 0 0 0 0 1 0 0 0
0 1 1 1 0 1 0 1 1 0
1 0 0 0 1 0 1 0 0 1
1 0 1 0 1 1 0 0 1 1
1 1 0 0 0 0 1 1 0 0
1 1 1 1 0 1 0 1 1 0

Second form of State table:

Present State Next State Output

X=0 X=1 Y
Y1 Y2 Y1 Y2 Y1 Y2
0 0 0 0 0 1 0
0 1 0 0 1 1 0
1 0 0 0 0 1 1
1 1 1 0 1 1 0

State Diagram:
Here the output depends on the present state only and is independent of the input.
The two values inside each circle separated by a slash are for the present state and output.

7. A sequential circuit has two T Flip_Flop A and B. The Flip_Flop input functions are:
TA=Bx TB=x
y=AB
 a. Draw the logic diagram of the Circuit,
b. Tabulate the state Table
c. Draw the state diagram:
Solution:
Logic Diagram:

State table:
Present State Input Flip_Flop input Next State Output
A B x TA=Bx TB=x A(t+1) B(t+1) y=AB
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 1 0
0 1 1 1 1 1 0 0
1 0 0 0 0 1 0 0
1 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1
1 1 1 1 1 0 0 1

Second Form of State table:

Present State Next State Output
x=0 x=1 x=0 x=1
A B A B A B y y
 0 0 0 0 0 1 0 0
0 1 0 1 1 0 0 0
1 0 1 0 1 1 0 0
1 1 1 1 0 0 1 1
State Diagram:

State Reduction /Minimization

Any design process must consider the problem of minimizing the cost of the final circuit. The
two most obvious cost reductions are reductions in

 number of flip-flops
 number of gates.

The number of states in a sequential circuit is closely related to the complexity of the resulting
circuit. It is therefore desirable to know when two or more states are equivalent in all aspects.
The process of eliminating the equivalent or redundant states from a state table/diagram is known
as state reduction.

Example: Let us consider the state table of a sequential circuit shown in the below Table

Present State Next State Output

x=0x=1 x= x=
0 1
A B C 1 0
B F D 0 0
C D E 1 1
 D F E 0 1
E A D 0 0
F B C 1 0

Table. State table

It can be seen from the table that the present state A and F both have the same next states, B
(when x=0) and C (when x=1). They also produce the same output 1 (when x=0) and 0 (when
x=1). Therefore states A and F are equivalent. Thus one of the states, A or F can be removed
from the state table. For example, if we remove row F from the table and replace all F's by A's in
the columns, the state table is modified as shown in the below Table

.Present Next State Output Present Next Output

State State State x= x=
x=0 x=1 x= x= x= x= 0 1
0 1 0 1
A B C 1 0 A B C 1 0
B A D 0 0 B A D 0 0
C D E 1 1 C D B 1 1
D A E 0 1 D A B 0 1
E A D 0 0

State F removed Reduced state table

It is apparent that states B and E are equivalent. Removing E and replacing E's by B's results in
the reduce table shown in below Table.

The removal of equivalent states has reduced the number of states in the circuit from six to four.
Two states are considered to be equivalent if and only if for every input sequence the circuit
produces the same output sequence irrespective of which one of the two states is the starting
state.

Example 2. Reduce the number of states in the following state diagram and draw the reduced
state diagram.
Step 1: Determine the state table for the given state diagram

Next State Output

Present State
x=0 x=1 x=0 x=1
A B C 0 0
B D E 1 0
C C D 0 1
D A D 0 0
E C D 0 1
Step 2: Find the Equivalent States
From the above state table C and E generate exactly same next state and same output for every
possible set of inputs. The state C and E go to next states C and D and have output 0 and 1 for
X=0 and X=1. Therefore state E can be removedand replaced by C. The final reduced state table
is shown below

Next State Output

Present State
x=0 x=1 x=0 x=1
A B C 0 0
B D C 1 0
C C D 0 1
D A D 0 0
Reduced State Table
Step 3: Draw the State diagram

Design of Sequential Circuits

The design of a synchronous sequential circuit starts from a set of specifications and
culminates in a logic diagram or a list of Boolean functions from which a logic diagram can be
obtained. In contrast to a combinational logic, which is fully specified by a truth table, a
sequential circuit requires a state table for its specification. The first step in the design of
sequential circuits is to obtain a state table or an equivalence representation, such as a state
diagram.

A synchronous sequential circuit is made up of flip-flops and combinational gates. The

design of the circuit consists of choosing the flip-flops and then finding the combinational
structure which, together with the flip-flops, produces a circuit that fulfils the required
specifications.

The number of flip-flops is determined from the number of states needed in the circuit.

The recommended steps for the design of sequential circuits are set out below.
The type of Flip-flop to be used may be included in the deisgn specifications ormay depend what
is available to the designer.
Flip-Flop Applications
JK General Applications
D Shift Register
T Binary Counters

Example 1: Design a synchronous sequential circuit whose state diagram is shown in

Figure. The type of flip-flop to be use is J-K.

From the state diagram, we can generate the state

table shown in Table. Note that there is no output
section for this circuit. Two flip-flops are needed to
represent the four states and are
Renamed as Q0Q1. The input variable is labeled x.

Present State Next State Output Transitions Flip-flop inputs

Q0 Q1 x=0 x=1 Q0 Q1 JK
00 00 01 0 0 0 X
01 10 01 0 1 1 X
10 10 11 1 0 X 1
11 11 00 1 1 X 0
State table. Excitation table for
JK flip-flop
Excitation table of the circuit
Present State Next State Input Flip-flop Inputs
Q0 Q1 Q0 Q1 x J0K0 J1K1
00 00 0 0X 0X
00 01 1 0X 1X
 01 10 0 1X X1
01 01 1 0X X0
10 10 0 X0 0X
10 11 1 X0 1X
11 11 0 X0 X0
11 00 1 X1 X1

In the first row of Table above, we have a transition for flip-flop Q0 from 0 in the present state to
0 in the next state. In Table 10 we find that a transition of states from 0 to 0 requires that input J
= 0 and input K = X. So 0 and X are copied in the first row under J0 and K0 respectively. Since
the first row also shows a transition for the flip-flop Q1 from 0 in the present state to 0 in the next
state, 0 and X are copied in the first row under J1 and K1. This process is continued for each row
of the table and for each flip-flop, with the input conditions as specified.

The simplified Boolean functions for the combinational circuit can now be derived. The input
variables are Q0, Q1, and x; the output are the variables J0, K0, J1 and K1. The information from
the truth table is plotted on the Karnaugh maps shown in Figure below.

Karnaugh Maps

The flip-flop input functions are derived:

J0 = Q1 * x' K0 = Q1 * x
J1 = x K1 = Q0' * x' + Q0 * x = Q0 x
Note: the symbol  is exclusive-NOR.

The logic diagram is

Example 2: Design a sequential circuit whose state tables are specified in Table using D flip-
flops.

State table of a sequential circuit. Excitation table for

a D flip-flop.

Present State Next State Output Output Flip-flop

Q0 Q1 x=0 x=1 x=0 x=1 Transitions inputs
00 00 01 0 0 Q0 Q1 D
01 00 10 0 0 0 0 0
10 11 10 0 0 0 1 1
11 00 01 0 1 1 0 0
1 1 1
Next step is to derive the excitation table for the design
circuit, which is shown in Table. The output of the circuit is labeled Z.
Excitation table

Present State Next State Input Flip-flop Inputs Output

Q0 Q1 Q0 Q1 x D0 D1 Z
00 00 0 0 0 0
00 01 1 0 1 0
01 00 0 0 0 0
 01 10 1 1 0 0
10 11 0 1 1 0
10 10 1 1 0 0
11 00 0 0 0 0
11 01 1 0 1 1
Now plot the flip-flop inputs and output functions on the Karnaugh map to derive the Boolean
expressions, which is shown in Figure

Karnaugh maps

The simplified Boolean expressions are:

D0 = Q0 * Q1' + Q0' * Q1 * x
D1 = Q0' * Q1' * x + Q0 * Q1 * x + Q0 * Q1' * x'
Z = Q0 * Q1 * x

Finally, draw the logic diagram.

State Assignments
After the number of states in a state table has been reduced, the next step in realizing the
transition table (aka. state-assigned table) is to assign flip-flop states (i.e. binary values) to
correspond to the states in the state table.
The cost of the logic required to realize a sequential circuit is strongly dependent on the way this
state assignment is made.
Guidelines
Minimize no of bit changes for all state.
Guidelines based on next state input / output

Highest Priority: States which have the same next state for a given input should be
given adjacent assignments.
Medium Priority: States which are the next states of the same state should be given
adjacent assignments.
lowest Priority:. States which have the same output for a given input should be given
adjacent assignments.

State Table with assignment states

 Present Next State Output
State
X=0 X=1 X=0 X=1
00 01 10 0 0
01 11 10 1 0
10 10 11 0 1
11 00 11 0 0
State assignment Problem:
1. Design a sequential circuit for a state diagram shown .use stae assignment rules
for assigning states and compare the required combinational circuit with random
state assignment.

Present State Input Next State Output

A0 B0 C0 X A(t+1) B(t+1) C(t+1) Z
0 0 0 0 0 0 1 0
0 0 0 1 0 1 0 0
0 0 1 0 0 1 1 0
0 0 1 1 1 0 0 0
0 1 0 0 1 0 0 0
0 1 0 1 0 1 1 0
0 1 1 0 0 0 0 0
0 1 1 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 x X X X
1 1 1 1 X X X X

The random assignments require:

7 three input AND functions

1 two input AND functions

 4 two input OR functions

______________________

12 gates with 31 inputs

Now we will apply the state assignment rules and compare the results.

Rules 1 says that: e and d must be adjacent and

b and c must be adjacent

Rules 2 says that : e and d must be adjacent and

b and c must be adjacent

Applying Rule1 and Rule 2 to the state diagram we get the state
assignment as

Present State Input Next State Output

A0 B0 C0 X A(t+1) B(t+1) C(t+1) Z
0 0 0 0 0 0 1 0
0 0 0 1 0 1 1 0
0 0 1 0 1 0 1 0
0 0 1 1 1 1 1 0
0 1 0 0 X X X X
0 1 0 1 X X X X
0 1 1 0 1 1 1 0
0 1 1 1 1 0 1 0
1 0 0 0 X X X X
1 0 0 1 X X X X
1 0 1 0 0 0 0 0
1 0 1 1 0 0 0 1
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 0 0 0 1
1 1 1 1 0 0 0 0

The random assignments require:

4 three input AND functions

1 two input AND functions

2 two input OR functions

______________________
7 gates with 18 inputs