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Processing Techniques

The document discusses several key processing techniques used in advanced semiconductor manufacturing including dielectric deposition, etching, lithography, and metallization. It provides details on lithography methods, etching techniques like wet and dry etching, and examples of processes like dielectric deposition and photonic crystal fabrication. The techniques described are essential steps for fabricating devices like transistors, lasers, and photonic crystals.

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Sankha Deep
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0% found this document useful (0 votes)
43 views20 pages

Processing Techniques

The document discusses several key processing techniques used in advanced semiconductor manufacturing including dielectric deposition, etching, lithography, and metallization. It provides details on lithography methods, etching techniques like wet and dry etching, and examples of processes like dielectric deposition and photonic crystal fabrication. The techniques described are essential steps for fabricating devices like transistors, lasers, and photonic crystals.

Uploaded by

Sankha Deep
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced Semiconductor Materials

Processing technologies

Motivation
• To fabricate the chips we need several processing techniques
• An exposure to these techniques is necessary

Major Steps/Techniques
• Dielectric deposition
• Etching
• Lithography
• Metallisation
Literature:
1) Materials Science and Technology, vol. 16, Processing of Semiconductors, Ed. Cahn et al., volume ed.
K.A.Jackson, VCH, Weiheim, Germany, 1996.
2) R.Williams, Modern GaAs Processing Methods, Artech House, Inc, Norwood, MA, USA, 1990.
3) S.A.Campbell, The science and engineering of microelectronic fabrication, Oxford University Press,
New York, USA, 1996.
Sebastian Lourdudoss
Processing steps involved in a Field
Effect Transistor (FET) fabrication

Sebastian Lourdudoss
Processing steps involved in a Field
Effect Transistor (FET) fabrication

Figs. 1-8: Schematic flow ofa “self-aligned” process wherein the


gate metal layer is used to protect the FET channel from ion
implantation and processing damage:
1-2: channel and gate definition
3: self-aligning
4: device isolation
5-8: ohmic contacts, first and second level interconnections and
passivation protection

Sebastian Lourdudoss
Processing steps involved in a Buried
heterostructure laser

1) Epitaxial growth metal


2) Dielectric deposition (PECVD)
3) Resist coating Contact
p-InP
4) Patterns by lithography SI-InP
Active
5) Removal of unwanted dielectrics n-InP
6) Removal of unwanted resist
7) Mesa etching (with dielectric mask)
8) Regrowth of current blocking layer(s)
9) Removal of (dielectric) mask
10) Substrate lapping
11) Ohmic contacts on both sides

Sebastian Lourdudoss
Dielectric deposition

Dielectrics:
SiO2, SiNx and Polyimide

PECVD Spin coating

* Plasma enhanced chemical vapour


deposition
* Plasma = electrons, atoms,
molecules, ions, radicals From Cahn
* CVD temp. too high to preserve InP
and GaAs
* PECVD: T= 175-400 oC; P ~ 1x10-3
torr (0.13 Nm-2)
* Available gases: NH3, SiH4 ,He, N2,
N2O, O2, CF4, Ar
* SiN4 deposition rate 100-500 Å/min
and thickness 0.1-1.0 µm
Sebastian Lourdudoss
Etching techniques : Wet etching

+ Inexpensive
+ Quick
+ Low damage
- Difficult to control
+/- Orientation
dependent

From Cahn

From Cahn
From Cahn
Sebastian Lourdudoss
Etching techniques : Selective etching

InGaAsP QW
InGaAsP QW

InP InP

InP: HCl:H3PO4
InGaAsP: H2SO4:H2O2:H2O

Sebastian Lourdudoss
Etching techniques : Dry etching

+ Very good control


+/- Orientation independent
+ Faithful reproduction of
dielectrics pattern
- Expensive
- Time consuming
- Damage can occur
Damages: From Cahn
- atomic displacement Gases:
- creation of donors, CH4, C2H6, H2, CF4,CCl4, BCl3, CHCl3 etc.
acceptors and deep levels
Pressure:
- non-stoichiometry at the 10-3-10-5 torr
surface etc.
Temperature
Occasionally heated - heating occurs due to plasma

Sebastian Lourdudoss
Etching techniques : Three types of dry
etching

From: C-F. Carlström, Ph.D. Thesis,


KTH, 2001

Sebastian Lourdudoss
Etching techniques : Dry etching

p+-InP buffer
Applications
• Conventional laser mesas (1.5 µm wide/3-5 µm GaInAsP MQW
tall) GaInAsP

• Bragg gratings n-InP buffer

• VCSEL mesas 3-20 µm wide/5-15 µm tall


InP substrate
• Etched laser mirrors (several µm tall)
• Isolation of trenches (1 µm wide/1-3 µm deep)
CCDFB laser structure
• Q-wires and dots (ca 10-15 nm wide, > 100 nm
tall; ca 15 x15x15 nm3 )
• Photonic crystals

Sebastian Lourdudoss
Photonic Crystal work at KTH : some
representative examples (Courtesy: Anand, KTH)
Line defect photonic crystal waveguides, tapers
Nano-fabrication:High Simple PhC slabs:
aspect ratio etching Mirrors

Basic PhC properties- Low-loss W3 PhC waveguides (0.5dB/100µm) ,


State of the art PhC band-gap, transmission efficient taper sections (coupling 70%)
etching for InP: Ar/Cl2
CAIBE Collab. EPFL Collab. CNRS-LPN
Design and simulations: FMI Focusing by a flat PhC lens

Resonant Cavities InP-


Drop filter
InP/GaInAsP/InP membrane
Technology

Experimental evidence for


Q-factor: 3200 negative refraction @
Quality factor: 460 Contra-directional coupling
optical communication
Radiation loss at wavegelengths
Drop function demonstrated
Sebastian Lourdudoss
the mirrors
State-of-the-art photonic crystal etching in
InP/GaInAsP
Results from Ar/Cl2 CAIBE (2004)

etch depths
5 µm; d > 280 nm
4 µm; d ~ 200 nm

Courtesy: Anand, KTH

Sebastian Lourdudoss
Lithography
Types of Photolithography
1 Proximity printing
•Mask in close proximity to the wafer (not in contact
with it)
•Diffraction at pattern edges cause light divergence
non-uniform
poor resolution
poor reproducibility

2 Contact printing
•Widely spread
•Simple
•1:1 exposure
•Mask damage due to contact and frequent cleaning –
Also wafer damage
•Mask and wafer never perfectly flat
•Suitable for small areas

PHOTOLITHOGRAPHY 3 Projection printing


• What? •Mask and the wafer shifted synchronously while ligh
Transfer of patterns on wafers by optical sources passes through the mask
• How? •Wafer must be flat since the depth of focus is only a
•Resist (a light sensitive) film on the wafer µm’s.
•Pattern exposed on the resist
•Development 4 Optical stepper
•Exposed part dissolved (positive resist) •Dominant
•Unexposed part dissolved (negative resist) •Whole wafer can be covered by the patterns
•Pattern transfer on the wafer •1:1, 1:5, 1:10 exposure
•Very faithful reproduction
•Clean
From Williams
Sebastian Lourdudoss
Lithography

Certain terms:
•Airy pattern
Intensity of the focused image not a point but a
pattern described by e.g. a Bessel function
•F-number = Focal length (F) / Aperture (D)
•Numerical aperture (NA) = n sin (α)
n = Ref. Index of the image space (=air = 1) and α is
half the divergence angle
•F number = 1/(2NA) if n ~ 1 (for air) and α is small

•Radius of the first null, r = 1.22 λ (F/D)


(comes from beam analysis of the Bessel function)
= 1.22 λ (2 NA) where λ is the wavelength

•Resolution of the stepper = λ/ (2NA)

•Depth of the field, DOF = λ/ (2NA)2

Resist
•Positive (exposed part dissolves in the developer)
•Negative (unexposed part dissolves in the From Williams
developer)
•Adhesion on oxide or dielectric improved by an
adhesion promoter prior to resist application (not
improved on metal or GaAs) - e.g. HMDS (hexamethy
dioxysilazane)

Sebastian Lourdudoss
Cost and limitations of Photolithograpy

Courtesy: William Tong, HP, 2004


1 April 2011 Aalto University, Helsinki 21
E-beam lithography

E-BEAM LITHOGRAPHY

•E-beam instead of optical light


•Electron energy 10-25 keV
•Beam current <50 nA
•Resists sensitive to e-beam (less sensitive to normal light but slightly sensitive to deep ultra violet light)
PMMA (Polymethy methylacrylate) a +ve resist
•Developer: Methyl isobutyl ketone (MIBK)
Profile:
Long development: Undercut
Short development: Not enough time to dissolve all of the lower material
•Resolution < 0.25 µm
Spot size of diameters below 100 Å
•Patterns are “written” by e-beam throughout the wafer under computer control
Also called “direct slice writing”
No mask = no defects
•Easy pattern modifications
•Large depth of field
•Exposure (electron dose) determines the patterns
Low = does not reach the substrate
High = undercut
Moderate = vertical

From Williams

Sebastian Lourdudoss
E-beam lithography

•Electron scattering in the resist layer and back


scattering from the substrate
Real exposed area wider than the “beam area”
Proximity effect = Area between two lines or
pattern fields also get exposed
•High energy electrons - Interaction with the resist
results
bond breaking (positive resist) – Result: greater
solubility by the developer
crosslinking (negative resist) – Result: less
solubility
•Long writing time = less throughput
•SI substrates deflect the electron beams (can be
solved by depositing thin conductive layers)

From Williams

Sebastian Lourdudoss
UV-Nanoimprint Lithography
-Stamp
Resist application
- Resist

- Substrate (Wafer)

- UV light
UV-curing
- Carrier

- Vacuum chuck
Stamp and substrate
separation

Residual layer etching

UV-NIL process steps

Courtesy: Aleksandr Kravchenko Quartz mold


and Qin Wang, Acreo Sebastian Lourdudoss
State of the art
•State of the art: Acreo’s results:
 Resolution: 10 nm  Resolution: <50 nm
 Aspect ratio: 5  Aspect ratio: 4
 High throughput
 High throughput

SEM image of “star-like” array AFM image of the bio-sensor


Line width: 50 nm, Perfect structure filling,
Spacing: 20 nm Pattern height: 300 nm

Courtesy: Aleksandr Kravchenko


Sebastian Lourdudoss and Qin Wang, Acreo
Metallisation

Evaporation
Sputtering
E-beam evaporation
From Campbell

Sebastian Lourdudoss

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