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2 Ec2354 - Vlsi Design

This document contains a 20 question exam on VLSI design. Part A contains 10 short answer questions covering topics like MOS transistor operating regions, channel length modulation, logical effort, parasitic delay, time-dependent dielectric breakdown, clocked vs static circuits, sequencing overhead, fault models, always/initial statements, and Verilog for a 1-bit full adder. Part B contains longer questions about MOS transistor parameters/current calculation, fabrication processes, inverter delays, reliability, modeling, characterization with SPICE, static/ratioless circuits, dynamic circuits, BIST techniques, testers/fixtures/programs, and HDL modeling of a 4-bit synchronous counter.

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125 views2 pages

2 Ec2354 - Vlsi Design

This document contains a 20 question exam on VLSI design. Part A contains 10 short answer questions covering topics like MOS transistor operating regions, channel length modulation, logical effort, parasitic delay, time-dependent dielectric breakdown, clocked vs static circuits, sequencing overhead, fault models, always/initial statements, and Verilog for a 1-bit full adder. Part B contains longer questions about MOS transistor parameters/current calculation, fabrication processes, inverter delays, reliability, modeling, characterization with SPICE, static/ratioless circuits, dynamic circuits, BIST techniques, testers/fixtures/programs, and HDL modeling of a 4-bit synchronous counter.

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krishna_Scrbid
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com

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING


EC2354- VLSI DESIGN
PART-A(2*10= 20)
1. What are the different operating regions ofa MOS transistor?
2. What is channel length modulation?
3. Write the expressions for logical effort and parasitic delay of an n-input NOR gate.
4. What is TDDB ?
5. What are the merits and demerits of CVSL over static CMOS circuits.
6. Define sequencing overhead.
7. What is fault model?
8. Define ATPG.
9. Differentiate always and initial statements.
10. Write a verilog program for a 1 bit full adder.

PART-B(16 *5 = 80)
11. (a) An n-MOS transistor has the following parameters.Gate oxide thickness(tox
)=10 nm, relative

permittivity of oxide(εox) = 3.9, electron mobility= 520 cm2/V-sec, threshold voltage


=0.7 V, permittivity of free space = = 8.85 x 10-14 F/cm and (W/L)= 8. Calculate the
drain current when (Vgs = 2 V and Vds =1. 2 V ) and (Vgs = 2 V and Vds =2 V ) .
Also compute the gate oxide capacitance per unit area. W and L refer to the width and
Length of the channel respectively. (6)
(b) Explain the Secondary effects of MOS transistors in detail (10)
(or)
12. (a)Explain in detail the fabrication process of n-MOS transistor with neat
diagrams. (10)

(b) Discuss in detail with a neat layout, the design rules for a CMOS inverter. (6)
13. (a)Estimate the delay of an inverter driving ‘h’ identical inverters. Thereby,
estimate the delay of FO4 inverter. Assume inverter is constructed in a 180 nm
process with τ= 15 ps. (6)

(b)Explain Reliability terminology and reliability related issues in detail (10)


(or)
14. (a)Explain Different Device MOS Models with the necessary equations (8)

(b)How can Circuits be characterized using SPICE ? (8)


15. (a)Explain in detail about Static/Ratioless circuit family. (10)

(b) Explain DCVS circuit family (6)


(or)
16. (a)Explain in detail about Clock skew and Time borrowing concepts that cut into
the effective period available for computation. (8)

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(b)Write short notes on sequencing Dynamic circuits (8)


17. (a)With necessary circuit modules, explain BIST techniques. (10)

(b)Write short notes on Testers,Test fixutures and Test programs (6)


(or)
18. Explain Manufacturing Test principles in detail (16)
19. Design and develop a HDL project for a 4 bit synchronous counter using structural
modeling. Also, realize a test bench program to simulate the counter. (16)

(or)
20. (a) Explain conditional and looping statements in Verilog with suitable examples.
(8)

(b)Explain how gate delays can be modeled in Verilog. (8)

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