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Tutorial Sheet For Slow Learners.: CSE2001: Computer Architecture and Organization

This document provides tutorial questions about computer architecture and organization concepts including memory mapping, cache design, memory addressing, virtual memory, and floating point number representation. Specifically, it asks the reader to: 1) Design a memory system with RAM, ROM, and interface units given chip specifications. 2) Calculate bit fields for an 8-way set associative cache configuration. 3) Illustrate direct mapping, fully associative mapping, and 2-way set associative mapping for a main memory organization. 4) Determine page residency and hit ratio for a given virtual memory reference string. 5) Provide address mappings for given memory addresses under direct, fully associative and 2-way set associative cache

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26 views2 pages

Tutorial Sheet For Slow Learners.: CSE2001: Computer Architecture and Organization

This document provides tutorial questions about computer architecture and organization concepts including memory mapping, cache design, memory addressing, virtual memory, and floating point number representation. Specifically, it asks the reader to: 1) Design a memory system with RAM, ROM, and interface units given chip specifications. 2) Calculate bit fields for an 8-way set associative cache configuration. 3) Illustrate direct mapping, fully associative mapping, and 2-way set associative mapping for a main memory organization. 4) Determine page residency and hit ratio for a given virtual memory reference string. 5) Provide address mappings for given memory addresses under direct, fully associative and 2-way set associative cache

Uploaded by

Suman Sharma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CSE2001: Computer Architecture and Organization

Tutorial Sheet for Slow Learners.

1. A computer employs RAM chips of 512 x 16 and ROM chips of 1024bytes. Give the memory
map table and Design the memory system which needs 1K x 16 of RAM, 2K x 16 of ROM and
2 interface units with 512 registers each.

2. Design an 8-way set associative cache that has 16 blocks and 32 bytes per block. Main memory
is byte addressable. Assume 32-bit addressing and calculate the following:
a) How many bits are used for the byte field?
b) How many bits are used for the set field?
c) How many bits are used for the tag?

3. The main memory of a computer is organized as 64 blocks with a block size of eight words.
The cache has eight block frames.
a. Identify the tag field, the block number and the word number in case of direct mapping.
b. Show the fully associative mapping and the address bits that identify the tag field and
the word number
c. Show the two-way set associativity mapping and the address bits that identify the tag
field, the set number and the word number

4. The following sequence of virtual page numbers is encountered in the course of execution on a
computer with virtual memory:
342647132635123
Determine the four pages that are resident in main memory after each page reference. Calculate
the hit ratio considering LRU as the replacement policy adopted.

5. Consider a computer with the following characteristics: total of 1Mbyte of main memory; word
size of 1 byte; block size of 16 bytes; and cache size of 64 Kbytes.

a) For the main memory addresses of F0010, 01234, and CABBE, give the corresponding tag,
cache line address, and word offsets for a direct-mapped.

b) For the main memory addresses of F0010 and CABBE, give the corresponding tag and
offset values for a fully-associative.
c) For the main memory addresses of F0010 and CABBE, give the corresponding tag, cache
set, and offset values for a two-way set-associative.
6. Represent the following number in IEEE single precision format.
a.199.95
b.-77.7

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