Pixelplus-Pc1030n C11168

Data sheet
Issue No : PD-701-028
1/4 inch VGA class Analog/Digital Output

NTSC/PAL CMOS Image Sensor
l
tia
en
PC1030N
fid
R 1
Rev 1.0
0
Last update : 22 . Sep. 2009

on
C
6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,

Suwon-si, Gyeonggi-do, 443-766, Korea
Tel : 82-31-888-5300, FAX : 82-31-888-5398
py g ⓒ 2009,, Pixelplus
Copyright p Co.,Ltd
,
ALL RIGHTS RESERVED
PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Revision History
Version Date [D/M/Y] Notes Writer

0.0 20/05/2008 (Preliminary) Jong Beom Choi
0.1 04/06/2008 Customer datasheet is released SungJe Cheon
l
0.2 20/06/2008 DVDD voltage is modified SungJe Cheon
tia
Add DC Characteristics
Add AC Ch
Characteristics
t i ti
0.3 04/07/2008 Junhee Cho
Add Optical Performance
Add Power Sequence
0.4 09/07/2008 Modify effective pixel area. Fig.10 SungJe Cheon
0.5
06
0.6
22/07/2008
28/07/2008 Add VGA digital
en
Modify LED Control
di it l output
t t only
l mode
d
Bongju Lee
S
SungJe
J Ch
Cheon
0.7 23/09/2008 Removed “Preliminary” letters Jincheol Jeong
0.8 06/02/2009 Released Power Sequence Yoon Shik Kim
fid
0.9 27/03/2009 Change (Total pixel array Æ Effective pixel array) Heungseok Park
1.0 21/05/2009 Add Application note Jongwu Ryu
Change(SCLK Æ SSCLK, SDAT Æ SSDAT,

RCLK Æ RSCLK, RDAT Æ RSDAT)
1.1 22/09/2009 JiKyung Moon
Page 7,20,29,30
on
Modify Fig number. Page 13,14,15,18,19

C
Caution : This datasheet can be changed without prior notice !! If you want to get up-to-date version,
please send a mail to [email protected].
PD-701-028 Rev 0.7 2/96 CrystalImage & ImagingInnovation

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Table of Contents
▶ Features (3) 640x480 VGA Digital Output Only
- [ Fig. 1 ] PIN Description - [Fig.10] Timing diagram for Hsync, MCLK,
- [ Table 1 ] Typical Parameters PCLK and Data ( Default : YUV )
l
- [Fig.11] Timing diagram for Hsync, MCLK,
tia
PCLK and Data ( Bayer )
▶ Pin Descriptions
- [ Table 2 ] Pin Descriptions - [Fig.12] Timing diagram for Vsync and Hsync
▶ Signal Environment ▶ NTSC/PAL wire-strapping

en - [Fig 13] Example of wire-strapping
- [Table 3] wire-strapping
▶ Chip
p Architecture
- [Table 4] TV mode registers
- [ Fig. 2 ] Block Diagram
- [Table 5] Flicker mode register
- [Table 6] Mirror mode register
▶ Frame Structure and Windowing
fid
- [ Fig. 3 ] Default data structure of frame and
▶ Register initializing by I2C EEPROM
window
- [Fig 14] Connection with I2C EEPROM
- [Fig 15] Configuration of I2C EEPROM
▶ Data Formats
on
- [ Fig. 4 ] Bayer Color Filter Pattern

▶ 2-wire Serial Interface Description
- [ Fig. 5 ] 4:2:2 YUV data sequence.
▶ 2-wire Serial Interface Functional Description

▶ Data and Synchronization Timing
(1) ITU-R BT656

C
▶ Register Tables
- [ Fig. 6 ] Timing diagram of ITU-R BT601 and
ITU-R BT656.
▶ Register
g Tables ( Detailed )
- [ Fig. 7 ] Vertical Timing diagram of ITU-R of
ITU-R BT656.
(2) 320x240 (320x288) Digital Output ▶ Application Note
- [ Fig. 8 ] Timing diagram for Hsync, MCLK,

PCLK and Data
- [ Fig
Fig. 9 ] Timing diagram for Vsync and Hsync
Hsync.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Features
LEDCTL1
LEDCTL0
CADDR1
CADDR0
MOTION
RSDAT
HGND
DGND
HVDD
DVDD
▷ 648 x 488 Effective pixel array with
RGB bayer color filters and micro-lens
35 34 33 32 31 30 29 28 27 26
and optical black pixel. RSCLK 36 25 PCLK
SSCLK 37 24 X2
▷ Power supply : SSDAT 38 23 X1
l
D4 39 22 D3
AVDD : 2.8V, CVDD : 2.8V, DVDD : 1.8V,
tia
D5 40 21 D2
HVDD : 2.8 ~ 3.3V
HSYNC 1 PC1030N 20 D1
D6 2 19 D0
▷ Output formats : D7 3 18 TE
CVBS ( NTSC/PAL), VSYNC 4 17 REXT
RSTB 5 16 CGND
ITU-R. BT601/656( 60 fields/sec. interlaced @
27MHz) with CVBS, en 6 7 8 9 10 11 12 13 14 15
320x240(288) YCbCr422 (30(25)fps. @ 27MHz)
BY
DD
NC
NC
ND
DD
CP
CN
D1
D1
with CVBS
CVBS,
AVDD
AGND
STDB
C
AVD
N
N
AGN
CVD
C
640x480(VGA) YCbCr422 digital output only
(30fps. @ 27MHz).
▷ Image processing on chip :

fid
lens shading, gamma correction, [ Fig. 1 ] PIN Description (CLCC)
defect correction, low pass filter,
color interpolation, edge enhancement, Optical Format ¼ inch
color correction, brightness, contrast,
Pixel Size 5.55 um x 5.55 um
saturation, auto black level compensation,
auto white balance, auto exposure control Effective Pixel Array 648 x 488
on
and back light compensation.

Effective Image Area 3596.4um x 2708.4um
▷ Frame size
size, window size and position can Clock Frequency 27 MHz
be programmed through a 2-wire serial
Frame Rate 60(50) fields/sec @ 27MHz
interface bus.
Dark Signal 47.9 [mV/sec] @60’C
C
▷ VGA / QVGA / QQVGA / CIF / QCIF Scaling.

Sensitivity 3.16 [V/Lux.sec]
▷ 50Hz,
50Hz 60Hz flicker automatic cancellation
cancellation. 213 [[mW]] @ Dynamic
y
Power Consumption
19.2 [uW] @ Standby
▷ High Image Quality and High low light
performance. Operating Temp.
-40’C ~ 105’C
(Fully Functional Temp.)
Dynamic Range 63.5 [dB] @60’C
SNR 45.6 [dB] @60’C
[ Table 1 ] Typical Parameters

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ PIN Descriptions [ Table 2 ] Pin Descriptions
PIN Name I/O Functions / Descriptions

N
No. Type
T
1 HSYNC O Horizontal synchronization pulse. HSYNC is high ( or low ) for the horizontal window of
interest. It can be programmed to appear or not outside the vertical window of interest.
2 D6 O Bit 6 of parallel data output.
l
tia
4 VSYNC O Vertical sync
y : Indicates the start of a new frame.
5 RSTB I System reset must remain low for at least 8 master clocks after power is stabilized. When
the sensor is reset, all registers are set to their default values.
6 AVDD P Analog Power supply : 2.8V DC with 0.1uF capacitor to AGND.
7 N.C en
8 N.C
9 AGND P Analog Power ground

10 STDBY I Power standby mode. When STDBY=‘1’ there’s no current flow in any analog circuit
branch, neither any beat of digital clock. D<9:0> and PCLK, HSYNC, VSYNC pins can
be programmed to tri-state or all ‘1’ or all ‘0’. But it is possible to control internal registers
through I2C bus interface in STDBY mode. All registers retain their current values.
fid
11 CVDD P DAC Power supply : 2.8V DC with 0.1uF capacitor to AGND.
12 CP O Composite signal.
signal (Connect to 75ohm to AGND)
13 CN O Connect 37.5ohm to AGND
14 AVDD1 P Analog Power supply : 2.8V DC with 0.1uF capacitor to AGND.

on
15 AGND1 P Analog Power ground

16 CGND P DAC Power ground.
17 REXT I External Resistor. The resistor value can be changed by user tuning. (Connect to 30Kohm
to AGND)
18 TE I Chip Test Mode enable. (Connect to HGND)
C

output
23 X1 I Master clock input pad or Crystal input pad

24 X2 O Crystal output pad
25 PCLK O Pixel clock. Data can be latched by external devices at the rising or falling edge of PCLK.
The polarity and drivability can be controlled.
26 LEDCTRL0 O LED Control bit 0. LEDCTRL[1:0] provide 2bit combination of enable signal which can
turn-on LED device when low light condition.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
PIN Name I/O Functions / Descriptions

N
No. Type
T
27 MOTION O Motion detection. It lets user or processor know whether there are motion of something on
video. When the motion exists on the video, the output goes LOW to HIGH
28 CADDR0 I Chip address bit 0. Chip address can be changed If this CADDR[1:0] pins are tied to
l
HVDD or HGND.
Chip address bit 1. Chip address can be changed If this CADDR[1:0] pins are tied to
tia
29 CADDR1 I
HVDD or HGND.
30 DVDD P Digital Power supply : 1.8V DC with 0.1uF to DGND
31 DGND P Digital Power ground.
32 HGND P I/O Power ground.
33 HVDD P I/O Power supply: 2.8~3.3V DC with 0.1uF capacitor to HGND.

en
34 LEDCTRL1 O LED Control bit 1. LEDCTRL[1:0] provide 2bit combination of enable signal which can
u o LED device
turn-on dev ce when
w e low
ow light
g condition.
co d o .
35 RSDAT I/O 2-wire serial interface for external EEPROM.
36 RSCLK O 2-wire serial interface for external EEPROM
37 SSCLK I 2-wire serial interface slave clock input.
fid
38 SSDAT I/O 2-wire serial interface slave databus.

on
C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Signal Environment
PC1030N has 3
3.3V
3V tolerant Input pads
pads. Input signals must be higher than or equal to HVDD but cannot be
higher than 3.3V. PC1030N input pad has built in reverse current protection circuit, which makes it possible to
apply input voltage even if the HVDD is disconnected or floating. Voltage range for all output signals is 0V ~
HVDD.
l
tia
▶ Chip Architecture
PC1030N has 648 x 488 effective pixel array and column/row driver circuits to read out the pixel data
progressively. CDS circuit reduces noise signals generated from various sources mainly resulting from
process variations. Pixel output is compared with the reset level of its own and only the difference signal is
sampled, thus reducing fixed error signal level. Each of R, G, B pixel output can be multiplied by different gain
en
factors to balance the color of images in various light conditions. The analog signals are converted to digital
forms one line at a time and 1 line data are streamed out column byy column. The Bayer
y RGB data are passed
p
through a sequence of image signal processing block and pre-encoder and encoder blocks to produce YCbCr
4:2:2 output data or composite output. Image signal processing includes such operations as gamma correction,
defect correction, low pass filter, color interpolation, edge enhancement, color correction, contrast stretch,
fid
color saturation, white balance, exposure control and back light compensation. Internal functions and output
signal timing can be programmed simply by modifying the register files through 2-wire serial interface.
Analog Control signal

Digital Control signal Standby
RSTB
on w decoder
Timing MCLK
Effective Pixel array Control
648 × 488 Control registers
8
Row
Bayer RGB
8
Hsync
Vsync
Data
Data
pclk
…
PCLK
C
CDS<0:655>
DC control
HSYNC
e Signal
Proccessing
… VSYNC
ADC<0:655>
ADC 0:655 8
Bias / AD
al
Image
2-wire seria
interface
Registers
… SSDAT/RSDAT
Column decoder SSCLK/RSCLK

hsync
vsync
Cb
Cr
Y
Digital Control signal Encoder & composite

Pre Encoder
Pre-Encoder BT.656 DAC
[ Fig. 2 ] Block Diagram

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Frame Structure and Windowing
Origin
g ( 0, 0 ) of the frame is at the upper right
g corner. Size of the frame is determined by
y two registers
g :
framewidth( Reg.A-06h, A-07h ) and frameheight( Reg.A-08h, A-09h ). One frame consists of framewidth + 1
columns and frameheight + 1 rows. framewidth and frameheight can be programmed to be larger than total
array size. Default window array of 640 x 480 pixels is positioned at ( 110, 12 ). It is possible to define a
l
specific region of the frame as a window. Pixel scanning begins from ( 0, 0 ) and proceeds row by row
tia
downward, and for each line scan direction is from right to the left. Hsync signal indicates if the output is from a
pixel that belongs to the window or not.
not There are two counters to indicate the present coordinate of frame
scanning : Frame row counter and frame column counter. Counter values repeat the cycle of 0 to frameheight ,
and 0 to framewidth respectively. The counter values increase at the pace of pixel clock (PCLK), which does
not change as the frame size is altered. The pixel data rate is fixed and is independent of frame size(frame
rate).
en
PC1030N Frame Structure
(0,0)
8 (106,8)
fid
4 (110,12)
640
104 106
480 Effective pixel

4 4
on
(749,491)
(753,495)
4
29
(857,524) Dummy pixel

Effective window
C
[ Fig. 3 ] Default data structure of frame and window. ( Top view )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Digital Data Formats
Pixel array is covered by Bayer color filters as can be seen in

R G R G R G
the [ Fig. 4 ]. Since each pixel can have only one type of filter on it,
G B G B G B
only one color component can be produced by a pixel. PC1030N
R G R G R G
sensor provides this Bayer pattern RGB data through an 9-bit
l
G B G B G B channel. It takes one PCLK to pass one pixel RGB data to output
tia
R G R G R G bus. Generally one pixel of an image consists of R,G,B color
G B G B G B components. Since one pixel of bayer RGB is composed of one of
the 3 components, the other two components of a pixel must be
[ Fig. 4 ] Bayer Color filter pattern derived from neighbor pixels. For example, G component for a B
pixel is calculated as an average of its four nearest G neighbors, and
en
its R component as an average of its four nearest R neighbors.
This operation of inferring missing data from existing ones is called the color interpolation
interpolation. Color
interpolation produces an undesirable artifact in image. Sampling nature of color filter can leave an
interference pattern around an area with repetitive fine lines. PC1030K adopts a low pass filter to
prevent the interference patterns ( called Moire pattern) from degrading the image quality too much.
fid
After color interpolation, every pixel has all three color components. And then the pixel data pass
image processing block to improve the image quality.
It is possible to extract monochrome luminance data from RGB color components and the conver-
sion equation is : Y = 0.299R + 0.587G + 0.114B where R,G and B are gamma corrected color
on
components. And the color information is separated from luminance information according to following
equations.
Cb = -0.148R – 0.291G + 0.439, Cr = 0.439R -0.368G – 0.071B

C
Since human eyes are less sensitive to color variation than to luminance, color components can be
sub-sampled to reduce the amount of data to be transmitted, but preserving almost the same image
quality.
lit
PC1030K supports 4:2:2 YCbCr data format
where Cb and Cr components are horizontally
Cb1 Y1 Cr1 Y2 Cb3 Y3 Cr3 Y4 …
sub-sampled such that U and V for every other
pixel are omitted. PC1030K also support 4:2:2
[ Fig.
Fig 5 ] 4:2:2 YCbCr data sequence
sequence. YUV data format.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Data and Synchronization Timing
(1) ITU-R BT656 ( CCIR656 )
[ Fig. 6 ] shows ITU-R BT601 and ITU-R BT656 timing diagram. Sampling clocks of ITU-R BT601 and
ITU-R BT656 are 13.5MHz and 27MHz respectively. ITU-R BT656 format is generated from ITU-R BT601
format data by serialization and timing reference. Timing reference indicates Start or End of video. It
l
includes field, vsync and hsync information.
tia
PC1030N provides two kinds of active video sizes with BT656 format such as 720x480i and 720x576i
( ‘i’ stands for interlaced scan). The horizontal size is stretched from 640 to 720 pixels. 720x480i size BT656
supports for 525-line video, and 720x576i size BT656 for 625-line video. Horizontal timing of 720x480i and
720x576i size BT656 is shown in [Fig. 6] and vertical Timing diagram is shown in [Fig. 7]
ITU-R BT. 601

Y 718 719 720 721
en 857
(863)
0 1 2 3
Cb 359 360 0 1
Cr 359 360 0 1
fid
ITU-R BT. 656

Cb 428(431)
Cr 428(431)
Y 857(863)
Y 856(862)
Cb 359
Cb 360
Cr 359
Cr 360
Y 719
Y 721
Y 718
Y 720
Cb 0
Cb 1
Cr 0
Cr 1
Y1
Y3
Y0
Y2
on
Replaced by replaced by digital replaced by

timing reference blanking data timing reference
C Cb 359
9
Y 718
Cr 359
9
Y 719
9
Cb 0
Cb 1
Cr 0
Cr 1
Y1
Y3
Y0
Y2
End of Start of
active video active video
[ Fig. 6 ] Timing diagram of ITU-R BT601 and ITU-R BT656

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
525-LINE FORMAT 625-LINE FORMAT
EAV SAV EAV SAV

1 1 1
FF,00, FF,00,
BLANK BKANK FF,00, FF,00,
00,F1 00,EC BLANK BLANK
4 00,B6 00,AB
l
FF,00, FF,00, 23
BLANK BLANK
tia
00,B6 00,AB
23
FF, FF,
FIELD0 00, 00,
FF, FF, BLANK ACTIVE
ODD 00, 00,
FIELD0 00, 00,
BLANK ACTIVE 9D 80
ODD 00,
9D
00,
80
en FF,00, FF,00,
311
263 BLANK BLANK
FF,00, FF,00, 00,B6 00,AB
BLANK BLANK 313
00,B6 00,AB
266 FF,00, FF,00,
fid
BLANK BLANK
FF,00, FF,00, 00,F1 00,EC
BLANK BLANK
00,F1 00,EC
336
286
FF, FF, FF, FF,

00, 00, 00, 00,
FIELD1 BLANK ACTIVE
on
BLANK ACTIVE FIELD1 00, 00,

00, 00,
EVEN EVEN DA C7
DA C7
525 624
FF,00, FF,00, FF,00, FF,00,
BLANK BLANK BLANK BLANK
00,F1 00,EC 00,F1 00,EC
C
3
625 625
[ Fig. 7 ] Vertical Timing diagram of ITU-R BT656
• The numbers on the image indicate Line number.
• For 525-line format, active lines are 240 per a field. For 625-line format, active lines are 288 per a field.
• Vertical Timing is slightly different to Typical BT.656 for 525-line format. In active data regions above [Fig. 7],
they have only active pixel data not any fixed data (eg. black data).
• (design reference: Video Demystified 3rd edition, chapter 4)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(2) 320x240 (320x288) Digital Output Timing
[ Fig. 8 ] shows the Horizontal sub-sampled YUV422 data sequence of PC1030N. In this mode, the
frequencies of MCLK, PCLK and internal processing clock are equal. And Horizontal data are reduced
by one half of full size(640). The width of Hsync can be programmed by windowx1 / x2( Reg.A-0Ah, 0Bh,
l
0Eh, 0Fh ) and given by
tia
Hsync Width = (windowx2 - windowx1 + 1) / 2
It is not the same to horizontal scaling. This mode can provide digital data output concurrent to analog TV
output. In NTSC mode, it provides 320x240 size images with 30fps. And in PAL mode, it does 320x288
size images with 25 fps.
In this mode Hsync / PCLK polarity can also have any combinations possible. Data can be latched at the
en
rising or falling edge of PCLK. Hsync can be set to be active high or active low
Data value can be selected in Invalid or blanking region . ( Reg
Reg.B
B-13h
13h ~ 16h,
16h Reg
Reg. B-1B
B 1B ~ 1Eh )
Hsync Width = (window x2 – window x1 + 1) / 2

fid
Hsync
MCLK
PCLK
DATA AB U Y V Y U Y U Y V Y FF
on
[ Fig.
g 8 ] Timing
g diagram
g for Hsync,
y MCLK, PCLK and Data
[ Fig. 9 ] shows timing diagram of Vsync and Hsync in NTSC mode. Valid Hsync number is controlled
by scale_y, windowY1 and windowY2 registers. Vsync is controlled by Vsyncstart and vsyncstop
C
registers.
V
Vsync
Vsync width = ( vsyncstop – vsyncstart )
Hsync
1 line time Hsync Width =

= ( framewidth + 1 ) x pclk (
(window x2 – window x1 + 1 ) / 2
[ Fig. 9 ] Timing diagram for Vsync and Hsync

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(3) 640x480 VGA Digital Output Only Timing

[ Fig.
Fi 10 ] shows
h the
th VGA d
data
t sequence off PC1030N
PC1030N. IIn [ Fi
Fig. 10 ] Hsync
H / PCLK polarity
l it can h
have any
combinations possible. Data can be latched at the rising or falling edge of PCLK. Hsync can be set to be active
high or active low. The sequence default YUV data is [ U,Y, V, Y, …] for common even / odd rows.
The width of Hsync can be programmed by windowx1 / x2( Reg.A-0Ah, 0Bh, 0Eh, 0Fh )
l
and given by
tia
Hsync Width = (windowx2 - windowx1 + 1)
Data value can be selected in Invalid or blanking region . ( Reg.B-13h ~ 1Eh )
Hsync Width = ( window x2 – window x1 + 1 )
Hsync
MCLK
en
PCLK
fid
DATA AB U Y V Y U Y U Y V Y FF
[ Fig. 10 ] Timing diagram for Hsync, MCLK, PCLK and Data ( default )
The default sequence Bayer data is [RGRG…] for even rows and [GBGB…] for odd rows. The data
order can be changed by register (Reg.B-09h ).
on
[ Fig. 11 ] shows the bayer data sequence of PC1030N. PCLK frequency is (MCLK)/2 when output data
is bayer data.
Hsync Width = ( window x2 – window x1 + 1 )

C
Hsync
MCLK
PCLK
DATA(E) AB R G R G FF
DATA(O) AB G B G B FF
[ Fig. 11 ] Timing diagram for Hsync, MCLK’, PCLK and Data ( Bayer )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
In [ Fig. 12 ], Vsync polarity also can have any combinations possible and can be set to be active high
or active low.
low The width of Vsync can be programmed by vsyncstart / vsyncstop( Reg.A-12h
Reg A 12h ~ 15h ) and
given by
Vsync Width = ( vsyncstop – vsyncstart ).
l
tia
The width of Vreference can be programmed by register windowy1 / y2( Reg.A-0Ch, 0Dh, 10h, 11h )
and given by
Vreference width = ( windowy2 - windowy1 + 1).
Vreference
en
Vreference width = ( window y2 –window y1 + 1 )
Vsync(def.)
fid
Vsync width = ( vsyncstop – vsyncstart )
Hsync
on
1 line time Hsync Width =

= ( framewidth + 1 ) x pclk (window x2 – window x1 + 1)
[ Fig. 12 ] Timing diagram for Vsync and Hsync

C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ NTSC/PAL Wire-strapping
Wi
Wire_strapping
t i iis a ffunction
ti off chip
hi mode
d selection
l ti att Reset(HW
R t(HW resett or soft
ft reset).
t) Chi
Chip mode
d iis
automatically selected according to DO7~DO0 pads wired with pull-up or pull-down at RESET. [Fig.10]
shows one example of Wire-strapping configuration and [Table 3] shows chip mode selection by wire-
strapping.
l
HVDD
tia
100K
DO7 DO6 DO5 DO4
PC1030N
en
DO0 DO1 DO2 DO3
fid
[Fig.13] Example of wire-strapping ((M)NTSC, Manual-A Flicker Mode, No Mirror)
DO7 DO6 DO5 DO4 DO2 DO1 DO0

(M)NTSC - - - - L L L
on
NTSC-J - - - - L L H
(M)PAL - - - - L H L
TV_MODE
(Nc)PAL - - - - L H H
(N)PAL - - - - H L L
(B,D,G,H,I)PAL - - - - H L H
C
No Flicker cancel - - L L - - -
Manual-A - - L H - - -
FLICKER Manual-B - - H L - - -
Auto Flicker - - H H - - -
cancel
No Mirror L L
Mirror-V H L - - - - -
MIRROR
Mirror-H L H - - - - -
Mirror-VH H H - - - - -
[Table 3] wire-strapping

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
[
[Table 4]] shows TV_mode wire-strapping
pp g registers.
g The registers
g are changed
g byy DO2~DO0 under
RESET=‘0’.
"000b" "001b" "010b" "011b" "100b" "101b"
l
Register name Reg.Addr (M)NTSC NTSC-J (M)PAL (Nc)PAL (N)PAL (OTHER)PALs
chip_mode A-04h 00 00 00 01 01 01
tia
framewidth A-06/07h 0359 0359 0359 040D 040D 040D
frameheight A-08/09h 020C 020C 020C 0207 0207 0207
windowy2 A-10/11h 00F0 00F0 00F0 0120 0120 0120
scale_y B-21h 40 40 40 35 35 35
fd_a_step B-89/8Ah 03E8 en 03E8 03E8 03F0 03F0 03F0
fd_b_step B-8B/8Ch 0341 0341 0341 04B9 04B9 04B9
fd period a
fd_period_a B-91/92/93h 010600 010600 010600 010380 010380 010380
fd_period_b B-94/95/96h 013AAF 013AAF 013AAF 00D8C3 00D8C3 00D8C3
fd_period_c B-97/98h 0625 0625 0625 0514 0514 0514
fd_fheight_a B-99/9Ah 020C 020C 020C 0207 0207 0207
fid
fd_fheight_b B-9B/9Ch 020C 020C 020C 0207 0207 0207
enc_scfreq B-A5h 00 00 03 02 01 01
enc_blank
bl k B A8h
B-A8h F0 F0 F0 FC F0 FC
enc_pedestal B-A9h 2A 00 2A 00 2A 00
enc_burst B-Aah 70 70 75 75 75 75
enc_Ygain B-Abh 82 8D 82 89 82 89
on
enc_Ugain B-Ach 6F 78 6F 75 6F 75
enc_Vgain B-Adh 9C A9 9C A6 9C A6
enc_Crange_L B-B1h 48 62 48 5B 48 5B
enc_chroma_max_L B-B3h CD DF CD D7 CD D7
enc_chroma_min_L B-B5h 6D 35 6D 45 6D 45
C
expfrmH C-11h 020C 020C 020C 0207 0207 0207

ae_winy_L C-51h 07 07 07 08 08 08
ae_height C-54/55h 00E2 00E2 00E2 0110 0110 0110
ae_cwiny_L C-59h 4C 4C 4C 5B 5B 5B
ae_cheight_L C-5Dh 4B 4B 4B 5A 5A 5A
[Table 4] TV_mode registers

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
[
[Table 5]] and [[Table 6]] show Flicker mode and Mirror mode related registers
g and setting
g values at
RESET respectively.
l
"00b" "01b" "10b" "11b"
tia
Register name Normal(off) manual A manual B auto fd
flicker_control_2 80 88 84 C0
[Table 5] Flicker mode register
Register name
mirror
"00b"
No mirror
00
en "01b"
H mirror
01
"10b"
V mirror
02
"11b"
HV mirror
03
[Table 6] Mirror mode register

fid
on
C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Initializing by I2C-EEPROM
PC1030N supports
pp that user tuning
g registers
g can be set by
y I2C EEPROM initially.
y After reset time it
tries to access I2C EEPROM whether it has connected. If the connection has accomplished, it reads
data from I2C EEPROM and sets its registers. [Fig. 14] shows how to connect PC1030N and I2C
EEPROM.
l
HVDD
tia
HVDD
100K HVDD
DO7 DO6 DO5 DO4 RSCLK

Optional
PC1030N RSDAT I2C EEPROM
DO0 DO1 DO2 DO3

en
fid
[Fig. 14] Example of connection with EEPROM
User can make use of two methods below. Please refer to [Fig. 15] on next page about EEPROM configuration.
1. Using strap & EEPROM – NTSC / PAL selectable by strap

on
(1) Write proper values to NTSC_START, NTSC_LENGTH, PAL_STARTP, PAL_LENGTH,

COM_STARTP and COM_LENGTH on EEPROM
(2) Write register addresses and data that user want to set on EEPROM
(3) Adjust strap as user want.
C
* (M)NTSC, NTSC-J, (M)PAL : Setting is loaded by NTSC_START and NTSC_LENGTH.

(Nc)PAL, (N)PAL, (B,D,G,H,I)PAL : Setting is loaded by PAL_STARTP and PAL_LENGTH
* Caution : In case PAL-M,, NTSC setting
g method should be used
2. Using EEPROM without strap – NTSC or PAL only

(1) Write 0(zero) to NTSC_STARTP, NTSC_LENGTH, PAL_STARTP, PAL_LENGTH on EEPROM
(2) Write proper values to COM_STARTP and COM_LENGTH on EEPROM
(3) Write register addresses and data that user wants to set
set.
** Caution : It covers up to 2K bytes ROM (24xx16)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
ADDRESS CONTENT EXAMPLE(DEC)
0 NTSC_STARTP_H 0
1 NTSC_STARTP_L 12 ROM Address from 0 to 11 are reserved. These memory

spaces have information how the EEPROM are configured.
2 NTSC_LENGTH_H 0
1. NTSC_STARTP_H/L : indicates start address for NTSC setting
3 NTSC_LENGTH_L 10
l
2. NTSC_LENGTH: Total length for NTSC setting (Reg.Addrs & Data)
4 PAL_STARTP_H 0
tia
3. PAL_STARTP_H/L : indicates start address for PAL setting
5 PAL_STARTP_L 22
4 PAL
4. PAL_LENGTH
LENGTH : Total length for PAL setting
6 PAL_LENGTH_H 00 5. COM_STARTP_H/L : indicates start address for common
7 PAL_LENGTH_L 20 register setting to NTSC and PAL
6. COM_LENGTH: Total length for common setting
8 COM_STARTP_H 0
9 COM_STARTP_L 50 en
10 COM_LENGTH_H 0
11 COM LENGTH L
COM_LENGTH_L 30
12 REG_ADDRESS (NTSC_START)
13 REG_DATA
14 REG_ADDRESS
fid
User must configure the pair of register address and setting data
15 REG_DATA
… …
20 REG_ADDRESS …
21 REG_DATA (NTSC_END)
22 REG_ADDRESS (PAL_START)
on
23 REG_DATA
.. … …
41 REG DATA
REG_DATA (PAL END)
(PAL_END)
… … …
50 REG_ADDRESS (COMMON
START)
C
51 REG_DATA
… ... …
78 REG ADDRESS
REG_ADDRESS
79 REG_DATA (COMMON END)
… … …
[Fig. 15] Configuration of EEPROM & Example

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ 2-wire Serial Interface Description
The registers
g of PC1030N are written and read through
g the 2-wire Serial Interface. The PC1030N has 2-
wire Serial Interface slave. The PC1030N is controlled by the Register Access Clock (SSCLK), which is driven
by the 2-wire Serial Interface master. Data is transferred into and out of the PC1030N through the Register
Access Data (SSDAT) line. The SSCLK and SSDAT lines are pulled up to VDD by a 2kΩ off-chip resistor.
l
Either the slave or master device can pull the lines down. The 2-wire Serial Interface protocol determines
tia
which device is allowed to pull the two lines down at any given time.
Start bit
The start bit is defined as a HIGH to LOW transition of the data line while the clock line is HIGH.
Stop bit
The stop bit is defined as a LOW to HIGH transition of the data line while the clock line is HIGH.
en
Slave Address
The 8
8-bit
bit address of a 2-wire
2 wire Serial Interface device consists of 7-bit
7 bit of address and 1-bit
1 bit of direction.
direction A
‘0’ in the LSB of the address indicates write mode, and a ‘1’ indicates read-mode.
Data bit transfer
One data bit is transferred during each clock pulse. The SSCLK pulse is provided by the master. The
fid
data must be sGroup During the HIGH period of the SSCLK : it can only change when the SSCLK is LOW.
Data is transferred 8 bits at a time, followed by an acknowledge bit.
Acknowledge bit
The receiver generates the acknowledge clock pulse. The transmitter ( which is the master when writing,
or the slave when reading ) releases the data line, and receiver indicates an acknowledge bit by pulling the
data line low during the acknowledge clock pulse.
on
No-acknowledge bit
The no-acknowledge bit is generated when the data line is not pulled down by the receiver during the
acknowledge clock pulse. A no-acknowledge
no acknowledge bit is used to terminate a read sequence.
Sequence
A typical read or write sequence begins by the master sending a start bit. After start bit, the master
sends the slave device’s 8-bit address. The last bit of the address determines if the request will be a read or a
C
write, where a ‘0’ indicates a write and a ‘1’ indicates a read. The slave device acknowledges its address by
sending an acknowledge bit back to the master. If the request was a write, the master then transfers the 8-bit
register address to which a write should take place. The slave sends an acknowledge bit to indicate that the
register address has been received. The master then transfers the data 8 bits at a time, with the slave sending
an acknowledge bit after each 8 bits. The PC1030N uses 8 bit data for its internal registers, thus requiring one
8-bit transfer to write to one register. After 8 bits are transferred, the register address is automatically
incremented, so that the next 8 bits are written to the next register address. The master stops writing by
sending a start or stop bit. A typical read sequence is executed as follows. First the master sends the write-
mode slave address and 8-bit 8 bit register address just as in the write request. The master then sends a start bit
and the read-mode slave address. The master then clocks out the register data 8 bits at a time. The master
sends an acknowledge bit after each 8-bit transfer. The register address is auto-incremented after each 8 bit
is transferred. The data transfer is stopped when the master sends a no-acknowledge bit.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ 2-wire Serial Interface Functional Description
Single
g Write Mode operation
p
S SLAVE ADDRESS W A REGISTER ADR. A DATA A P
l
Multiple Write Mode (Register address is increased automatically)1 operation
tia
S SLAVE ADDRESS W A REGISTER ADR. A DATA A ···
DATA A ··· DATA A P
Single Read Mode operation en

S SLAVE ADDRESS W A REGISTER ADR. A ·························
··
Sr SLAVE ADDRESS R A DATA NA P
fid
Multiple Read Mode (Register address is increased automatically)1 operation
S SLAVE ADDRESS W A REGISTER ADR.

ADR A ·························
··
Sr SLAVE ADDRESS R A DATA A DATA A ···
on
························· DATA A DATA NA P

··
From master to slave From slave to master
S: Start condition. Sr : Repeated Start ( Start without preceding stop. )

C
SLAVE ADDRESS: It can be extended 60h to 67h via CADDR0 and CADDR1 pads
CADDR[1..0] “00” “01“ “10” “11”

write address 60h 62h 64h 66h(default)
read address 61h 63h 65h 67h(default)
R/W: Read/Write selection. High = read / LOW = write.

A: Acknowledge bit. NA : No Acknowledge.
DATA: 8-bit data
P: Stop
p condition
Note 1: Continuous writing or reading without any interrupt increases the register address automatically. If the
address is increased above valid register address range, further writing does not affect the chip operation in
write mode. Data from invalid registers are undefined in read mode.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group A )
l
tia
en
fid
on
C
( Group A : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group B )
l
tia
en
fid
on
C
( Group B : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group B )
l
tia
en
fid
on
C
( Group B : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group C )
l
tia
en
fid
on
C
( Group C : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group C )
l
tia
en
fid
on
C
( Group C : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Group D )
l
tia
en
fid
on
C
( Group D : continue )

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Detailed ) : Group A
Register
g names are written in slanted characters. To differentiate between decimal, binary,
y and hexa
numbers, ( d, b, and h ) are appended. The sensor should be reset by RSTB pin set low, after power is
up, for at least 16 master clock periods. And then all read-write registers are initialized by internal ROM
for about 3 ms. So we recommend you to write data to registers after initialization.
l
tia
(0-3) DeviceID, RevNumber, Register Selector
GROUP A
# default value
register name type stage Description
dec hex dec hex bin
2
00
01
02
DeviceID_H
DeviceID_L
RevNumber
16
48
1
10
30
01
en 00010000
00110000
00000001
RO
RO
RO
0
0
device ID
revision number
3 03 bank 0 00 xxxxxx00 RW 5 register group selector
Default : 00h( Device_ID_H ) = 10h,

fid
01h( Device_ID_L ) = 30h,
02h( Rev_Number ) = 00h,
03h( Register Selector )= 00h.
Description :
Indicates device ID, reversion number, Register Select.
on
Common registers of Group A(00h) / B(01h) / C(02h) / D(03h).
g
Register type
yp
RO : Available Read Only
RW : Available Read and Write
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(4) Chip mode < Group A >

# default value
dec hex dec hex bin
4 4 chip mode
chip_mode U U 000000UU RW 7 chip mode selection
Default : 04h = Variable according to wire-strapping

Description :
l
tia
register name : chip_mode
register
g # bit# name default U default(h)
( ) 0U default(b)
( ) 000000UU
7 x 0
6 x 0
5 x 0
04(d)
04(h)
4
2
x
x
0
0
en
1 U Chip mode selection
"00" - NTSC, (M)PAL
chip_mode "01"- PAL
fid
0 U Else – VGA digital output only
Chip_mode(1 : 0) : chip mode selection

The default value of this register is changed by wire-strapping under RESET=‘0’(HW/SW reset).
After reset, the register can be set with other values through SSCLK and SSDAT.
on
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(5) Mirror < Group A >

# default value
dec hex dec hex bin
5 5 mirror U U 000000UU RW 6 mirror mode selection
Default : 05h = Variable according to wire-strapping

Description :
l
tia
register name : chip_mode
register # bit# name default U default(h) 0U default(b) 000000UU
7 x 0
6 x 0
5 x 0 en
4 x 0
05(d)
05(h) 3 x 0
2 x 0
1 vm U vertical mirror ON/OFF

fid
0 hm U horizontal mirror ON/OFF
Mirror (1 : 0) : Vertical/Horizontal mirror

The default value of this register is changed by wire-strapping under RESET=‘0’(HW/SW reset).
After reset, the register can be set with other values through SSCLK and SSDAT.
on
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(6-7) FrameWidth < Group A >

# default value
dec hex dec hex bin
6 6 framewidth_h
framewidth h U U UUUUUUUU RW 5 framewidth (H)
7 7 framewidth_l U U UUUUUUUU RW 5 framewidth (L)
Default : Variable according to wire-strapping

Description :
l
FrameWidth is the number of columns to be counted during one line time. Column counter
tia
value is incremented 1 by 1 until it reaches FrameWidth, then it is reset to 0.
Usage:
NTSC/NTSC-J/(M) PAL : 0359h
(B, D, G, H, I, N, Nc) PAL : 040Dh en
VGA digital output only : 0359h
fid
(8-9) FrameHeight
# default value
dec hex dec hex bin
8 8 frameheight_h 2 02 00000010 RW 5 frameheight (H)
9 9 frameheight_l U U UUUUUUUU RW 5 frameheight (L)
on
Default : 08h = 02h, 09h = Variable according to wire-strapping

Description :
FrameHeight is the number of rows to be counted during one frame time. Row counter
value is incremented 1 by 1 until it reaches FrameHeight, then it is reset to 0.
C
Usage:
NTSC/NTSC-J/(M) PAL : 020Ch
(B, D, G, H, I, N, Nc) PAL : 0207h
VGA digital output only : 020Ch
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(10-17) WindowX / Y < Group A >

# default value
dec hex dec hex bin
10 0A windowx1_h
windowx1 h 0 00 00000000 RW 6 window X1 (H)
11 0B windowx1_l 3 03 00000011 RW 6 window X1 (L)
12 0C windowy1_h 0 00 00000000 RW 6 window Y1 (H)
13 0D windowy1_l 1 01 00000001 RW 6 window Y1 (L)
14 0E windowx2_h 2 02 00000010 RW 6 window X2 (H)
15 0F windowx2_l 130 82 10000010 RW 6 window X2 (L)
l
16 10 windowy2_h U UU 00000UUU RW 7 window Y2 (H)
17 11 windowy2_l U UU UUUUUUUU RW 7 window Y2 (L)
tia
Default : 0Ah = 00h
00h, 0Bh = 03h
03h, 0Ch = 00h
00h, 0Dh = 01h
01h, 0Eh = 02h
02h, 0Fh = 82h
82h,
10h / 11h = Variable according to wire-strapping
Description :
Window can be defined by 4 parameters : WindowX1, WindowY1, WindowX2, and WindowY2.
en
Serial image data stream out pixel by pixel. Window specifies the area of pixels that we are interested
in. Hsync signal indicates if the image data output is from a pixel that lies within the window area or
not. Output data stream does not stop for pixels lying outside the window : just the Hsync signal is de-
asserted.
The actual window position in the frame is given as
fid
upper right corner = ( Window X1 + 1, Window Y1 )
lower left corner = ( Window X2, Window Y2 - 1 )
All the coordinates are with respect to the maximum window origin (0
(0, 0) of [Fig
[Fig. 3]
3]. Window
position and size are with respect to the full sampling mode. It is not necessary to change the window
parameters when sampling mode is switched between one and another.
on
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(18-21) VsyncStartrow / VsyncStoprow < Group A >

# default value
dec hex dec hex bin
18 12 vsyncstartrow_h
t t h 0 00 00000000 RW 5 Output
O t t Vsync
V Row
R StStartt (H)
19 13 vsyncstartrow_l 14 0E 00001110 RW 5 Output Vsync Row Start (L)
20 14 vsyncstoprow_h 1 01 00000001 RW 5 Output Vsync Row Stop (H)
21 15 vsyncstoprow_l 238 EE 11101110 RW 5 Output Vsync Row Stop (L)
Default : 12h = 00h, 13h = 0Eh, 14h = 01h, 15h = EEh
l
Description :
tia
VsyncStartRow:
y Output
p Vsync
y Row Start points
p
VsyncStopRow: Output Vsync Row Stop points
en
fid
(22-23) VsyncColumn
# default value
dec hex dec hex bin
22 16 vsynccolumn_h 0 00 00000000 RW 5 Output Vsync Column Start (H)
23 17 vsynccolumn_l 31 1F 00010000 RW 5 Output Vsync Column Start (L)
on
Default : 16h = 00h, 17h = 1Fh

Description :
VsyncColumn:
y Output
p Vsync
y Column start p
points
C
Vsync
Rcount
VsyncStart VsyncStart_Column VsyncStop
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(25) Digital Gain < Group A >

# default value
dec hex dec hex bin
25 19 di it l i
digitalgain 64 40 01000000 RW 6 Di it l G
Digital Gain
i
Default : 19h = 40h

Description :
l
Digital Gain
tia
(26-27) Globalgain
dec
26
#
hex
1A
register name
globalgain
dec
0
default value
hex
00
bin
00000000 RW
en
type stage
6
Description
Globalgain( Globalgain for odd frame at dual exposure mode)
Default : 1Ah = 00h

fid
Description :
GlobalGain has effect on all of R, G, and B pixel outputs. Raw R, G, B data are amplified by a
common factor of GlobalGain.
GlobalGain The relation between GlobalGain and amplification factor is shown in
the picture below.
Gain ( x )
on
32
16 Maximum value of GlobalGain is
8
4 1001111 Gain factors for GlobalGain
1001111.
2 larger than or equal to 1010000 are
1
not defined.
C
GlobalGain
001111
000000
000000
0100000
0110000
010000
10
10
00
00
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(33-38) Integration Time < Group A >

# default value
dec hex dec hex bin
33 21 inttime H
inttime_H 0 00 00000000 RW 6 Integration Time (H)
34 22 inttime_M 128 80 10000000 RW 6 Integration Time (M)
35 23 inttime_L 0 00 00000000 RW 6 Integration Time (L)
Default : 21h = 00h, 22h = 80h, 23h = 00h
l
Description :
tia
There are 3 bytes of registers to control the photo-charge accumulation interval for each pixel.
4Ch and 4Dh registers indicate how many line times the integration will continue until they are all reset
reset.
4Eh register further sub-divide one line time into 256 smaller intervals. Total integration time is the
sum of the integral multiple and fractional parts of one line time.
As the row counter value is incremented from 0 to FrameHeight, each line relevant to the row
en
count is selected and all pixel data of that line is read out all at once. The read- out operation involves
pixel reset pulses, so all pixels that are selected and read out are reset to initial states.
To control exposure time, there runs another counter to select and reset a line other than the one
that is selected to be read out. The space between the two lines is equal to the number of integration
lines. There are two possible situations concerning the position of selected line and reset line. The 1st
fid
case is where the pre-reset counter runs ahead of read-out counter. And the other case Is just the
reverse of the 1st one. The number of integration lines is different for the two cases as is shown in the
left figures
figures. Since the basic unit of integration time for PC1030N is 1/ 256 line time
time, it is easy to
implement Auto Exposure algorithms without worrying about strong light environment where the
image may change abruptly in brightness or it may even blink.
on
F
FrameWidth
Width
FrameHeight
Integration
selected line pre-reset line
C
Integration
pre-reset line selected line
Integration
Case 1. Reset line preceding select line Case 2. Select line preceding reset line
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(39-43) White Balance R/G/B gain < Group A >

# default value
dec hex dec hex bin
39 27 wb_rgain
wb rgain 64 40 01000000 RW 6 Red gain for white balance
40 28 wb_ggain 64 40 01000000 RW 6 Green gain for white balance
41 29 wb_bgain 64 40 01000000 RW 6 Blue gain for white balance
Default : 27h = 40h, 28h = 40h, 29h = 40h
l
Description :
tia
White Balance Red gain :
RedGain is the multiplication factor for red pixel output. Total gain factor for red pixels is
( gain from GlobalGain ) * ( gain from RedGain ).
White Balance Green gain :
G1/G2 pixels are those green pixels whose nearest neighbors are red pixels or blue pixels.
White Balance Blue gain :
BlueGain is similar to RedGain.
en
fid
Gain ( x )
on
4 R / G / B gain can be used for white balance

3 control. Bit7 of R/G/B Gain is weighted by 2, bit6
2 by 1 and the other consecutive bits are weighted
1 by 1/2, 1/4, 1/8, … respectively. That is, R/G/B
R/G/B Gain gain is a binary number with decimal point
C 00000000
01000000
10000000
11000000
11111111
between bit6 and bit5.

0
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(49) Analog control 06 < Group A >

# default value
dec hex dec hex bin
49 31 analog control 06
analog_control_06 89 59 01011001 RW 5 analog control register 06
Default : 31h = 59h

Description :
l
tia
register name : analog_control_06
register # bit# name default 89 default(h) 59 default(b) 01011001
7 0
Reserved
6 1
5 0
en
pad_drivability Data & VSYNC PAD pad drivability control register
49(d) 4 1
31(h) 3 1
2 Reserved 0
1 0
fid
0 Reserved 1
(50) Analog control 07

# default value
dec hex dec hex bin
on
50 32 analog_control_07 0 00 00000000 RW 5 analog control register 07
Default : 32h = 00h

D
Description
i ti :

C
7 motion_pad_en 0 motion output pad enable
6 Reserved 0
5 dac_pd 0 DAC power down
50(d) 4 0
Reserved
32(h) 3 0
2 Reserved 0
1 R
Reserved
d 0
0 Reserved 0
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(51) Analog control 08 < Group A >

# default value
dec hex dec hex bin
51 33 analog_control_08
l t l 08 5 5 00000101 RW 5 analog
l control
t l register
i t 08
Default : 33h = 05h

Description :
l
tia
7 ledctl_en 0 LEDCTL pad enable
6 0
ledctl_drv LEDCTL pad drivability
5 0
51(d)
33(h)
4
2
Reserved
hsync drv
hsync_drv
0
1
en hsync pad drivability
1 0
pclk_drv pclk pad drivability
0 1
fid
(52) A
Analog
l control
t l 09
# default value
dec hex dec hex bin
52 34 analog_control_09 0 0 00000000 RW 5 analog control register 09
on
Default : 34h = 00h

Description :

C
7 0 output pixel clock delay

000 : no delay 001b : 2.5ns
6 pclk_delay 0 010b : 5ns 011b : 7.5ns
100b : 10ns 101b : 12.5ns
5 0 110b : 15
15ns 111b : 17
17.5ns
5
52(d) 4 Reserved 0
34(h)
3 Reserved 0
2 Reserved 0
1 Reserved 0
0 Reserved 0
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(53) PixelBias < Group A >

# default value
dec hex dec hex bin
53 35 pixelbias 1 01 00000001 RW 5 pixel bias
Default : 20h = 01h

Description :
l
Pixel array has a source follower circuit for each column to buffer the photo-diode signal voltage.
tia
The source follower bias current is determined as an integral multiple of 1uA.
Ipixel = PixelBias * 1uA
54
(54) CompBias
dec
d
#
hex
h
36
register name
compbias
dec
d
15
default value
h
hex
0F
bi
bin
00001111 RW
en
type stage
5
Description
compbias
Default : 36h = 0Fh

Description :
fid
Comparator amp bias
on
(55) Soft reset

C
# default value
dec hex dec hex bin
55 37 soft_reset 0 00 xxxxxxx0 RW 5 software reset
Default : 37h = 00h

Description :
soft_reset(0) : Software reset bit
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(57) Bayer Control 02 < Group A >

# default value
dec hex dec hex bin
57 39 bayer control 02
bayer_control_02 240 F0 11110000 RW 6 bayer control register 02
Default : 39h = F0h

Description :
l
tia
register name : bayer_control_02
register # bit# name default 240 default(h) F0 default(b) 11110000
Pixel Clock Divide

7 1 000b : master clock x 1/2
001b : master clock x 1/3
en 010b : master clock x 1/4
6 clkdiv(2:0) 1 011b : master clock x 1/6
5 1 111b : master clock x 1 ( default ) – for NTSC / PAL
57(d)
39(h)
4 Reserved 1
3 Reserved 0
fid
2 Reserved 0
1 Reserved 0
0 Reserved 0
on
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(62) Bayer Control 07 < Group A >

# default value
dec hex dec hex bin
62 3E bayer control 07
bayer_control_07 0 00 00000000 RW 5 bayer control register 07
Default : 3Eh = 00h

Description :
l
tia
register name : bayer_control_07
register # bit# Name default 0 default(h) 00 default(b) 00000000
7 Reserved 0
6 Reserved 0
en Variable Frame rate mode

5 frmvar_en 0 ‘0’ : disable
‘1’ : enable (for VGA digital output only)
62(d)
3E(h) 4 0
3 0
2 Reserved 0
fid
1 0
0 0
on
C
< Group A >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(235 - 254) Parking_guide < Group A >

# default value
dec hex dec hex bin
235 EB pg_x0_h
pg x0 h 0 00 00000000 RW 5
Horizontal Center position
236 EC pg_x0_l 0 00 00000000 RW 5
237 ED pg_x1_h 0 00 00000000 RW 5
Honrizontal Distance from Horizontal Center
238 EE pg_x1_l 0 00 00000000 RW 5
239 EF pg_y1_h 0 00 00000000 RW 5
Vertical position of Horizontal Line 1
240 F0 pg_y1_l 0 00 00000000 RW 5
l
241 F1 pg_y2_h 0 00 00000000 RW 5
242 F2 pg_y2_l 0 00 00000000 RW 5
tia
243 F3 pg_y3_h 0 00 00000000 RW 5
244 F4 pg_y3_l 0 00 00000000 RW 5
245 F5 pg_y4_h
pg_y _ 0 00 00000000 RW 5
V ti l position
Vertical iti off Horizontal
H i t l Line
Li 4
246 F6 pg_y4_l 0 00 00000000 RW 5
247 F7 pg_dx1 0 00 00000000 RW 5 Slope of Horizontal Line 1 to Line2
250 FA pg_dx4 0 00 00000000 RW 5 Slope of Horizontal Line 4 to End line
251 FB pg_bottom_h 0 00 00000000 RW 5
Bottom Limit of Park ing guide
252 FC pg_bottom_l 0 00 00000000 RW 5
253
254
FD
FE
pg_T
pg_bg_clamp
0
200
00
C8
00000000
11001000
RW
RW
en 5
5
Default : EBh = 00h, EAh = 00h, EBh = 00h, ECh = 00h, EDh = 00h, ECh = 00h, EEh = 00h,
Park ing guide Line Thick
Transparency of park ing guide line
EFh = 00h, F0h = 00h, F1h = 00h, F2h = 00h, F3h = 00h, F4h = 00h, F5h = 00h, F6h = 00h,
F7h = 00h, F8h = 00h, F9h = 00h, FAh = 00h, FBh = 00h, FCh = 00h, FDh = 00h, FEh = C8h
fid
Description :
pg x0 : Horizontal Center p
pg_ position
pg_x1 : Horizontal Distance form Horizontal Center
pg_y1[12:0] : Vertical Position of Horizontal Line 1
on

pg_y1[15:13]
1[15 13] : C
Color
l off Li
Line 1
1, Li
Line 5 and
d Li
Line 6 ((show
h nextt page))
( [15] – Red, [14] – Green, [13] – Blue )
pg_y2[15:13] : Color of Line 2 ( [15] – Red, [14] – Green, [13] – Blue )
C

pg_dx1 : slope of Horizontal Line 1 to Line 2
pg_dx4 : slope of Horizontal Line 4 to End Line
pg_bottom : bottom limit of Parking guide
pg_T : Line Thickness
pg bg clamp : Transparency of parking guide line
pg_bg_clamp

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
< Group A >
pg_x1[15:0]
l
pg_dx1[7:0]
tia
pg_dx2[7:0]
pg_dx3[7:0]
pg_dx4[7:0]
Line 1
pg_y1[12:0]
Line 5
Line 2
en pg y2[12:0]
pg_y [ :0]
Line 3
pg_y3[12:0]
fid
Line 4
pg_y4[12:0]
pg_T[7:0]
Line 6
pg_x0[15:0]
on
[Fig] Parking guide Diagram

C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Detailed ) : Group B < Group B >
(260) ISP Function Control 0

# default value
dec hex dec hex bin
260 4 isp_func_0 255 FF 11111111 RW 6 ISP control register 00
l
Default : 04h = FFh
tia
Description :
register name : isp_function_control_00
register # bit# name default 255 default(h) FF default(b) 11111111
6
ccr_en
Reserved
1
1
en Color Correction
‘0’ : Color correction disable
‘1’
1 : Color correction enable (default)
Low Pass Filter

5 lpf_en 1 ‘0’ : Disable.
fid
‘1’ : Enable. (default)
260(d)
04(h) 4 Reserved 1
3 Reserved 1
Edge Enhancement
2 edge_en 1 ‘0’ : Disable
‘1’ : Enable (default)
on
1 Reserved 1
0 Reserved 1
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(262) ISP Function Control 2 < Group B >

# default value
dec hex dec hex bin
262 6 i
isp_func_2
f 2 96 60 01100000 RW 6 ISP control
t l register
i t 02
Default : 06h = 60h

Description :
l
tia
Sephia
7 sephia_en 0 ‘0’ : Disable (default)
‘1’ : Enable
4
Reserved
Reserved
parking_guide_en
en
1
0
Parking guide enable
‘0’ : Disable (default)
262(d) ‘1’ : Enable
06(h) Reverse ( reg_ae_ysel='3', Y601 selection )
fid
3 reverse 0 ‘0’ : Disable (default)
‘1’ : Enable
0
Reserved
1 0
Lens Shading Enable

0 lens_en 0 ‘0’ : Disable
on
‘1’ : Enable (default)

C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(263) ISP Function Control 3 < Group B >

# default value
dec hex dec hex bin
263 7 i
isp_func_3
f 3 203 CB 11001011 RW 6 ISP control
t l register
i t 03
Default : 07h = CBh

Description :
l
tia
register # bit# name default 216 default(h) D8 default(b) 11011000
7 1
Reserved
6 1
263(d)
5
4
Reserved
0
0
en
07(h)
Gamma Correction
3 gm_en 1 ‘0’ : Disable
‘1’ : Enable (defualt)
fid
2 Reserved 0
1 Reserved 1
0 Reserved 1
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(264) I2C control 1 < Group B >

# default value
dec hex dec hex bin
264 8 i2
i2c_control_1
t l 1 80 50 01010000 RW 5 I2C control
t l register
i t 01
Default : 08h = 50h

Description :
l
tia
register name : i2c_control_1
7 0
6 1
3
Reserved
Reserved
0
0
en
264(d)
08(h) Clock kill control register
2 clkoff 0 ‘0’ : Clock kill disable (default)
fid
‘1’ : Clock kill enable
Register standby mode

1 stdby 0 ‘0’ : Off (default)
‘1’ : On
Digital data output enable

0 dout_en 0 ‘0’ : Disable (default)
‘1’ : Enable
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(265) Format < Group B >

# default value
dec hex dec hex bin
265 9 f
format
t 0 00 00000000 RW 2 O t t Format
Output F t control
t l register
i t
Default : 09h = 00h

Description :
l
tia
register name : format_control
7 0
0 : CB Y CR Y
6 0
1 : CR Y CB Y
265(d)
( )
09(h)
5
3
format control
format_control
0
0
en 2 : Y CB Y CR
3 : Y CR Y CB
4 : RGRG…GBGB, Raw Bayer
5 : GBGB
GBGB...RGRG,
RGRG Raw Bayer
6 : GRGR...BGBG, Raw Bayer
7 : BGBG...GRGR, Raw Bayer
2 0 12 : mono Sensor
13 : YYYY
1 0
fid
0 0
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
< Group B >
(266) Format2
# default value
dec hex dec hex bin
266 A format2 0 00 00000000 RW 6 Output Format2 control register
Default : 0Ah = 00h

Description :
l
tia
register name : format2
7 1 "01" - CCIR656 interlaced, "10" – 320x240 (320x288),

dout_select
6 0 Else – VGA digital output only
266(d)
0A(h)
5
3
Reserved
Reserved
dout_field_mode
en 0
0 select 320x240(288) digital output (even or odd : default=odd)
2 Reserved 0
1 Reserved 0
fid
0 Reserved 0
dout_select :
“01b” – ITU-R BT656( CCIR656) interlaced format output.
on
“10b” – i) Horizontal sub-sampled YCbCr422 and one field output among odd and even fields
concurrent with analog composite(27MHz master clock) at 4d ≤ Format register ≤
else – VGA digital output only
C
dout_field_mode (for 320x240(288)) :

‘0’ – odd field selected
‘1’ – even field selected
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(267) Sync control 0 < Group B >

# default value
dec hex dec hex bin
267 0B sync_control_0
t l 0 0 00 00000000 RW 6 S h i ti control
Synchronization t l register
i t 00
Default : 0Bh = 00h

Description :
l
tia
register name : sync_control_00
7 Reserved 0
Vsync Drop ( VD ), sync_drop[1]

6 0 ‘0’ : disable. ( default )
267(d)
5
sync_drop[1:0]
en
0
‘1’ : enable.
Hsync Drop ( HD ), sync_drop[0]
‘0’ : disable. ( default )
‘1’ : enable.
0B(h)
4 0
3 0
fid
2 sync_pclkrate 0 pclk rate control
1 0
0 0
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(268) Sync control 1 < Group B >

# default value
dec hex dec hex bin
268 0C sync_control_1
t l 1 2 02 00000010 RW 6 S h i ti control
Synchronization t l register
i t 01
Default : 0Ch = 02h

Description :
l
tia
register name : sync_control_01
Output Pad set to Hi Impedance ( HiZ )

7 hiz 0 ‘0’ : disable. ( default )
‘1’ : enable.
6 sync_vsyncPolarity
en 0
Vsync Polarity Change
‘0’ : disable. ( default )
‘1’ : enable.
Active High of Hsync All Lines

5 sync_hsyncAllLines 0 ‘0’ : Disable. ( default )
‘1’ : Enable.
Hsync Polarity Change

fid
268(d) 4 sync_hsyncPolarity 0 ‘0’ : Disable. ( default )
0C(h) ‘1’ : Enable.
PCLK Window
3 sync_pclkwindow 0 ‘0’ : Disable. ( default )
‘1’ : Enable.
PCLK Polarity
2 sync_pclkPolarity 0 ‘0’ : Disable. ( default )
on
‘1’ : Enable.
Stand by Level
1 stdbyLevel 1 ‘0’ : Output level in stand by mode. ( default )
‘1’ : Hi
Hiz iin stand
t db by mode.
d
0 Reserved 0
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(275-282) CCIR656 Sync Index Value < Group B >

# default value
dec hex dec hex bin
275 13 sync_blank
bl k EAV
EAV_f0
f0 182 B6 10110110 RW 5 blankk EAV
bl off fi
field0(odd)
ld0( dd) or bl
blankk EAV off fframe
276 14 sync_blank SAV_f0 171 AB 10101011 RW 5 blank SAV of field0(odd) or blank SAV of frame
277 15 sync_activEAV_f0 157 9D 10011101 RW 5 active EAV of field0(odd) or active EAV of frame
278 16 sync_activSAV_f0 128 80 10000000 RW 5 active SAV of field0(odd) or active SAV of frame
279 17 sync_blank EAV_f1 241 F1 11110001 RW 5 blank EAV of field1(even)
280 18 sync_blank SAV_f1 236 EC 11101100 RW 5 blank SAV of field1(even)
l
281 19 sync_activEAV_f1 218 DA 11011010 RW 5 active EAV of field1(even)
282 1A sync_activSAV_f1 199 C7 11000111 RW 5 active SAV of field1(even)
tia
Default : 13h = B6h, 14h = ABh, 15h = 9Dh, 16h = 80h, 17h = F1h, 18h = ECh, 19h = DAh, 1Ah = C7h
Description :
EAV and SAV signals are inserted for synchronization purposes.
BlankSAV : Blank Range Start of Video en
BlankEAV : Blank Range End of Video
ActiveSAV : Active Range Start of Video
ActiveEAV : Active Range Stop of Video
fid
Vsync
Hsync
SAV EAV SAV aEAV aSAV aEAV aSAV EAV SAV

on
... 80 10 80 10 80 10 80 10FF 00 00 XY ... FF 00 00 XY 80 10 80 1080 10 80 10

EAV : blank EAV, SAV : blank SAV
aEAV : Active EAV
EAV, aSAV : Active SAV
Usage:
i) dout_select( format2 register ) = “00b” or “11b”
C
- sync_blank_EAV_f0 ~ sync_activSAV_f0 registers used.

ii) dout_select( format2 register) = “01b”
- sync_blank_EAV_f0 ~ sync_activSAV_f0 registers used for odd field.
- sync_blank_SAV_f1 ~ sync_activSAV_f1 registers used for even field.
iii) dout_select(format2 register) = “10b”
- sync_blank_EAV_f0 ~ sync_activSAV_f0 registers used only.
.
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(283-286) Sync CCIR < Group B >

# default value
dec hex dec hex bin
283 1B sync_ccirFF
sync ccirFF 255 FF 11111111 RW 5 CCIR data format FFh
284 1C sync_ccir00 0 00 00000000 RW 5 CCIR data format 00h
285 1D sync_ccir80 128 80 10000000 RW 5 CCIR data format 80h
286 1E sync_ccir10 16 10 00010000 RW 5 CCIR data format 10h
Default : 1Bh = FFh, 1Ch = 00h, 1Dh = 80h, 1Eh = 10h
l
Description :
tia
CCIR data format FFh
CCIR data format 00h
(288-290) Scale
dec
288
#
hex
20
register name
scale_x
dec
32
default value
hex
20
bin
00100000
en
type stage
RW 6
Description
Horizontal scale factor ( 20h = x1 )

289 21 scale_y U U UUUUUUUU RW 6 Vertical scale factor ( 20h = x1 )
290 22 scale_th 4 04 00000100 RW 6 scale threshold
fid
Default : 80h = 20h, 81h = variable with wire-strap setting, 82h = 04h
Description :
Scale X : 80h
80h, Horizontal scale factor 20h = x1
Scale Y : 81h, Horizontal scale factor 20h = x1
Scale Th : 82h, Scale threshold
on
Usage:
i) NTSC, NTSC-J or (M)PAL
- scale_x = 20h, scale_y = 40h(x1/2)
ii) PALs
- scale_x = 20h, scale_y = 35h(x3/5)
C
(292-293) yContast / yBrightness

# default value
dec hex dec hex bin
292 24 ycontrast 64 40 01000000 RW 6 Y contrast
293 25 ybrightness 1 01 00000001 RW 6 Brightness
Default : 24h = 40h, 25h = 01h

Description :
Luminous (Y) = Conversion Y x Contrast + Brightness
* Brightness : 2’s complement arithmetic ; range (-128) ~ (+127)
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
< Group B >
(294) Y Max
# default value
dec hex dec hex bin
294 26 ymax 254 FE 11111110 RW 6 max. Y
Default : 26h = FEh,

Description :
l
Out Y Maximum (Clamping) data.
tia
YUV : 1 ~ Y_clamp * 0, 255 : CCIR656 special number.
(295-296) Sepia Color : Cb tone / Cr tone
dec
295
#
hex
27
register name
sephia_cb
dec
192
default
d f lt value
hex
C0
l
bin
11000000
en
type stage
RW 6
Description
Cb sephia
296 28 sephia_cr 64 40 01000000 RW 6 Cr sephia
Default : 27h = C0h, 28h = 40h

fid
Description :
fixed color ((Cb / Cr ) data when sepia
p or color vignette
g mode.
Cb Color tone : sephia_cb
Cr Color tone : sephia_cr
on
(302-304) Edge Enhancement

C
# default value
dec hex dec hex bin
302 2E edge_gain 36 24 00100100 RW 5 Reference Edge Gain - 1
303 2F edge
g _thp
p 16 10 00010000 RW 5 Positive Edge
g Threshold
Default : 2Eh = 10h , 2Fh = 10h, 30h = 1Fh

Description :
Edge Gain : 0x04 = x1
Edge Threshold : Positive Edge enhancement threshold.
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(314-328) Gamma Coefficient < Group B >

# default value
dec hex dec hex bin
314 3A gm y0
gm_y0 0 00 00000000 RW 5 Gamma Y0
315 3B gm_y1 12 0C 00001100 RW 5 Gamma Y1
316 3C gm_y2 25 19 00011001 RW 5 Gamma Y2
317 3D gm_y3 39 27 00100111 RW 5 Gamma Y3
318 3E gm_y4 52 34 00110100 RW 5 Gamma Y4
319 3F gm_y5 75 4B 01001011 RW 5 Gamma Y5
l
320 40 gm_y6 92 5C 01011100 RW 5 Gamma Y6
321 41 gm_y7 116 74 01110100 RW 5 Gamma Y7
tia
322 42 gm_y8 134 86 10000110 RW 5 Gamma Y8
323 43 gm_y9 164 A4 10100100 RW 5 Gamma Y9
324 44 gm_y
g y10 186 BA 10111010 RW 5 Gamma Y10
325 45 gm_y11 206 CE 11001110 RW 5 Gamma Y11
326 46 gm_y12 224 E0 11100000 RW 5 Gamma Y12
327 47 gm_y13 241 F1 11110001 RW 5 Gamma Y13
328 48 gm_y14 255 FF 11111111 RW 5 Gamma Y14
Description :
en
Default : 00h, 0Ch, 19h, 27h, 34h, 4Bh, 5Ch, 74h, 8Ch, A4h, BAh, CEh, E0h, F1h, FFh
Gamma Correction is applied to RGB signal which ranges from 0 to 255 to compensate
non-linear characteristics of display brightness vs input brightness. In many cases,
power function of 0.45 is used as gamma function for CRT display.
fid
Gamma Out
GC14
GC13
GC12
GC11
on
GC10
GC9
GC8
GC7
GC6
GC5
C
GC4
GC3
GC2
GC1
GC0 Gamma In
0 4 8 12 16 24 32 48 64 96 128 160 192 224 256
GC : Gamma coefficient
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(330-344) Lens Shading Compensation < Group B >

# default value
dec hex dec hex bin
330 4A llens_gainr
i 0 00 00000000 RW 5 Red
R d llens gain
i
331 4B lens_gaing1 0 00 00000000 RW 5 Gr lens gain
332 4C lens_gaing2 0 00 00000000 RW 5 Gb lens gain
333 4D lens_gainb 0 00 00000000 RW 5 Blue lens gain
336 50 lens_rx 0 00 00000000 RW 5 red lens x origin
337 51 lens_ry 0 00 00000000 RW 5 red lens y origin
l
338 52 lens_g1x 0 00 00000000 RW 5 green1 lens x origin
339 53 lens_g1y 0 00 00000000 RW 5 green1 lens y origin
tia
340 54 lens_g2x 0 00 00000000 RW 5 green2 lens x origin
341 55 lens_g2y 0 00 00000000 RW 5 green2 lens y origin
342 56 lens_bx 0 00 00000000 RW 5 blue lens x origin
343 57 lens_by 0 00 00000000 RW 5 blue lens y origin
344 58 lens_scale 81 51 01010001 RW 5 East/West/South/North lens scale factor
Default : 4Ah = 00h, 4Bh = 00h, 4Dh = 00h, 50h = 00h, 51h = 00h
Description :
en
52h = 00h, 53h = 00h, 54h = 00h, 55h = 00h, 56h = 00h, 57h = 00h, 58h = 51h
Lens Gain R : Lens Shading Gain. 0x20 = x 1 gain.

Lens Gain G1 : Lens Shading Gain. 0x20 = x 1 gain.
fid
Lens Gain G2 : Lens Shading Gain, 0x20 = x 1 gain.
Lens Gain B : Lens Shading Gain. 0x20 = x 1 gain.
Lens Red XY Origin
O : Window center origin Red XY value
for Lens shading compensation
Lens Green XY Origin : Window center origin Green XY value for
on
Lens shading compensation

Lens Blue XY Origin : Window center origin Blue XY value for
g compensation
Lens shading p
Lens Scale : East/West/South/North lens scale factor
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(351-360) Edge data for auto focus < Group B >

# default value
dec hex dec hex bin
351 5F af_cweight
af cweight 7 07 00000111 RW 6 af center weight
352 60 af_cwinx1_h 1 01 00000001 RW 6 af window X1_H
353 61 af_cwinx1_l 104 68 01101000 RW 6 af window X1_L
354 62 af_cwinx2_h 2 02 00000010 RW 6 af window X2_H
355 63 af_cwinx2_l 48 30 00110000 RW 6 af window X2_L
356 64 af_cwiny1_h 0 00 00000000 RW 6 af window Y1_H
l
357 56 af_cwiny1_l 179 B3 10110011 RW 6 af window Y1_L
358 66 af_cwiny2_h 1 01 00000001 RW 6 af window Y2_H
tia
359 67 af_cwiny2_l 72 48 01001000 RW 6 af window Y2_L
360 68 af_edge_th 0 00 00000000 RW 6 af edge threshold
Default : 5Fh = 07h, 60h = 01h, 61h = 68h, 62h = 02h, 63h = 30h, 64h = 00h, 65h = B3h
66h = 01h, 67h = 48h, 68h = 00h
Description :
af_cweight : center weight of edge
en
af_edge_sum=center_edge_sum * af_cweight +peri_edge_sum*(16-af_cweight) / 16
af_cwinx1, af_cwinx2, af_cwiny1, af_cwiny2 : AF Center window x and y position

af_edge_th : edge threshold for af_edge_sum
fid
Related Reg.: BankA – windowx1(0A,0Bh), windowy1(0C,0Dh), windowx2(0E,0Fh), windowy2(10,11h)
BankD – af_edge_sum4~1 (38~3Bh)
on
* AF Center window
row count
windowy1: 14d
(default)
C
af_cwiny1 : 179d
(default)
af_cwiny1 : 328d
(default)
windowy2: 493d (VGA)
windowx1 af_cwinx1 af_cwinx2 windowx2

column count 131d (default) 360d (default) 560d (default) 770d (default)
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(362) TP control 0 < Group B >

# default value
dec hex dec hex bin
362 6A tp control 0
tp_control_0 0 00 00000000 RW 5 Test Pattern control register 00
l
TPC = 01h TPC = 02h TPC = 03h TPC = 04h TPC = 05h
tia
TPC = 06h TPC = 07h TPC = 08h TPC = 09h TPC = 0Ah
en
TPC = 0Bh TPC = 0Ch TPC = 0Dh TPC = 0Eh TPC = 0Fh
fid
on
C
TPC = 1Ah TPC = 1Bh TPC = 1Ch TPC = 1Dh TPC = etc
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(363~367) TP control 1~5 < Group B >

# default value
dec hex dec hex bin
363 6B tp_control_1
tp control 1 255 FF 11111111 RW 5 Test Pattern control register 01
364 6C tp_control_2 255 FF 11111111 RW 5 Test Pattern control register 02
365 6D tp_control_3 255 FF 11111111 RW 5 Test Pattern control register 03
366 6E tp_control_4 255 FF 11111111 RW 5 Test Pattern control register 04
l
tia
Default : 6Bh = FFh, 6Ch = FFh, 6Dh = FFh, 6Eh = FFh, 6Fh = 00h
Description :
tp_control_1 : R of Bayer
tp_control_2 : G1 of Bayer en
tp_control_3 : G2 of Bayer
tp_control_4
l 4 : B off B
Bayer
fid
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(374) Filcker Control 2 < Group B >

# default value
dec hex dec hex bin
374 76 fli k er_control2
flick t l2 U U UUUUUUUU RW 5 fli k er mode
flick d control
t l register
i t 02
Default : 76h = variable with wire_strapping

Description :
l
tia
register name : flicker_control_2
7 Reserved U
6 fd_en U Auto flicker detection enable
( )
374(d)
76(h)
5
3
Reserved
Reserved
manual_A
U
U
en Manual_A
2 manual_B U Manual_B
1 U
fid
Reserved
0 U
Mode Bit3 Bit2 Bit6

(manual60) (manual50) (fd_en)
on
Normal 0 0 0
(flicker mode off)
Manual 60Hz flicker mode 1 0 0
Manual 50Hz flicker mode 0 1 0
C
Auto Flicker Detection 0 0 1
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(392-413) Filcker cancellation method2 < Group B >

# default value
dec hex dec hex bin
401 91 fd period a h
fd_period_a_h U U UUUUUUU RW 5 flick er period for CASE A (H)
402 92 fd_period_a_m U U UUUUUUU RW 5 flick er period for CASE A (M)
403 93 fd_period_a_l U U UUUUUUU RW 5 flick er period for CASE A (L)
404 94 fd_period_b_h U U UUUUUUU RW 5 flick er period for CASE B (H)
405 95 fd_period_b_m U U UUUUUUU RW 5 flick er period for CASE B (M)
406 96 fd_period_b_l U U UUUUUUU RW 5 flick er period for CASE B (L)
l
407 97 fd_period_c_h U U UUUUUUU RW 5 flick er period for 1/20 sec (H)
408 98 fd_period_c_m U U UUUUUUU RW 5 flick er period for 1/20 sec (M)
tia
409 99 fd_fheight_a_h U U UUUUUUU RW 5 flick er frameheight for CASE A (H)
410 9A fd_fheight_a_l U U UUUUUUU RW 5 flick er frameheight for CASE A (L)
411 9B fd fheight b h
fd_fheight_b_h U U UUUUUUU RW 5 flick er frameheight for CASE B (H)
412 9C fd_fheight_b_l U U UUUUUUU RW 5 flick er frameheight for CASE B (L)
Default : 91h ~ 9Ch = variable with wire_strapping,
Description :
FD Period A : Exposure period A
en
FD Period B : Exposure period B
FD Period C : Exposure period C
FD Frame Height A : Frame Height for each state A
fid
FD Frame Height B : Frame Height for each state B
on
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(420) Encoder control < Group B >

# default value
dec hex dec hex bin
420 A4 encoder control 0 00 00000000 RW 5 encoder control
Default : A4h = 00h

Description :
l
tia
register name : Encoder control
7 encoder_off 0 ‘1’- encoder off, ‘0’- encoder on
6 Reserved 0
420(d)
A4(h)
5
3
Reserved
enc_colorbar_en
enc_colorbar_mode
en
0
0
Colorbar on/off
‘0’-100% color bar, ‘1’-75% color bar
2 Reserved 0
1 Reserved 0
fid
0 Reserved 0
on
(421) enc_scfreq
# default value
dec hex dec hex bin
421 A5 enc_scfreq U UU UUUUUUUU RW 5 subcarrier frequency selection
Default : A5h : wire-strapping register

C
Description :
enc_scfreq : sub-carrier frequency selection
“00” : 3.579545 MHz for (M) NTSC, NTSC-J
“01” : 4.43361875 MHz for (B, D, G, H, I, N) PAL
“10” : 3.58205625 MHz for (Nc) PAL
“11” : 3.57561149 MHz for (M) PAL
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(422-437) Composite level parameters < Group B >

# default value
dec hex dec hex bin
422 A6 enc sync
enc_sync 16 10 00010000 RW 5 sync level
423 A7 enc_blank H 0 00 00000000 RW 5
blank level
424 A8 enc_blank L U UU UUUUUUUU RW 5
425 A9 enc_pedestal U UU UUUUUUUU RW 5 pedestal
426 AA enc_burst U UU UUUUUUUU RW 5 burst amplitude
427 AB enc_Ygain U UU UUUUUUUU RW 5 Y convergence gain from YCbCr to YUV
l
428 AC enc_Ugain U UU UUUUUUUU RW 5 U convergence gain from YCbCr to YUV
429 AD enc_Vgain U UU UUUUUUUU RW 5 V convergence gain from YCbCr to YUV
tia
430 AE enc_Yrange_H 3 03 xxxxx011 RW 5
max. luminance
431 AF enc_Yrange_L 32 20 00100000 RW 5
432 B0 enc Crange H
enc_Crange_H 1 01 xxxxx001 RW 5
max. amplitudes of chrominance
433 B1 enc_Crange_L U U UUUUUUUU RW 5
434 B2 enc_chroma_max_H 3 03 xxxxx011 RW 5
maximum chrominance of composite output
435 B3 enc_chroma_max_L U U UUUUUUUU RW 5
436 B4 enc_chroma_min_H 0 00 xxxxx000 RW 5
minmum chrominance of composite output
437 B5 enc_chroma_min_L U U UUUUUUUU RW 5
A8h, A9h, AAh

AAh, ABh
ABh, ACh
ACh, ADh
Description : please refer to next page.
ADh, B1h
B1h, B3h
en
Default : A6h = 10h, A7h = 00h, AEh = 03h, AFh = 20h, B0h = 01h, B2h = 03h, B4h = 00h
A8h A9h B3h, B5h : wire
wire-strapping
strapping registers (refer to page14)
enc_sync : sync_level
enc_blank : blank level
fid
enc_pedestal : pedestal level
enc_burst : burst amplitude
enc_Y/U/Vgain: Conversion gain of YCbCr to YUV
enc_Yrange : separate Y range into positive and negative regions.
enc_Crange : define maximum level of Chrominance
on
enc_chroma_max: define maximum level of Composite.

enc_chroma_min: define minimum level of Composite.
C
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
< Group B >
1534
1023 enc_chroma_max
white
l
tia
enc_burst en enc_pedestal
enc_blank
enc_sync
enc_chroma_min
0
fid
- 512
reg_chroma_max/min registers define the max. and min. of active data level.
on
Y value 511
1023
reg_Crange
reg_Yrange
0
C
- reg_Crange
- 511
0
reg_Yrange defines the boundary between positive or reg_Crange designates the maximum amplitude of chroma.
negative
g number of Y before composition.
p It can be one of 0 to 511.
In colorbar, Y might be negative values. It is the reason why
the register exists.
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(473) burst_toffset < Group B >

# default value
dec hex dec hex bin
473 D9 burst toffset
burst_toffset 0 00 00000000 RW 5 Burst Time offset
Default : D9h = 00h
l
Description :
tia
burst_toffset : Burst time offset
It changes burst position on Back Porch
Porch.
msb: sign, other bits : magnitude
en
burst_toffset: 00h
fid
burst_toffset: 88h
on
C
burst_toffset: 08h
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(485-496) motion detection < Group B >

# default value
dec hex dec hex bin
485 E5 md_yth
md yth 64 40 01000000 RW 5 Y(luminance) threshold for motion detection
486 E6 md_diff 64 40 01000000 RW 5 Difference of brightness between current and previous frames
487 E7 md_interval 8 08 00001000 RW 5 frame interval for motion detection
489 E9 md_section7 255 FF 11111111 RW 5
490 EA md_section6 255 FF 11111111 RW 5
491 EB md_section5 255 FF 11111111 RW 5
l
492 EC md_section4 255 FF 11111111 RW 5
mask s of 64 sections on one frame
493 ED md_section3 255 FF 11111111 RW 5
tia
494 EE md_section2 255 FF 11111111 RW 5
495 EF md_section1 255 FF 11111111 RW 5
496 F0 md_section0 255 FF 11111111 RW 5
Default : E5h = 40h, E6h = 40h, E7h = 08h, E9h ~ F0h = all FFh
Description :
the same section.

en
md_yth: Threshold of Y (luminance) mean difference between current and previous frames at
md_diff: Difference between entire current and previous frame’s brightness means
md_interval: define frame interval for motion detection.
md_section7~0 : masks of 64 sections on one frame
fid
md_section7(7) – mask bit for 63rd section,
md_section7(6) – mask bit for 62nd section,
md section7(5) – mask bit for 61st section,
md_section7(5) section
…
md_section0(7) – mask bit for 7th section,
on

md_section0(3) – mask bit for 3rd section,
md_section0(2) – mask bit for 2nd section,
md_section0(1) – mask bit for 1st section,
640
C
md_section0(0) – mask bit for 0th section

0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
480
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63 60
80
< Group B >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Register Tables ( Detailed ) : Group C < Group C >
(516) Auto
A to control 1
# default value
dec hex dec hex bin
516 04 auto_control_1 152 98 10011000 RW 6 auto control register 01
l
Default : 04h = 98h
tia
Description :
register name : auto_control_01
5
Reserved
Reserved
Reserved
en 1
4 Reserved 1
3 Reserved 1
fid
516(d)
04(h) Auto White Balance Register update
Auto White Balance Register
2 0 ‘0’ : Update by internal function (default)
Update
‘1’ : Update
p by
y external interface
Auto Exposure Register update

1 0
00b : Update by Internal function. (default)
Auto Exposure Register
01b : Update by Exposure register
Update(1:0)
0 0 10b : Update by External_Inttime & Linear Gain
on
11b : Update by Inttime & Globalgain register

C
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(518) Auto control 3 < Group C >

# default value
dec hex dec hex bin
518 06 auto_control_3
t t l 3 144 90 10010000 RW 5 auto
t control
t l register
i t 03
Default : 06h = 90h

Description :
l
tia
register name : auto_control_03
7 Reserved 1
LED Control 1 Enable

6 LED Control 1 EN 0 ‘0’ : Disable (default)
5 LED Control 2 EN
en 0
‘1’ : Enable
LED Control 2 Enable

‘0’ : Disable (default)
‘1’ : Enable
518(d) 4 Reserved 1
06(h)
fid
3 Reserved 0
2 Reserved 0
1 0
Reserved
0 0
on
C
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(519-521) External Integration Time < Group C >

# default value
dec hex dec hex bin
519 07 ext_inttime_h
t i tti h 0 00 00000000 RW 6 External
E t l Integration
I t ti Time
Ti (H)
520 08 ext_inttime_m 128 80 10000000 RW 6 External Integration Time (M)
521 09 ext_inttime_l 0 00 00000000 RW 6 External Integration Time (L)
Default : 07h = 00h, 08h = 80h, 09h = 00h
l
Description :
tia
Manual external integration time
(522-523) External linear Globalgain
dec
522
523
#
hex
0A
0B
register name
ext_glbg_h
ext_glbg_l
dec
1
0
default value
hex
01
00
bin
00000001
00000000
RW
RW
en
type stage
6
6
Description
External Globalgain (H)

External Globalgain (L)
Default : 0Ah = 01h, 0Bh = 00h

Description :
fid
Manual external Globalgain.
(524-527) Exposure Register

# default value
dec hex dec hex bin
on
524 0C exposure_t 0 00 00000000 RW 6 Current Exposure (T)

525 0D exposure_h 0 00 00000000 RW 6 Current Exposure (H)
526 0E exposure_m 128 80 10000000 RW 6 Current Exposure (M)
527 0F exposure_l 0 00 00000000 RW 6 Current Exposure (L)
Default : 0Ch ( Exposure Register - T ) = 00h

0Dh ( Exposure Register - H ) = 00h
C
0Eh ( Exposure Register - M ) = 80h

0Fh ( Exposure Register - L ) = 00h
Description :
Exposure[31:0] : “Exposure” register means abstract exposure level of sensor. Larger the
value of Exposure, effectively longer exposure time. LSB of Exposure
corresponds to 1/256 line exposure time. User can write Exposure
register only when AE function is disabled.
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(528-529) Exposure FrameHeight < Group C >

# default value
dec hex dec hex bin
528 10 expFrmH_H
F H H 2 02 00000010 RW 5 Reference
R f Exposure
E F
FrameHeight
H i ht (H)
529 11 expFrmH_L 12 0C 00001100 RW 5 Reference Exposure FrameHeight (L)
Default : 10h = 02h, 11h = 0Ch
l
tia
(530-533) Middle / Maximum FrameHeight
dec
d
530
531
#
hex
h
12
13
register
g name
midfrmheight_h
midfrmheight_l
dec
d
2
12
default
h
hex
02
0C
value
bi
bin
00000010
00001100
RW
RW
en
type
yp stage
g
5
5
Description
p
Middle FrameHeight (H)

Middle FrameHeight (L)
532 14 maxfrmheight_h 2 02 00000010 RW 5 Max FrameHeight (H)
533 15 maxfrmheight_l 12 0C 00001100 RW 5 Max FrameHeight (L)
fid
Default : 12h = 02h, 13h = 0Ch, 14h = 02h, 15h = 0Ch
on
(534-542) Middle / Maximum / Minimum Exposure

# default value
dec hex dec hex bin
534 16 minexp_h 0 00 00000000 RW 5 Middle Exposure (T)
535 17 minexp_m 0 00 00000000 RW 5 Middle Exposure (H)
C
536 18 minexp_l 12 0C 00001100 RW 5 Middle Exposure (M)

537 19 midexp_t 0 00 00000000 RW 5 Max Exposure (T)
538 1A midexp_h 65 41 01000001 RW 5 Max Exposure (H)
539 1B midexp_m 159 9F 10011111 RW 5 Max Exposure (M)
540 1C maxexpp_t 0 00 00000000 RW 5 Min Exposure
p ((H))
541 1D maxexp_h 65 41 01000001 RW 5 Min Exposure (M)
542 1E maxexp_m 159 9F 10011111 RW 5 Min Exposure (L)
Default : 16h = 00h, 17h = 00h, 18h = 0Ch, 19h = 00h, 1Ah = 41h, 1Bh = 9Fh, 1Ch = 00h, 1Dh = 41h
1Eh = 9Fh
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(549) AE center Weight < Group C >

# default value
dec hex dec hex bin
549 25 ae_c_weight
i ht 3 03 00000011 RW 6 AE Center
C t Weight
W i ht
Default : 25h = 03h,

Description :
l
Center window weight (CW) for back light compensation.
tia
((Yc × CW)) + ( Yp
p × ((16 – CW)) ) Yc : Center window Y mean
Bright mean =
16 Yp : Periphery Y mean.
en
(550-551) Auto Exposure Speed
fid
# default value
dec hex dec hex bin
550 26 ae_up_speed 8 08 00001000 RW 6 AE upside Speed
551 27 ae_down_speed 12 0C 00001100 RW 6 AE downside Speed
Default : 26h = 08h, 27h = 0Ch

Description :
AE up Speed : AE speed applied when exposure is decreasing.
on
AE down Speed : AE speed applied when exposure is increasing

C
(552) Auto Exposure Lock

# default value
register
i t name t
type stage
t D
Description
i ti
dec hex dec hex bin
552 28 ae_lock 10 0A 00001010 RW 6 AE lock range
Default : 28h = 0Ah,

Description :
set margin of Auto Exposure function.
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
< Group C >
(564) User wYt
# default value
dec hex dec hex bin
564 34 user_wyt 128 80 10000000 RW 2 user Y target
Default : 34h = 80h

Description :
l
User weight Y target offset
tia
en
fid
(590-597) AE Window
# default value
dec hex dec hex bin
590 4E ae_winx_h 0 00 00000000 RW 5 AE window start X position(H)
591 4F ae_winx_l 26 1A 00011010 RW 5 AE window start X position(L)
592 50 ae_winy_h 0 00 00000000 RW 5 AE window start Y position(H)
on
593 51 ae_winy_l U UU UUUUUUUU RW 5 AE window start Y position(L)

594 52 ae_width_h 2 02 00000010 RW 5 AE window Width (H)
595 53 ae_width_l 108 6C 01101100 RW 5 AE window Width (L)
596 54 ae_height_h U UU UUUUUUUU RW 5 AE window Height (H)
597 55 ae height l
ae_height_l U UU UUUUUUUU RW 5 AE window Height (L)
Default : 4Eh = 00h, 4Fh = 1Ah, 50h = 00h, 52h = 02h, 53h = 6Ch,
51h , 54h , 55h – wire strapping register (refer to page14)
C
Description :
ae_winx : AE window start X position
_ y : AE window start Y p
ae_winy position
ae_width : AE window Width
ae_height : AE window Height
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(598-605) AE Center Window < Group C >

# default value
dec hex dec hex bin
598 56 ae_cwinx_h
ae cwinx h 0 00 00000000 RW 5 AE Center window start X position(H)
599 57 ae_cwinx_l 210 D2 11010010 RW 5 AE Center window start X position(L)
600 58 ae_cwiny_h 0 00 00000000 RW 5 AE Center window start Y position(H)
601 59 ae_cwiny_l U UU UUUUUUUU RW 5 AE Center window start Y position(L)
602 5A ae_cwidth_h 0 00 00000000 RW 5 AE Center window Width (H)
603 5B ae_cwidth_l 200 C8 11001000 RW 5 AE Center window Width (L)
l
604 5C ae_cheight_h 0 00 00000000 RW 5 AE Center window Height (H)
605 5D ae_cheight_l U UU UUUUUUUU RW 5 AE Center window Height (L)
tia
Default : 56h = 00h
00h, 57h = D2h
D2h, 58h = 00h
00h, 5Ah = 00h
00h, 5Bh = C8h
C8h, 5Ch = 00h
59h, 5Dh – wire strapping register ( refer to page14)
Description :
ae_cwinx : AE Center window start X position
ae_cwiny : AE Center window start Y position
ae_cwidth : AE Center Window Width
ae_cheight : AE Center Window Height
en
fid
Default window width = 640

Window Start Point
( Window X1 ,
Window Y1 )
on
= ( 1, 1 )
( X1, Y1 )
window
Height = 480
ae cheight
ae_cheight ((ae_cwinx,, ae_cwiny)
y)
Default w
( X2, Y2 )
C
Window Stop Point

( Window X2 , Window Y2 ) ae_cwidth
= ( 640, 480 )
C t window
Center i d
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(666-675) AWB Window < Group C >

# default value
dec hex dec hex bin
666 9A awb_winx1_h
awb winx1 h 0 00 00000000 RW 5 AWB window start X position(H)
667 9B awb_winx1_l 124 7C 01111100 RW 5 AWB window start X position(L)
668 9C awb_winy1_h 0 00 00000000 RW 5 AWB window start Y position(H)
669 9D awb_winy1_l 46 2E 00101110 RW 5 AWB window start Y position(L)
670 9E awb_winx2_h 3 03 00000011 RW 5 AWB window end X position (H)
671 9F awb_winx2_l 0 00 00000000 RW 5 AWB window end X position(L)
l
672 A0 awb_winy2_h 1 01 00000001 RW 5 AWB window end Y position(H)
673 A1 awb_winy2_l 202 CA 11001010 RW 5 AWB window end Y position(L)
tia
674 A2 awb_deltax 0 00 00000000 RW 5 AWB delta X for awb center window
675 A3 awb_deltay 0 00 00000000 RW 5 AWB delta Y for awb center window
Default : 9Ah = 00h, 9Bh = 7Ch, 9Ch = 00h, 9Dh = 2Eh, 9Eh = 03h, 9Fh = 00h, A0h = 01h,
A1h = CAh, A2h = 00h, A3h = 00h
Description : en
awb_winx1 : AWB window start X position
awb_winy1
b i 1 : AWB window
i d start
t t Y position
iti
awb_winx2 : AWB Window end X position
awb_winy2 : AWB Window end Y position
awb_deltax : AWB delta X for awb center window from awb_winx1 and awb_winx2
fid
awb_deltay : AWB delta Y for awb center window from awb_winy1 and awb_winy2
on
awb_winx2 – awb_winx1 + 1
AWB Window Start Point
( awb_winX1
_ ,
wb_winy2 – awb_winy1 +1
1
awb_windY1 )
= ( 124,46 )
C
awb_deltay
awb
AWB Window Stop Point

( awb_winX2 , awb_win Y2 ) awb_deltax
= ( 768, 458 )
Center window
reference count : rcount and ccount
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(676-677) AWB R/B ratio < Group C >

# default value
dec hex dec hex bin
676 A4 awb_rgratio
b ti 128 80 10000000 RW 5 AWB Red/Green
R d/G Ratio
R ti
677 A5 awb_bgratio 128 80 10000000 RW 5 AWB Blue/Green Ratio
Default : A4h = 80h, A5h = 80h

Description :
l
awb_rgratio : Red mean target = Evaluate Green mean x R ratio / 128
tia
awb_bgratio : Blue mean target = Evaluate Green mean x B ratio / 128
(678) Auto White Balance Lock

# default value
en
dec hex dec hex bin
678 A6 awb_lock 2 02 00000010 RW 5 AWB lock range
fid
Default : A6h = 02h,
Description :
awb lock : Set margin of Auto White Balance functions
awb_lock
on
(679) Auto White Balance Speed

C
# default value
dec hex dec hex bin
679 A7 awb_speed 8 08 00001000 RW 5 AWB speed ( target AWB step numbers : 16 steps need to approach at One Time )
Default : A7h = 08h

08h,
Description :
awb_speed : Auto White Balance evaluate speed.
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(697-705) Color Correction Coefficients < Group C >

# default value
dec hex dec hex bin
697 B9 cc11
11 56 38 00111000 RW 5 Color
C l correction
ti matrix
t i (1 , 1)
698 BA cc12 165 A5 10100101 RW 5 Color correction matrix (1 , 2)
699 BB cc13 13 0D 00001101 RW 5 Color correction matrix (1 , 3)
700 BC cc21 147 93 10010011 RW 5 Color correction matrix (2 , 1)
701 BD cc22 45 2D 00101101 RW 5 Color correction matrix (2 , 2)
702 BE cc23 6 06 00000110 RW 5 Color correction matrix (2 , 3)
l
703 BF cc31 131 83 10000011 RW 5 Color correction matrix (3 , 1)
704 C0 cc32 170 AA 10101010 RW 5 Color correction matrix (3 , 2)
tia
705 C1 cc33 77 4D 01001101 RW 5 Color correction matrix (3 , 3)
Default : B9h = 38h, BAh = A5h, BBh = 0Dh, BCh = 93h, BDh = 2Dh, BEh = 06h, BFh = 83h,
C0h=AAh, C1h = 4Dh
Description :
R’
G’
B’
=
en
cc11 cc12 cc13
cc21 cc22 cc23 *
cc31 cc32 cc33
R
G
B
R’, G’ and B’ are color corrected R,G and B

fid
on
C
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(748-750) LED Control Threshold < Group C >

# default value
dec hex dec hex bin
748 EC led th1 t
led_th1_t 0 00 00000000 RW 5
749 ED led_th1_h 0 00 00000000 RW 5 led control threshold 1
750 EE led_th1_m 0 00 00000000 RW 5
751 EF led_th2_t 0 00 00000000 RW 5
752 F0 led_th2_h 0 00 00000000 RW 5 led control threshold 2
753 F1 led_th2_m 0 00 00000000 RW 5
l
754 F2 led_th3_t 0 00 00000000 RW 5
755 F3 led_th3_h 0 00 00000000 RW 5 led control threshold 2
tia
756 F4 led_th3_m 0 00 00000000 RW 5
757 F5 led_th4_t 0 00 00000000 RW 5
758 F6 led th4 h
led_th4_h 0 00 00000000 RW 5 led control threshold 2
759 F7 led_th4_m 0 00 00000000 RW 5
Default : All = 00h

Description :
LED Control Threshold en
fid
exp < reg_led_th1 : LOW
reg_led_th1 < exp ≤ reg_led_th2 : HOLD
reg_led_th2 < exp : HIGH
on
exp < reg_led_th3 : LOW

reg_led_th3 < exp ≤ reg_led_th4 : HOLD
C
reg_led_th4 < exp : HIGH
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(761) User CS < Group C >

# default value
dec hex dec hex bin
761 F9 user cs
user_cs 32 20 00100000 RW 5 user cs
Default : F9 = 20h
Description : User Color Saturation
l
tia
▶ Register
R i t Tables
T bl ( Detailed
D t il d ) : Group
G D
(825) af_edge_sum
dec
830
831
#
hex
3E
3F
register name
af_edge_sum_4
af_edge_sum_3
dec
0
0
default value
hex
0
0
bin
RO
RO
en
type stage
0
0
Description
edge data for auto focus(T)

edge data for auto focus(H)
832 40 af_edge_sum_2 0 0 RO 0 edge data for auto focus(M)
833 41 af_edge_sum_1 0 0 RO 0 edge data for auto focus(L)
fid
Description :
af_edge_sum : edge data for auto focus support
on
C
< Group C >

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Electrical Characteristics
Absolute
Ab l t Maximum
M i Ratings
R ti *
HVDD,AVDD Supply Voltage ------------------------------------------------ -0.3V to 4.5V
DVDD Supply Voltage --------------------------------------------------------- -0.3V to 2.5V
DC Voltage at any input pin ---------------------------------------------------- -0.3V to HVDD+0.3V
DC Voltage at any output pin --------------------------------------------------- -0.3V to HVDD+0.3V
l
Storage Temperature ------------------------------------------------------------ -40°C to + 125 °C
tia
Table 4
4. DC Characteristics
Symbol Descriptions Min Typ Max Unit

VDDD Digital VDD voltage relative to GND( DGND) level. 1.71 1.8 1.89 V
VDDA
HVDD
Analog voltage relative to GND(AGND) level. en
High VDD(HVDD) voltage relative to GND(DGND) level
level.
2.66
2 66
2.66
2.8
2.8
3.3
2.94
3 47
3.47
V
Supply current at 60 fps. Currents are programmable through 2-

wire serial interface. @
fid
DVDD=1.8V 25.0 mA
IDDD
AVDD=2.8V 19.0 mA
HVDD=2.8V 4.9 mA
CVDD=2.8V 36.0 mA
Standby supply current@

on
IDDS 9 uA
DVDD=1.8V/AVDD=2.8V/HVDD=2.8V/CVDD=2.8V
VIL1 Input voltage LOW level 0.2*HVDD V
VIH1 Input voltage HIGH level 0.8*HVDD V
VIL2 Input voltage LOW level for rClk, rData. 0.2*HVDD V

VIH2 Input voltage HIGH level for rClk, rData 0.8*HVDD V
C
CIN Input pin capacitance 10 pF
VOL1 Output Voltage LOW 0.1*HVDD V
VOH1 Output Voltage HIGH 0.9*HVDD V

VOL2 Output Voltage LOW level for rClk, rData. 0.2 V
VOH2 Output Voltage HIGH level for rData. HVDD-0.2 V
IIN Input leakage current 0.005 1 uA
IOT Output leakage current 0.005 1 uA
* Excessive stresses may cause permanent damage to the device.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
Table5. AC Characteristics (In case of HVDD=2.8V)

Cload=16pF
fMCLK Master clock Frequency 27 MHz
duty Master clock duty cycle 50 %
t1 Master clock rise/fall time 4.7 ns
l
t2 PCLK rise/fall time 3.5 ns
tia
t3 PCLK rising
g edge
g to HSYNC 20.85 ns
t4 PCLK rising edge to digital output 19.75 ns
t5 MCLK rising edge to PCLK rising edge 21.45 ns
t6 PCLK rising edge to VSYNC 21.1 ns
MCLK
50%
en t1 t1
t5
90%
fid
PCLK 10%
t2 t3
t3
HSYNC
t4
on
Digital
Output
Fig 12 Timing diagram of Clock,

Fig. Clock Data,
Data and HSync
t1 t1
C
50%
MCLK
t5
90%
PCLK 10%
t2 t6
t6
VSYNC
t4
Digital
Output
Fig. 13 Timing diagram of Clock, Data, and VSync

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
Table 6. Electro-Optical Characteristics ( @ 60degree )
Symbol Parameter Notes Min Typ Max Unit
l
Sens Sensitivity 1) 3.16 V/Lux.sec
tia
Vsat Saturation Level 2) 1.2 V
Vdrk Dark Signal 3) 47.9 mV/sec
DR Dynamic range 4) 63.5 dB
Notes :
en
1) This value comes from the wafer test
test. The calculation sequence is as follows
(1) read the saturation level from evaluation pad
follows.
(2) calculate One LSB.

(3) Read output signal of Green pixels under illumination with output signal equal to 50% of
fid
saturation signal.
(4) Read the Luminance and Integration Time when 50% of saturation signal.
(5) Calculate the sensitivity using (1)~(4)
= (the signal of Green pixels * one LSB ) / (luminance * integration time)
2) Read the value of evaluation pad when all pixels are saturated in condition
on
3) Measured at the zero illumination.

(1) read the dark signal average of all pixels for minimum integration time
(2) read the dark signal average of all pixels for maximum integration time
(3) [Dark signal @ maximum integration time] – [Dark signal @ minimum integration time]
(4) convert to mV/sec unit
C
4) For frame rate=60 fps

20*Log [Saturation Signal /Dark signal] [dB]

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
Power-On Sequence
DVDD t1
l
HVDD, AVDD, CVDD
tia
MCLK •••
t2
STDBY
RSTB
t3 t4
en
t5
fid
Power-Off Sequence
DVDD
t6
on
HVDD, AVDD, CVDD
Table7. Recommended Power-On/Off sequence

C

From DVDD rising to HVDD, AVDD,
t1 0 ns
CVDD rising
t2 From HVDD rising to MCLK Start 0 ns
t3 From MCLK Start to STDBY rising 0 ns

t4 From STDBY rising to falling 2 ms
t5 From STDBY rising to RSTB rising t4 x 10 ms
t66 From HVDD
F HVDD, AVDD
AVDD, CVDD ffalling
lli to
0 ns
DVDD falling

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
▶ Application Note
- Revision Number
Reg. Addr. (Hex) Read Value (Hex) Register Name Descriptions
02 00 RevNum Revision Number of PC1030N
l
tia
-Default Setting
PC1030N’s default setting is considered to meet acquirement of SMPTE-170M.-2004.
- Register Groups
en
PC1030N has four Register Groups (Register A, B, C & D).
So, you must be careful and make sure that the correct register group is firstly selected before you access registers .
Register Group can be selected by Setting Reg.03h.
Address (Hex) Write Value (Hex) Register Name Descriptions

fid
03 00 RegisterSel Select Register Group A
01 Select Register Group B
02 Select Register Group C
03 Select Register Group D

on
Ex) When you want to write (or read) the value to Reg.04h in the Register Group A,
=> 1st > Write 0x00 to Reg.03h
2nd >Write (or Read) the value to Reg.04h
Reg 04h
When you want to write (or read) the value to Reg.04h and 05h in the Register Group B,
=> 1st > Write 0x01 to Reg.03h
C
2nd >Write (or Read) the values of Reg.04h and 05h
< Notation >

We will use the following notation in this application note to separate registers according to the Register Group
which they belong to.
Register Group Notation Example
A A- A-10 : Reg.10h in Register Group A
B B-
B B-4C
B 4C : Reg
Reg.4Ch
4Ch in Register Group B
C C-
D D-

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Flicker Free Mode

(1) Manual Flicker Free Mode
-Related
R l t dRRegisters
i t : Reg.B-76h,
R B 76h R Reg.B-91h
B 91h ~ B
B-96h
96h , -Related
R l t d Strap
St pin
i : D4,D5.
D4 D5
Flicker canceling mode can be set by not only writing registers directly but also controlling by strap pin as D4,D5.
Strap setting can be ignored after register setting has been changed by EEPROM and external i2c master.
l
tia
Reg. Addr. (Hex) Register Name Default Value (Hex) Setting value Descriptions
B-91 PD_PeriodA (H) 01

MCLK Freq. / Frame Width Flicker period
B-92 PD_PeriodA (M) 06 256 *
120
B-93 PD_PeriodA (L) 3C
B-94
B-95
B-96
PD_PeriodB (H)
PD_PeriodB(M)
PD_PeriodB (L)
en
01
3A
AF
256 *
MCLK Freq. / Frame Width
100
Flicker period
Reg. Addr. (Hex) Register Name Default Value (Hex) Setting Value Descriptions
fid
B-76 FdControl02 00 80 / 88 / 84 Off / 60Hz / 50Hz
Flicker Free Enable
-Flicker Period Control Register Setting

on
ex) 60Hz flicker, MCLK = 27MHz, NTSC

Frame Width = Frame Width (Reg A-06h
A-06h,A-07h)
A-07h) + 1 = 858d.
858d
Æ FD_PeriodA = 256*(27000000 / 858 ) / (60*2) = 67132d = 1063Ch.
Æ FD_PeriodA (H) = 01h, FD_PeriodA (M) = 06h, FD_PeriodA (L) = 3Ch.
C
ex) 50Hz flicker, MCLK = 27MHz, NTSC

F
Frame Width = Frame
F Width (R
(Reg A
A-06h,A-07h)
06h A 07h) + 1 = 858d..
858d
Æ FD_PeriodB = 256*(27000000 / 776) / (50*2) = 80559d = 13AAFh.
Æ FD_PeriodB (H) = 01h, FD_PeriodB (M) = 3Ah, FD_PeriodB (L) = AFh.
*) Frame Width Value

NTSC - 0359h (857d), PAL - 040Dh (1037d)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(2) Auto Flicker Detection Mode

PC1030N support auto flicker detection mode.
Reg. Addr. (Hex) Appropriate value Register Name Default Value Descriptions
(Hex)
B-89 256 * 256 * 4 Reserved 03

60Hz flicker period (line)
l
B-8A Reserved E8
tia
B-8B 256 * 256 * 4 Reserved 03
50H flicker
50Hz fli k period
i d (line)
(li )
B-8C Reserved 42
B-90 Appropriate Value FD_Th 10 Flicker Detection

Threshold
B-91 en FD_PeriodA (H) 01 Flicker Period for 60Hz

MCLK Freq. / Frame Width flicker
B-92 256 * FD_PeriodA (M) 06
120
B-93 FD_PeriodA (L) 3C
B-94 FD_PeriodB (H) 01 Flicker Period for 50Hz

MCLK Freq. / Frame Width flicker
B-95 256 * FD_PeriodB (M) 3A
fid
100
B-96 FD_PeriodB (L) AF
B-97 MCLK Freq.

F / Frame
F Wid h
Width FD PeriodC (H)
FD_PeriodC 06 Period (line) for 20Hz
B-98 20 FD_PeriodC (M) 25
Reg. Addr. (Hex) Setting Value (Hex) Register Name Default Value Descriptions
on
(Hex)
B-76 C0 FdControl02 00 50Hz / 60Hz flicker

Auto Detection
- Flicker Detection Control Registers Setting

ex) Frame Width = Frame Width (Reg A-06h,A-07h) + 1 = 858d, MCLK = 27MHz, NTSC
C
(1) FD_PeriodA (60Hz flicker) = 256*(27000000 / 858) / (60*2) = 67132d = 1063Ch.

Æ FD_PeriodA (H) = 01h, FD_PeriodA (M) = 06h, FD_PeriodA (L) = 3Ch.
(2) FD_PeriodB
FD PeriodB (50Hz flicker) = 256
256*(27000000
(27000000 / 858) / (50*2)
(50 2) = 80559d = 13AAFh.
Æ FD_PeriodB (H) = 01h, FD_PeriodB (M) = 3Ah, FD_PeriodB (L) = AFh
(3) FD_PeriodC = (27000000 / 858) / 20 = 1573d = 625h.
Æ FD_PeriodC (H) = 06h, FD_PeriodC (M) = 25h
(4) Reg.B-89h ~ 8Ah = 256*256*4 / FD_PeriodA(H) = 256*256*4 / 262= 1000d = 3E8h
Æ Reg.B-89h = 03h, Reg.B-8Ah = E8h
(5) Reg.A-8Bh ~ 8Ch = 256*256*4 / FD_PeriodB(H) = 256*256*4 / 314 = 834d = 342h
Æ Reg.B-8Bh = 03h, Reg.B-8Ch = 42h
*) Frame Width Value - NTSC - 0359h (857d), PAL - 040Dh (1037d)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- AE Control
(1) Internal AE Control
Related Registers : Int.Time(Reg.A-21h
Int Time(Reg A 21h ~ A-26h),
A 26h) GlobalGain(Reg
GlobalGain(Reg.A-1Ah,
A 1Ah A-1Bh),
A 1Bh) AutoControl1(Reg.C-04h),
AutoControl1(Reg C 04h)
MidFrmHeight(Reg.C-12h, C-13h), MaxFrmHeight(Reg.C-14h, C-15h), MidExp(Reg.C-19h ~
C-1Bh), MaxExp (Reg.C-1Ch ~ C-1Eh), MinExp(Reg.C-16 ~ C-18h), ExpFrmHeight(Reg.C-10
~11h), AELock(Reg.C-28h)
l
tia
If AEr bits of AutoControl1(Reg.C-04h)
( g ) register
g is set to “00”,, IntTime(Reg.A-21
( g h ~ A-26h),), GlbGain(Reg.A-
( g
1Ah, A-1Bh) registers are automatically controlled by ISP to adjust overall brightness of sensor image. During
auto exposure process, the average brightness of image is adjusted to get close to Target Exp. value with the
margin set by AELock(Reg.C-28h) register. IntTime registers are controlled, at first. If Integration Line is limited
to the MaxFrmHeight(Reg.C-14h, C-15h), then Global Gain is controlled. Variation of GlbGain and IntTime
Bright IntTime => 0

en
registers are limited by MaxExp, MidExp, MinExp and MaxFrameHeight registers described in the figure below.
IntTime => MinExp, GlobalGain => 1X

fid
Int.Line control range (Frame rate is fixed to Max.Frame Rate .)
IntTime => FrameHeight , GlobalGain => 1X

on
Auto gain control range (Frame rate is fixed to Max.Frame Rate and
Global Gain is controlled.)
IntTime => FrameHeight, GlobalGain => ( MidFrmHeight / ExpFrmHeight ) X

C
Auto frame control range (Frame rate is changed.)
IntTime => MaxFrmHeight / (MidFrmHeight / ExpFrmHeight),

GlobalGain => ( MidExp/ExpFrameHeight ) X
Auto gain control range (Frame rate is fixed to Min.Frame Rate and
Global Gain is controlled.)
IntTime => MaxFrmHeight / (MidFrmHeight / ExpFrmHeight),

Dark
GlobalGain => (MidExp / (MaxFrmHeight / (MidFrmHeight / ExpFrmHeight)) ) X

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
Auto Frame Control Method can be used to get brighter image in dark condition. Frame rate is automatically
controlled by ISP between Max.Frame Rate and Min.Frame Rate.
Max. Frame Rate = (MCLK frequency) / (Frame Height * Frame Width * 2)
Min. Frame Rate
= (MCLK frequency) / ((MaxFrmHeight / Mid. Global Gain)* Frame Width * 2)
l
Max. Int. Time = MaxFrmHeight / Mid. Global Gain ------ (1)
tia
Min. Int. Time = MinExposure ------ (2)
( Frame Height = FrameHeight + 1, Frame Width = FrameWidth + 1 )

Min. Frame Rate is controlled by MaxFrmHeight register. MaxFrmHeight must be bigger than ExpFrmHeight and
MidFrmHeight.( MaxFrmHeight >= MidFrmHeight >= ExpFrmHeight )
2) Auto Gain Control
en
Auto Gain Control Method can be used to get brighter image in dark condition. Global gain is controlled
automatically by ISP between Max.Global Gain and Min.Global Gain.
Max. Gain = Max. Global Gain * Max. Digital Gain
Max. Digital Gain = (MaxExp / (Max. Global Gain * Max. Int. Time)) X ------ (3)
Max. Global Gain = (MidExp / Max. Int. Time) X ------- (4)
fid
Mid. Global Gain = (MidFrmHeight / ExpFrmHeight) X ------ (5)
Min. Global Gain = 1X ------ (6)
MaxExp must be bigger than MaxFrmHeight. (MaxExp >= MaxFrmHeight) and MidFrmHeight must be bigger
than MaxFrmHeight (MidFrmHeight >= MaxFrmHeight).
Digital Gain
on
(3)
Global Gain
C
(4)
(5)
(6)
Int. Time
(1)
(2)
Exp.Frame Max.Frame Max.

Height Height Exposure
Min. Mid.Frame Mid.
Exposure Height Exposure

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
(2) External AE Control

1) Exposure Control Mode
Related Registers : AutoControl1 (Reg.C-04h), Exposure (Reg.C-0Ch ~ C-0Fh)
If you turn off internal AE function of PC1030N, you can control Integration line and Global gain through
Exposure (Reg.C-0Ch ~ C-0Fh) registers for implementing external Auto Exposure function. IntTime (Reg.A-21h ~
l
A-26h) and GlobalGain (Reg.A-1Ah, A-1Bh) registers aren’t accessible by user. Exposure (Reg.C-0Ch ~ C-0Fh)
tia
registers aren’t controllable while internal AE is working.
- Disable Internal AE Function for This Mode
Reg. Addr. (Hex) Register Name Descriptions
C-04
C-26
AutoControl1
AEUpSpeed
en
Set Bit 1 & 0 (AEr) to “01” to turn off internal AE function and control it by Exposure
registers.
Set this register to 00h
C-27 AEDownSpeed Set this register to 00h

fid
- Registers for External AE Control
R
Reg. Add (Hex)
Addr. (H ) R i t Name
Register N D
Descriptions
i ti
C-0C Exposure(T) Exposure register
C-0D Exposure(H)
on
C-0E Exposure(M)
C-0F Exposure(L)
(1) MinExp < Exposure ≤ FrameHeight ( Int.Line Control Range )

C
(2) FrmHeight < Exposure ≤ MidExp ( Global Gain Control Range )

(3) FrameHeight < Exposure ≤ MaxFrmHeight ( Frame Rate Control Range )
Current Frame Rate = ((MCLK freq.)
q ) / ((Exposure
p g )) * Frame Width * 2))
– ((MidExpp + FrameHeight))
Min. Frame Rate is limited by MaxFrmHeight.
(4) MaxFrmHeight < Exposure ≤ MaxExp ( Global Gain Control Range )
Current Global Gain = (MidExp / FrameHeight) * (Exposure / MaxFrmHeight) X

Max.Gain is limited by MaxExp.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
2) Manual External IntTime and Global Gain Control Mode
Related Registers : AutoControl1 (Reg.C-04h), ExtIntTime (Reg.C-07h ~ 09h), ExtLGlbG (Reg.C-0Ah, C-0Bh)
If you turn off internal AE function of PC1030N, you can control Integration line and Global gain through
ExtIntTime (Reg.C-07h ~ C-09h) and ExtGlbG (Reg.C-0Ah, C-0Bh) registers for implementing external Auto
Exposure function. IntTime (Reg.A-21h ~ A-26h) and GlobalGain (Reg.A-1Ah, A-1Bh) registers aren’t accessible
by user. ExtIntTime (Reg.C-07h ~ C-09h) and ExtGlbG (Reg.C-0Ah, C-0Bh) registers aren’t controllable while
l
internal AE is working.
tia
- Disable Internal AE Function for This Mode
C-04 AutoControl1 Set bit 1& 0 (AEr) to “10” to turn off internal AE function & control it by External
C-26
C-27
AEUpSpeed
AEDownSpeed
en
Int.Time & External Global Gain.
- Registers for External AE Control

fid
C-07
C 07 ExtIntTime(H) External Integration Time
C-08 ExtIntTime(M)
C-09 ExtIntTime(L)
on
C-0A ExtLGlbG(H) External Global Gain ( 1X : Reg.C-0Ah = 01h, Reg.C-0Bh = 00h (Min.)
16X : Reg.C-0Ah = 10h, Reg.C-0Bh = 00h (Max.) )
C-0B ExtLGlbG(L)
(1) IntTime = ExtIntTime
(2) ExtLGlbG
C
GlobalGain
40h
…
30h
20h
10h
… ExtGlbG
1.0 2.0 4.0 8.0 16.0

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- AWB Control
(1) Internal AWB Control
Related Registers : RGain(Reg.A-27h), GGain(Reg.A-28h), BGain(Reg.A-29h), AWBRratio(Reg.C-A4h),
AWBBratio(Reg.C-A5h),
If WU of AutoControl1(Reg.C-04h) register is set to ‘1’, RGain(Reg.A-27h) and BGain(Reg.A-29h) registers
l
are automatically controlled by ISP to control the RGB ratio of sensor image. The ratio of average of R, G, B
tia
components can be controlled by AWBRratio and AWBBratio registers. Those ratios are defined according to
the following relation,
relation
AWBBratio AWBRratio
B = x G R = x G
(2) External AWB Control

128 en 128
If you turn off internal AWB function of PC1030N, you can control R, G and B gains through R, G and B Gain
(Reg.A-27h ~ A-29h) registers for implementing external Auto White Balance function. R and B gain registers
aren’t controllable while internal AWB is working.
fid
- Disable Internal AWB Function
C-04 AutoControl1 Set Bit 3(AWBr) to ‘0’ to turn off internal AWB function.
on
- Registers for external AWB control
Reg Addr.
Reg. Addr (Hex) Register Name Default Value (Hex) Descriptions
A-27 R Gain 40 1X R Gain = 0x40 ( 2X = 0x80 )
A-28 G Gain 40 1X G1 Gain = 0x40

C
A-29 B Gain 40 1X B Gain = 0x40

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Backlight Compensation
Related Registers : AECenterWinX (Reg.C-56h, C-57h), AECenterWinY (Reg.C-58h, C-59h),
AECenterWinWidth ((Reg.C-5Ah,
g 5Bh),
) AECenterWinHeight
g (Reg.C-5Ch,
( g 5Dh),
) AECenterWeight
g (Reg.C-25h)
( g )
1) Weight Window
l
Reg. Addr. (Hex) Register Name Default Value (Hex) Description
tia
C-56 AECenterWinX (H) 00 Minimum :
( g
WindowX1(Reg.A-0Ah, A-0Bh))
C-57 AECenterWinX (L) D2
C-58 AECenterWinY (H) 00 Maximum :

WindowX2(Reg.A-0Eh, A-0Fh)
C-59 AECenterWinY (L) UU
C-5A
C-5B
C-5C
AECenterWinWidth (H)
AECenterWinWidth(L)
( )
AECenterWinHeight (H)
en 00
C8
00
Minimum :
WindowY1(Reg.A-0Ch, A-0Dh)
Maximum:
WindowY2(Reg.A-10h, A-11h)
C-5D AECenterWinHeight (L) UU
fid
(WindowX1, WindowY1)
(AECenterWinX, AECenterWinY)
on
(AECenterWinX + AECenterWinWidth,
AEC t Wi Y + AECenterWinHeight)
AECenterWinY AEC t Wi H i ht)
(WindowX2, WindowY2)
Window size is different according to output mode(NTSC:640x240, PAL:640x288).

C
Therefore user should set AE center window size consider window size.
2) Weight Factor
Weight Factor is controlled by AECenterWeight register (Reg.C-25h).
0000b ≤ Weight Factor ≤ 1111b

Min. Max.
0000b ( 0X ) 1000b (8X) 1111b (15X)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Brightness / Y Contrast
-Related Registers : Brightness (Reg.B-25h), YContrast (Reg.B-24h)
Y reault = Y * (Ycontrast / 64) + Brightness
l
tia
(1) Brightness
Brightness is controlled by Brightness register (Reg.B-25h). The default value of this register is 01h.
Min. Default. Max.
80h (-128)
*B
Brightness
i ht
(2) Y Contrast
: 2’s
2’ compliment
li t
en 01h (1) 7Fh (+127)
fid
Contrast is controlled by Y Contrast register (Reg.B-24h). The default value of this register is 40h.
Min. Default. Max.
00h 40h FFh

on
C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Color Correction Matrix
Related Registers : ColorMatrix11 (Reg.C-B9h) ~ ColorMatrix33 (Reg.C-C1h)
Color correction can be accomplished by color transform registers (Reg.C-B9h ~ C-C1h) by means of the
following equation, where CC is 3x3 color correction matrix.
l
CT0 CT1 CT2 = m00 m01 m02 = 32 *CC
tia
CT3 CT4 CT5 m10 m11 m12
CT6 CT7 CT8 m20 m21 m22
* m00 ~ m22 : (bit7) | (bit6 ~ bit0) = sign digit | magnitude
<Ex.>
m00 m01 m02 = 32 *

en 1 7396
1.7396 -1 1444
-1.1444 0 4048
0.4048
m10 m11 m12 -0.6039 1.4137 0.1902
m20 m21 m22 -0.1025 -1.3094 2.4119

fid
= 55.6672 -36.6208 12.9536 = 38h A5h 0Dh
-19.3248 45.2384 6.0864 93h 2Dh 06h
-3.28 -41.9008 77.1808 83h AAh 4Dh

on
- Sharpness Control
Related Registers : EdgeGain (Reg.B-2Eh), EdgeThreshold (Reg.B-2Fh)
Sharpness is controlled by EdgeGain (Reg.B-2Eh) and EdgeThreshold register (Reg.B-2Fh). All three values
C
have the following Min. and Max. value.
00h ≤ EdgeGain
Ed G i ≤ 3Fh
00h ≤ EdgeThreshold ≤ FFh
The lowest sharpness level can be gotten by setting registers as follows.

EdgeGain = 00h, EdgeThreshold = FFh
And, the highest sharpness level can be gotten by setting registers as follows.
EdgeGain = 3Fh, EdgeThreshold = 00h
But, we recommend to set EdgeThreshold register value greater than 01h.

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Vertical / Horizontal Mirror
Related Registers : Mirror(Reg.A-05h), SyncControl0(Reg.B-0Bh). Related Strap pin : D6,D7.
Mi
Mirror mode
d can bbe sett bby nott only
l writing
iti registers
i t di directly
tl but
b t also
l controlling
t lli by b strap
t pin
i as D6
D6,D7.
D7
Strap setting can be ignored after register setting has been changed by EEPROM and external i2c master.
l
(1) Vertical Mirror
tia
Vertical Mirror is controlled by VM bit (Bit 1 of Reg.A-05h).
Set SD bits to ‘1’ (Bit 6 & 5 of Reg.B-0Bh)

Set VM bit to ‘1’ or ‘0’ (Bit 1 of Reg.A-05h)
en
Wait 1 (preview) frame time

fid
(2) Horizontal Mirror

Horizontal Mirror is controlled by HM bit (Bit 0 of Reg.A-05h).

on
Set HM bit to ‘1’ or ‘0’ (Bit 0 of Reg.A-05h)
Wait 1 (preview) frame time

C

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
- Special Effect
(1) Color Effect
Related Registers : ISPControl2 (Reg.B-06h),
(Reg B 06h) CbTone (Reg.B-27h),
(Reg B 27h) CrTone (Reg.B-28h)
(Reg B 28h)
l
Reg. Addr. (Hex) Setting value (Hex) Register Name Default Value (Hex) Descriptions
tia
B-06 81 ISPControl2 60
B 27
B-27 A
Appropriate
i Value
V l CbT
CbTone C0
B-28 Appropriate Value CrTone 40
en
fid
on
Sepia (Reg.B-27h : A0h, Reg.B-28h : 20h) Green (Reg.B-27h : C0h, Reg.B-28h : C0h)
C
Aqua (Reg.B-27h : 20h, Reg.B-28h : C0h) Red (Reg.B-27h : 00h, Reg.B-28h : 50h)

PC1030N
1/4 iinch
h VGA class
l Analog/Digital
A l /Di it l Output
O t t
l
tia
Cool (Reg.B-27h : 50h, Reg.B-28h : C0h) Warm (Reg.B-27h : 90h, Reg.B-28h : 30h)
en
fid
on
BW (Reg.B-27h : 00h, Reg.B-28h : 00h) Antique (Reg.B-27h : 90h, Reg.B-28h : 10h)

C

Pixelplus-Pc1030n C11168

Uploaded by

Copyright:

Available Formats

Pixelplus-Pc1030n C11168

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Pixelplus-Pc1030n C11168

Uploaded by

Copyright:

Available Formats

Data sheet

1/4 inch VGA class Analog/Digital Output

Last update : 22 . Sep. 2009

6th Floor, Gyeonggi R&DB Center, 906-5 Iui-dong, Yeongtong-gu,

Version Date [D/M/Y] Notes Writer

1.0 21/05/2009 Add Application note Jongwu Ryu

Change(SCLK Æ SSCLK, SDAT Æ SSDAT,

Modify Fig number. Page 13,14,15,18,19

PD-701-028 Rev 0.7 2/96 CrystalImage & ImagingInnovation

▶ Features (3) 640x480 VGA Digital Output Only

- [ Fig. 1 ] PIN Description - [Fig.10] Timing diagram for Hsync, MCLK,

- [ Table 1 ] Typical Parameters PCLK and Data ( Default : YUV )

▶ Signal Environment ▶ NTSC/PAL wire-strapping

- [ Fig. 4 ] Bayer Color Filter Pattern

▶ 2-wire Serial Interface Functional Description

(1) ITU-R BT656

- [ Fig. 8 ] Timing diagram for Hsync, MCLK,

PD-701-028 Rev 0.7 3/96 CrystalImage & ImagingInnovation

▷ Image processing on chip :

and back light compensation.

▷ VGA / QVGA / QQVGA / CIF / QCIF Scaling.

Dynamic Range 63.5 [dB] @60’C

SNR 45.6 [dB] @60’C

[ Table 1 ] Typical Parameters

PD-701-028 Rev 0.7 4/96 CrystalImage & ImagingInnovation

▶ PIN Descriptions [ Table 2 ] Pin Descriptions

PIN Name I/O Functions / Descriptions

9 AGND P Analog Power ground

13 CN O Connect 37.5ohm to AGND

14 AVDD1 P Analog Power supply : 2.8V DC with 0.1uF capacitor to AGND.

15 AGND1 P Analog Power ground

19 D0 O Bit 0 of parallel data output.

20 D1 O Bit 1 of parallel data output.

21 D2 O Bit 2 of parallel data output.

22 D3 O Bit 3 of parallel data output.

23 X1 I Master clock input pad or Crystal input pad

PD-701-028 Rev 0.7 5/96 CrystalImage & ImagingInnovation

PIN Name I/O Functions / Descriptions

33 HVDD P I/O Power supply: 2.8~3.3V DC with 0.1uF capacitor to HGND.

40 D5 O Bit 5 of parallel data output.

PD-701-028 Rev 0.7 6/96 CrystalImage & ImagingInnovation

Analog Control signal

Column decoder SSCLK/RSCLK

Digital Control signal Encoder & composite

[ Fig. 2 ] Block Diagram

PD-701-028 Rev 0.7 7/96 CrystalImage & ImagingInnovation

▶ Frame Structure and Windowing

480 Effective pixel

(857,524) Dummy pixel

[ Fig. 3 ] Default data structure of frame and window. ( Top view )

PD-701-028 Rev 0.7 8/96 CrystalImage & ImagingInnovation

▶ Digital Data Formats

Pixel array is covered by Bayer color filters as can be seen in

Cb = -0.148R – 0.291G + 0.439, Cr = 0.439R -0.368G – 0.071B

PD-701-028 Rev 0.7 9/96 CrystalImage & ImagingInnovation

▶ Data and Synchronization Timing

(1) ITU-R BT656 ( CCIR656 )

ITU-R BT. 601

ITU-R BT. 656