I.J.

Information Engineering and Electronic Business, 2014, 1, 1-14

Published Online February 2014 in MECS (http://www.mecs-press.org/)
DOI: 10.5815/ijieeb.2014.01.01

Design of FPGA based 32-bit Floating Point

Arithmetic Unit and verification of its VHDL
code using MATLAB
Naresh Grover, M.K.Soni
Faculty of Engineering and Technology, Manav Rachna International University, Faridabad, India
[email protected], [email protected]

Abstract — Most of the algorithms implemented in hardware arithmetic units because of their high
FPGAs used to be fixed-point. Floating-point operations integration density, low price, high performance and
are useful for computations involving large dynamic flexible applications requirements for high precious
range, but they require significantly more resources than operation.
integer operations. With the current trends in system Floating-point implementation on FPGAs has been
requirements and available FPGAs, floating-point the interest of many researchers. The use of custom
implementations are becoming more common and floating-point formats in FPGAs has been investigated
designers are increasingly taking advantage of FPGAs in a long series of work [1, 2, 3, 4, 5]. In most of the
as a platform for floating-point implementations. The cases, these formats are shown to be adequate for some
rapid advance in Field-Programmable Gate Array applications that require significantly less area to
(FPGA) technology makes such devices increasingly implement than IEEE formats [6] and to run
attractive for implementing floating-point arithmetic. significantly faster than IEEE formats. Moreover, these
Compared to Application Specific Integrated Circuits, efforts demonstrate that such customized formats enable
FPGAs offer reduced development time and costs. significant speedups for certain chosen applications. The
Moreover, their flexibility enables field upgrade and earliest work on IEEE floating-point [7] focused on
adaptation of hardware to run-time conditions. A 32 bit single precision although found to be feasible but it was
floating point arithmetic unit with IEEE 754 Standard extremely slow. Eventually, it was demonstrated [8] that
has been designed using VHDL code and all operations while FPGAs were uncompetitive with CPUs in terms
of addition, subtraction, multiplication and division are of peak FLOPs, they could provide competitive
tested on Xilinx. Thereafter, Simulink model in MAT sustained floating-point performance. Since then, a
lab has been created for verification of VHDL code of variety of work [2, 5, 9, 10] has demonstrated the
that Floating Point Arithmetic Unit in Modelsim. growing feasibility of IEEE compliant, single precision
floating point arithmetic and other floating-point
Index Terms — Floating Point, Arithmetic Unit, VHDL, formats of approximately same complexity. In [2, 5], the
Modelsim, Simulink. details of the floating-point format are varied to
optimize performance. The specific issues of
implementing floating-point division in FPGAs have
1. Introduction been studied [10]. Early implementations either
involved multiple FPGAs for implementing IEEE 754
The floating point operations have found intensive single precision floating-point arithmetic, or they
applications in the various fields for the requirements adopted custom data formats to enable a single-FPGA
for high precious operation due to its great dynamic solution. To overcome device size restriction,
range, high precision and easy operation rules. High subsequent single-FPGA implementations of IEEE 754
attention has been paid on the design and research of the standard employed serial arithmetic or avoided features,
floating point processing units. With the increasing such as supporting gradual underflow, which are
requirements for the floating point operations for the expensive to implement.
high-speed data signal processing and the scientific In this paper, a high-speed IEEE754-compliant 32-bit
operation, the requirements for the high-speed hardware floating point arithmetic unit designed using VHDL
floating point arithmetic units have become more and code has been presented and all operations of addition,
more exigent. The implementation of the floating point subtraction, multiplication and division got tested on
arithmetic has been very easy and convenient in the Xilinx and verified successfully. Thereafter, the new
floating point high level languages, but the feature of creating Simulink model using MAT lab for
implementation of the arithmetic by hardware has been verification of VHDL code of that 32-bit Floating Point
very difficult. With the development of the very large Arithmetic Unit in Modelsim has been explained. The
scale integration (VLSI) technology, a kind of devices simulation results of addition, subtraction,
like Field Programmable Gate Arrays (FPGAs) have multiplication and division in Modelsim wave window
become the best options for implementing floating

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
2 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

have been demonstrated. and smaller than 255, and there is 1 in the MSB of the
The rest of the paper is organized as follows. Section significand then the number is said to be a normalized
2 presents the general floating point architecture. number; in this case the real number is represented by (1)
Section 3 explains the algorithms used to write VHDL
codes for implementing 32 bit floating point arithmetic V = (-1s) * 2 (E - Bias) * (1.M) (1)
operations: addition/subtraction, multiplication and
division. The Section 4 of the paper details the VHDL Where M = m22 2-1 + m21 2-2 + m20 2-3+…+ m1 2-
22
code and behaviour model for all above stated +m0 2-23; Bias = 127.
arithmetic operation. The section 5 explains the design
steps along with experimental method to create
Simulink model in MAT lab for verification of VHDL 3. Algorithms for Floating Point Arithmetic Unit
code in Modelsim and the results are shown and
discussed in its section 6 while section 7 concludes the The algorithms using flow charts for floating point
paper with further scope of work. addition/subtraction, multiplication and division have
been described in this section, that become the base for
writing VHDL codes for implementation of 32-bit
2. Floating Point Architecture floating point arithmetic unit.
3.1 Floating Point Addition / Subtraction
Floating point numbers are one possible way of
representing real numbers in binary format; the IEEE The algorithm for floating point addition is explained
754 [11] standard presents two different floating point through flow chart in Figure 2. While adding the two
formats, Binary interchange format and Decimal floating point numbers, two cases may arise. Case I:
interchange format. This paper focuses only on single when both the numbers are of same sign i.e. when both
precision normalized binary interchange format. Figure the numbers are either +ve or –ve. In this case MSB of
1 shows the IEEE 754 single precision binary format both the numbers are either 1 or 0. Case II: when both
representation; it consists of a one bit sign (S), an eight the numbers are of different sign i.e. when one number
bit exponent (E), and a twenty three bit fraction (M) or is +ve and other number is –ve. In this case the MSB of
Mantissa. one number is 1 and other is 0.
32 bit Single Precision Floating Point Numbers IEEE
standard are stored as: Case I: - When both numbers are of same sign
S EEEEEEEE MMMMMMMMMMMMMMMMMMMMMM Step 1:- Enter two numbers N1 and N2. E1, S1 and E1,
S: Sign – 1 bit S2 represent exponent and significand of N1 and N2
E: Exponent – 8 bits respectively.
M: Mantissa – 23 bits Fraction Step 2:- Is E1 or E2 =‟0‟. If yes; set hidden bit of N1 or
N2 is zero. If not; then check if E2 > E1, if yes swap N1
Sign bit
8 bits 23 bits
and N2 and if E1 > E2; contents of N1 and N2 need not
to be swapped.
Biased exponent Significand Step 3:- Calculate difference in exponents d=E1-E2. If d
= „0‟ then there is no need of shifting the significand. If
32 bits d is more than „0‟ say „y‟ then shift S2 to the right by an
amount „y‟ and fill the left most bits by zero. Shifting is
Figure.1: IEEE 754 single precision binary format representation
done with hidden bit.
The value of number V: Step 4:- Amount of shifting i.e. „y‟ is added to exponent
of N2 value. New exponent value of E2= (previous E2)
If E=255 and F is nonzero, then V= Nan ("Not a + „y‟. Now result is in normalize form because E1 = E2.
Number")
Step 5:- Check if N1 and N2 have different sign, if „no‟;
If E=255 and F is zero and S is 1, then V= - Infinity Step 6:- Add the significands of 24 bits each including
If E=255 and F is zero and S is 0, then V= Infinity hidden bit S=S1+S2.
Step 7:- Check if there is carry out in significand
If 0<E<255 then V= (-1) **S * 2 ** (E-127) * (1.F)
addition. If yes; then add „1‟ to the exponent value of
(exponent range = -127 to +128)
either E1 or new E2. After addition, shift the overall
If E=0 and F is nonzero, then V= (-1) **S * 2 ** (-126) result of significand addition to the right by one by
* (0.F) ("un-normalized" values”) making MSB of S as „1‟ and dropping LSB of
significand.
If E=0 and F is zero and S is 1, then V= - 0
If E=0 and M is zero and S is 0, then V = 0 Step 8:- If there is no carry out in step 6, then previous
exponent is the real exponent.
An extra bit is added to the mantissa to form what is Step 9:- Sign of the result i.e. MSB = MSB of either N1
called the significand. If the exponent is greater than 0 or N2.

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 3
using MATLAB

Step 10:- Assemble result into 32 bit format excluding result to left until there is „1‟ in MSB and also count the
24th bit of significand i.e. hidden bit. amount of shifting say „z‟.
Case II: - When both numbers are of different sign Step 8:- Subtract „z‟ from exponent value either from E1
or E2. Now the original exponent is E1-„z‟. Also append
Step 1, 2, 3 & 4 are same as done in case I. the „z‟ amount of zeros at LSB.
Step 5:- Check if N1 and N2 have different sign, if Step 9:- If there is no carry out in step 6 then MSB must
„Yes‟; be „1‟ and in this case simply replace „S‟ by 2‟s
Step 6:- Take 2‟s complement of S2 and then add it to complement.
S1 i.e. S=S1+ (2‟s complement of S2). Step 10:- Sign of the result i.e. MSB = Sign of the larger
Step 7:- Check if there is carry out in significand number either MSB of N1or it can be MSB of N2.
addition. If yes; then discard the carry and also shift the Step 11:- Assemble result into 32 bit format excluding
24th bit of significand i.e. hidden bit.

Start

Enter N1 and N2 in
Floating Format

Yes Set S23 =0 of N1 or

Is E1 or E2=0
N2 i.e. hidden bit

No
Yes
Is E1 or E2=0 Swap N1 and N2

Calculate Difference d=E1-E2

Shift S2 of N2 to right by amount ‘d’ and fill left most

bit by Zero’s. Shifting is done by Hidden Bit.

Amount of Shifting i.e. ‘d’ is added to the exponent of N2 .New

exponent of N2 =D+E2 {Expo N1=Expo N2}. Now result is in normalized
form

Yes No
Are N1 and N2
having different
sign?

Yes No
Replace S2 of N2 by 2’s Compute Significand
complement S=S1+S2
Compute Compute
Sign=Sign of Sign=Sign of N1
larger number or N2

Compute Significand Carry Out Carry Out No Carry Out

S=S1+S2

Discard Carry and shift the result to left Add 1 to Exponent and Previous
until there is ‘1’ at MSB fill least Also Shift overall result Exponent is the
No Carry Out significant bits by zero. Calculate to right dropping LSB real Exponent
amount of shifting say ‘x’ and making MSB ‘1’

If MSB is 1, Replace S by
2’s Complement,
Amount of Shifting is Subtracting from Exponent to produce original
otherwise keep S as such
exponent .Exponent of result =N1Expo/N2Expo-‘x’

Assemble Result into 32 bit format

Figure. 2: Flow Chart for floating point Addition/Subtraction

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
4 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

In this algorithm three 8-bit comparators, one 24-bit One swap unit is required to swap the numbers if N2
and two 8-bit adders, two 8-bit subtractors, two shift is greater than N1. Swapping is normally done by taking
units and one swap unit are required in the design. the third variable. Two shift units are required one is
First 8-bit comparator is used to compare the shift left and second is shift right.
exponent of two numbers. If exponents of two numbers
3.2 Floating Point Multiplication
are equal then there is no need of shifting. Second 8-bit
comparator compares exponent with zero. If the The algorithm for floating point multiplication is
exponent of any number is zero set the hidden bit of that explained through flow chart in Figure 3. Let N1 and N2
number zero. Third comparator is required to check are normalized operands represented by S1, M1, E1 and
whether the exponent of number 2 is greater than S2, M2, E2 as their respective sign bit, mantissa
number 1. If the exponent of number 2 is greater than (significand) and exponent. Basically following four
number 1 then the numbers are swapped. steps are used for floating point multiplication.
One subtractor is required to compute the difference 1. Multiply signifcands, add exponents, and determine
between the 8-bit exponents of two numbers. Second sign
subtractor is used if both the numbers are of different M=M1*M2
sign than after addition of the significands of two E=E1+E2-Bias
numbers if carry appears. This carry is subtracted from S=S1XORS2
the exponent using 8-bit subtractor. 2. Normalize Mantissa M (Shift left or right by 1) and
One 24-bit adder is required to add the 24-bit update exponent E
significands of two numbers. One 8-bit adder is required
3. Rounding the result to fit in the available bits
if both the numbers are of same sign than after addition
of the significands of two numbers if carry appears. This 4. Determine exception flags and special values for
carry is added to the exponent using 8-bit adder. Second overflow and underflow.
8-bit adder is used to add the amount of shifting to the
exponent of smaller number.

Start

Enter N1 and N2 in
Floating Format
Compute Sign
S=S1 XOR S2

Add E1 from E2 i.e.

E=E1+E2-Bias

Multiply M1 and M2
i.e. M=M1*M2

Yes No
Set Exponent E for Is M=0
zero

Yes Check if M No
overflows

Right Shift M and

Set E=E+1 Yes Check if M No
is
normalized
Left Shift M and
Set E=E-1

Yes
Check if E
overflows

Set Indication for

No overflow

Assemble Result into 32 bit format with final S, M and E

Figure. 3: Flow Chart for floating point Multiplication

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 5
using MATLAB

Sign Bit Calculation: The result of multiplication is a must be between 1 and 254 otherwise the value is not a
negative sign if one of the multiplied numbers is of a normalized one .An overflow may occur while adding
negative value and that can be obtained by XORing the the two exponents or during normalization. Overflow
sign of two inputs. due to exponent addition can be compensated during
Exponent Addition is done through unsigned adder subtraction of the bias; resulting in a normal output
for adding the exponent of the first input to the exponent value (normal operation). An underflow may occur
of the second input and after that subtract the Bias (127) while subtracting the bias to form the intermediate
from the addition result (i.e. E1+E2 - Bias). The result exponent. If the intermediate exponent < 0 then it is an
of this stage can be called as intermediate exponent. underflow that can never be compensated; if the
Significand Multiplication is done for multiplying the intermediate exponent = 0 then it is an underflow that
unsigned significand and placing the decimal point in may be compensated during normalization by adding 1
the multiplication product. The result of significand to it .When an overflow occurs an overflow flag signal
multiplication can be called as intermediate product (IP). goes high and the result turns to ±Infinity (sign
The unsigned significand multiplication is done on 24 determined according to the sign of the floating point
bit. multiplier inputs). When an underflow occurs an
The result of the significand multiplication underflow flag signal goes high and the result turns to
(intermediate product) must be normalized to have a ±Zero (sign determined according to the sign of the
leading „1‟ just to the left of the decimal point (i.e. in floating point multiplier inputs).
the bit 46 in the intermediate product). Since the inputs
3.3 Floating Point Division
are normalized numbers then the intermediate product
has the leading one at bit 46 or 47. If the leading one is The algorithm for floating point multiplication is
at bit 46 (i.e. to the left of the decimal point) then the explained through flow chart in Figure 4. Let N1 and N2
intermediate product is already a normalized number are normalized operands represented by S1, M1, E1 and
and no shift is needed. If the leading one is at bit 47 then S2, M2, E2 as their respective sign bit, mantissa
the intermediate product is shifted to the right and the (significand) and exponent. If let us say we consider
exponent is incremented by 1. x=N1 and d=N2 and the final result q has been taken as
Overflow/underflow means that the result‟s exponent “x/d”. Again the following four steps are used for
is too large/small to be represented in the exponent field. floating point division.
The exponent of the result must be 8 bits in size, and
Start

Enter N1 and N2 in Floating

Format

Compute Sign S=S1

XOR S2
Subtract E2 from E1 i.e.
E=E1-E2

Divide M1 by M2 i.e.
M=M1/M2

Yes No
Set Exponent E for Is M=0
zero
Yes No
Check if M
overflows

Right Shift M and Set

E=E+1
Yes No
Check if M is
normalized

Left Shift M and

Set E=E-1

Yes
Check if E
overflows

No Set Indication for

overflow

Assemble Result q into 32 bit format with final S, M and E

Figure. 4: Flow Chart for floating point Division (q = x/d; N1=x and N2=d)

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
6 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

1. Divide signifcands, subtract exponents, and determine port(

sign
n1,n2:in std_logic_vector(32 downto 0);
M=M1/M2
E=E1-E2 clk:in std_logic;
S=S1XORS2 sum:out std_logic_vector(32 downto 0)
2. Normalize Mantissa M (Shift left or right by 1) and
update exponent E );
3. Rounding the result to fit in the available bits end component;
4. Determine exception flags and special values component fpm is
The sign bit calculation, mantissa division, exponent port(in1,in2:in std_logic_vector(31 downto 0);
subtraction (no need of bias subtraction here), rounding
the result to fit in the available bits and normalization is out1:out std_logic_vector(31 downto 0)
done in the similar way as has been described for );
multiplication.
end component;
signal out_fpa: std_logic_vector(32 downto 0);
4. VHDL Code
signal out_fpm,out_div: std_logic_vector(31 downto 0);
This section illustrates the main steps of VHDL code
that has been used to implement the 32-bit floating point signal in1_fpa,in2_fpa: std_logic_vector(32 downto 0);
arithmetic functions: addition/subtraction, multiplication begin
and division. It includes the arithmetic structure
followed by behavior model for different arithmetic in1_fpa<=in1&'0';
functions for 32-bit floating point format following in2_fpa<=in2&'0';
IEEE 754 standards.
fpa1:fpa_seq port map(in1_fpa,in2_fpa,clk,out_fpa);
fpm1:fpm port map(in1,in2,out_fpm);
ARITHMETIC UNIT STRUCTURE
fpd1:divider port map(clk,'0','1',in1,in2,out_div);
entity fp_alu is
process(sel,clk)
port(in1,in2:in std_logic_vector(31 downto 0);
begin
clk:in std_logic;
if(sel="01")then
sel:in std_logic_vector(1 downto 0);
output1<=out_fpa(32 downto 1);
output1:out std_logic_vector(31 downto 0));
elsif(sel="10")then
end fp_alu;
output1<=out_fpm;
architecture fp_alu_struct of fp_alu is
elsif(sel="11")then
component divider is
output1<=out_div;
port(
end if;
clk : in std_logic;
end process;
res : in std_logic;
end fp_alu_struct;
GO : in std_logic;
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0); FPA BEHAVIOUR
z : out std_logic_vector(31 downto 0); entity fpa_seq is
done : out std_logic; port(n1,n2:in std_logic_vector(32 downto 0);
overflow : out std_logic clk:in std_logic;
); sum:out std_logic_vector(32 downto 0));
end component; end fpa_seq;
component fpa_seq is architecture Behavioral of fpa_seq is

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 7
using MATLAB

--signal f1,f2:std_logic_vector(23 downto else

0):="000000000000000000000000";
s3:=s3;
signal sub_e:std_logic_vector(7 downto
-- end if;
0):="00000000";
---------------------same sign start
--signal addi:std_logic_vector(34 downto 0);
---------------adder 8 calling---------------
signal c_temp:std_logic:='0';--_vector(34 downto 0);
adder8(e2,d,e3);
signal shift_count1:integer:=0;
sub_e<=e3;
signal num2_temp2: std_logic_vector(32 downto
0):="000000000000000000000000000000000"; num1_temp:=n1(32)& e1 & s1;
signal s33:std_logic_vector(23 downto num2_temp:=n2(32)& e3 & s3;
0):="000000000000000000000000";
---------------adder 23 calling---------------
signal s2_temp :std_logic_vector(23 downto
0):="000000000000000000000000"; adder23(s1,s3,s4,c_out);

signal diff:std_logic_vector(7 downto 0):="00000000"; --s2_temp<=s4;

c_temp<=c_out;
----------sub calling---------------------------------------------
-------------------- if(c_out='1')then
sub(e1,e2,d); --shift1(s4,s_1,s5);
if(d>="00011100")then --s2_temp<=s5;
sum<=num1; s33<=s4;
elsif(d<"00011100")then s5:='1' & s4(23 downto 1);
shift_count:=conv_integer(d); s2_temp<=s5;
shift_count1<=shift_count; adder8(e3,"00000001",e4);
num2_temp2<=num2; e3:=e4;
--s2_temp<=s2; --sub_e<=e4;
--------------shifter calling------------------------------------- sum<=n1(32)& e3 & s5;
--------------------
else
shift(s2,shift_count,s3);
sum<=n1(32)& e3 & s4;
--s33<=s3;
end if;
------------sign bit checking------
end if;
if (num1(32)/=num2(32))then
end if;
s3:=(not(s3)+'1');------2's complement
end if;----same sign end
adder23(s1,s3,s4,c_out);
end if;
if(c_out='1')then
------final result assembling----------
shift_left(s4,d_shl,ss4);
--sum_temp<=n1(32)& e1 & s4;
sub(e1,d_shl,ee4);
--sum<=n1(32)& e3 & s4;
sum<=n1(32)& ee4 & ss4;
end process;
else
end Behavioral;
if(s4(23)='1')then
s4:=(not(s4)+'1');------2's complement
sum<=n1(32)& e1 & ss4; FPM BEHAVIOUR

end if; entity fpm is

end if; port(in1,in2:in std_logic_vector(31 downto 0);

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
8 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

out1:out std_logic_vector(31 downto 0)); --------------------------end multipier--------------------------

---------------------
end fpm;
begin
architecture Behavioral of fpm is
process(in1,in2)
procedure adder( a,b:in std_logic_vector(7 downto 0);
variable sign_f,sign_in1,sign_in2: std_logic:='0';
sout : out STD_LOGIC_VECTOR (8 downto
0))is variable e1,e2: std_logic_vector(7 downto
0):="00000000";
variable g,p:std_logic_vector(7 downto 0);
variable add_expo:std_logic_vector(8 downto
variable c:std_logic_vector(8 downto 0);
0):="000000000";
variable sout1 :STD_LOGIC_VECTOR (7 downto 0);
variable m1,m2: std_logic_vector(23 downto
begin 0):="000000000000000000000000";
c(0):='0'; variable mantisa_round: std_logic_vector(22 downto
0):="00000000000000000000000";
for i in 0 to 7 loop
variable prod:std_logic_vector(47 downto
g(i):= a(i) and b(i);
0):="00000000000000000000000000000000000000000
p(i):= a(i) xor b(i); 0000000";
end loop; variable mul_mantisa :std_logic_vector(47 downto
0):="00000000000000000000000000000000000000000
for i in 0 to 7 loop 0000000";
c(i+1):=(g(i) or (c(i) and p(i))); variable bias:std_logic_vector(8 downto
end loop; 0):="001111111";
for i in 0 to 7 loop variable bias_sub:std_logic_vector(7 downto
0):="00000000";
sout1(i):=c(i) xor a(i) xor b(i);
variable inc_bias:std_logic_vector(8 downto
end loop; 0):="000000000";
sout:=c(8) & sout1; variable bias_round:std_logic_vector(8 downto
end adder; 0):="000000000";
-------------------------------------------multiplier------------- begin
------------------ sign calculation
procedure multiplier ( a,b : in STD_LOGIC_VECTOR sign_in1:=in1(31);
(23 downto 0);
sign_in2:=in2(31);
y : out STD_LOGIC_VECTOR (47 downto 0))is
sign_f:=sign_in1 xor sign_in2;
variable temp,prod:std_logic_vector(47 downto 0);
begin
FPD BEHAVIOUR
temp:="000000000000000000000000"&a;
prod:="000000000000000000000000000000000000000 entity divider is
000000000"; port(
for i in 0 to 23 loop clk : in std_logic;
if b(i)='1' then res : in std_logic;
prod:=prod+temp; GO : in std_logic;
end if; x : in std_logic_vector(31 downto 0);
temp:=temp(46 downto 0)&'0'; y : in std_logic_vector(31 downto 0);
end loop; z : out std_logic_vector(31 downto 0);
y:=prod; done : out std_logic;
end multiplier;

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 9
using MATLAB

overflow : out std_logic z_mantissa <= (others => '0');

); z_exponent <= (others => '0');
end divider; EA <= (others => '0');
architecture design of divider is Q <= (others => '0');
signal x_reg : std_logic_vector(31 downto 0); B <= (others => '0');
signal y_reg : std_logic_vector(31 downto 0); overflow <= '0';
signal x_mantissa : std_logic_vector(23 downto 0); done <= '0';
signal y_mantissa : std_logic_vector(23 downto 0); else
signal z_mantissa : std_logic_vector(23 downto 0); case state is
signal x_exponent : std_logic_vector(7 downto 0); when reset => state <= idle;
signal y_exponent : std_logic_vector(7 downto 0); when idle =>
signal z_exponent : std_logic_vector(7 downto 0); if GO = '1' then
signal x_sign : std_logic; state <= s0;
signal y_sign : std_logic; x_reg <= x;
signal z_sign : std_logic; y_reg <= y;
signal sign : std_logic; end if;
signal SC : integer range 0 to 26; when s0 => state <= s1;
signal exp : std_logic_vector(9 downto 0); overflow <= '0';
signal EA : std_logic_vector(24 downto 0); SC <= 25;
signal B : std_logic_vector(23 downto 0); done <= '0';
signal Q : std_logic_vector(24 downto 0); sign <= x_sign xor y_sign;
type states is (reset, idle, s0, s1, s2, s3, s4); EA <= '0' & x_mantissa;
signal state : states; B <= y_mantissa;
begin Q <= (others => '0');
x_mantissa <= '1' & x_reg(22 downto 0); exp <= ("00" & x_exponent) + not ("00"
& y_exponent) + 1 + "0001111111";
x_exponent <= x_reg(30 downto 23);
when s1 => if (y_mantissa = x"800000" and
x_sign <= x_reg(31);
y_exponent = x"00") then
y_mantissa <= '1' & y_reg(22 downto 0);
overflow <= '1';
y_exponent <= y_reg(30 downto 23);
z_sign <= sign;
y_sign <= y_reg(31);
z_mantissa <= (others => '0');
process(clk)
z_exponent <= (others => '1');
begin
done <= '1';
if clk'event and clk = '1' then
state <= idle;
if res = '1' then
elsif exp(9) = '1' or exp(7 downto 0) = x"00" or
state <= reset; (x_exponent = x"00" and x_mantissa = x"00") or
(y_exponent = x"FF" and y_mantissa = x"00") then
exp <= (others => '0');
z_sign <= sign;
sign <= '0';
z_mantissa <= (others => '0');
x_reg <= (others => '0');
z_exponent <= (others => '0');
y_reg <= (others => '0');
done <= '1';
z_sign <= '0';

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
10 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

state <= idle; end if;

else when s4 => if exp = x"00" then
EA <= EA + ('0' & not B) + 1; z_sign <= sign;
state <= s2; z_mantissa <= (others => '0');
end if; z_exponent <= (others => '0');
when s2 => elsif exp(9 downto 8) = "01" then
if EA(24) = '1' then z_sign <= sign;
Q(0) <= '1'; z_mantissa <= (others => '0');
else z_exponent <= (others => '1');
Q(0) <= '0'; else
EA <= EA + B; z_sign <= sign;
end if; z_mantissa <= Q(24 downto 1);
SC <= SC - 1; z_exponent <= exp(7 downto 0);
state <= s3; end if;
when s3 => if SC = 0 then done <= '1';
if Q(24) = '0' then state <= idle;
Q <= Q (23 downto 0) & '0'; end case;
exp <= exp - 1; end if;
end if; end if;
state <= s4; end process;
else z <= z_sign & z_exponent & z_mantissa(22 downto 0);
EA <= EA(23 downto 0) & Q(24); end design;
Q <= Q(23 downto 0) & '0'; The VHDL code written has been tested and verified
on Xilinx ISE 8.1i for all operation. The design
state <= s1;
utilization summary has been shown in Figure 5.

Figure. 5: Design Utilization Summary of Floating Point Arithmetic Unit on FPGA

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 11
using MATLAB

5. Generation and verification of HDL code using

MATLAB
Generation and verification of HDL code using
MATLAB requires compatible versions of MATLAB
(Simulink) and HDL Simulator „Modelsim‟ to be loaded
on the same system [13, 14, 15]. The basic design steps
to create Simulink model for verification of VHDL code
in Modelsim HDL Simulator is shown in the flow chart
of Fig. 6.

Figure. 7: Simulink model to generate and verify Floating Point

arithmetic

Figure. 8: Simulink sub-system to launch HDL Simulator

6. RESULTS
Double clicking the „Launch HDL Simulator‟ in the
Simulink model loads the test bench for simulation. The
Figure. 6: Design steps to create Simulink model for verification of
VHDL code in Modelsim
ModelSim Simulator opens a display window for
monitoring the simulation as the test bench runs. The
The Simulink Model to generate and verify Floating wave window in Figure 9 shows the simulation of two
Point arithmetic created is shown in Figure 7. Input 1 exponential inputs and Select set to „01‟for „adder‟
and Input 2 are the two 32 bit floating point inputs to the result as HDL waveform. Figure 10 shows the
model and „Select‟ is set to „01‟ for Adder, „11‟ for simulation of two decimal inputs for „adder‟. Figure 11
Divider and „10‟ for Multiplier. It also has a scope to and 12 show the simulation of two decimal inputs for
view the output. A sub-system is created to launch the „divider‟. Figure 13 and 14 show the simulation of two
Modelsim Simulator from Simulink as shown in Fig. 8. decimal inputs for „multiplier‟.

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
12 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

Figure. 9: Simulation result of decimal inputs 1.1 & 1.1 for „adder‟ in Figure. 12: Simulation result of decimal inputs 2.5 & 4.75 for „divider‟
Modelsim wave window in Modelsim wave window

Figure. 10: Simulation result of decimal inputs 2.5 & 4.75 for „adder‟ Figure. 13: Simulation result of decimal inputs 1.1 & 1.1 for
in Modelsim wave window „multiplier‟ in Modelsim wave window

Figure. 11: Simulation result of decimal inputs 1.1 & 1.1 for „divider‟ Figure. 14: Simulation result of decimal inputs for 2.5 & 4.75
in Modelsim wave window „multiplier‟ in Modelsim wave window

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14
 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code 13
using MATLAB

Table-I below shows the input output details of the Floating point arithmetic architecture designed and linked using
Simulink and Modelsim.

Table I
Wave Select Input 1 Input 2 Output

Figure 9 01 32‟h3F8CCCCD 32‟h3F8CCCCD 32‟h404CCCCD

Figure 10 01 32‟h40200000 32‟h40980000 32‟h41440000

Figure 11 11 32‟h3F8CCCCD 32‟h3F8CCCCD 32‟h3F06BCA1

Figure 12 11 32‟h40200000 32‟h40980000 32‟h3F800000
Figure 13 10 32‟h3F8CCCCD 32‟h3F8CCCCD 32‟h3F9AE148
Figure 14 10 32‟h40200000 32‟h40980000 32‟h413E0000

7. Conclusion and Future Scope of Work Programmable Custom Computing Machines,

(Napa Valley, CA), pp. 185–194, April 2003.
The VHDL code written for complete 32-bit floating [6] IEEE Standards Board, “IEEE standard for binary
point arithmetic unit has been implemented and tested floating-point arithmetic,” Tech. Rep. ANSI/IEEE
on Xilinx. A process described to create Simulink model Std. 754-1985, The Institute of Electrical and
in MAT lab for verification of VHDL code in Modelsim Electronics Engineers, New York, 1985.
HDL Simulator has been used on the same VHDL code [7] B.Fagin and C. Renard, “Field programmable gate
and results were found in order. Once the Simulink arrays and floating point arithmetic,” IEEE
model has been created using MAT lab for VHDL code, Transactions on VLSI, vol. 2, no. 3, pp. 365–367,
the same can be optimized in MAT lab and the VHDL 1994.
code can be regenerated with the optimized results and [8] W. B. Ligon, S. P. McMillan, G. Monn, F. Stivers,
tested on Xilinx to see the improvement in the K. Schoonover, and K. D. Underwood, “A re-
parameters. evaluation of the praticality of floating-point on
FPGAs,” in Proceedings of the IEEE Symposium
on FPGAs for Custom Computing Machines,
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[1] N. Shirazi, A. Walters, and P. Athanas, [9] Z. Luo and M. Martonosi, “Accelerating pipelined
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14 Design of FPGA based 32-bit Floating Point Arithmetic Unit and verification of its VHDL code
using MATLAB

ACM New York, NY, USA ©2011 ISBN: 978-1-

4503-0449-8.
[15] Alejandro A. Valenzuela, Hikmat N. Abdullah. A
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Applications , 2011, pp 189-199.

Naresh Grover did his B.Sc (Engg.) in

1984 and M.Tech in Electronics and
Communication Engineering in 1998
from REC Kurukshetra (Now NIT
Kurukshetra). He has a rich experience
of 29 years in academics. He has
authored two books on
Microprocessors and is a co-author for a book on
Electronic Components and Materials. His core area of
interest is Microprocessors and Digital System Design.
Presently he is doing his research work in the area of
FPGA based digital system designs.

Dr. M. K Soni did his B.Sc (Engg.) in

1972 and M.Sc (Engg.) in 1975 from
REC Kurukshetra (Now NIT
Kurukshetra) and thereafter completed
his Ph.D from REC Kurukshetra (in
collaboration with IIT Delhi) in 1988.
He has a total 40 years of rich
experience into Academics. His area of interest is
microprocessor based control systems and digital
system design. He has more than 100 research papers in
the International and National Journals to his credit.
Presently he is Executive Director & Dean, Faculty of
Engineering and Technology, Manav Rachna
International University, Faridabad.

Copyright © 2014 MECS I.J. Information Engineering and Electronic Business, 2014, 1, 1-14