SystemVerilog

A Design & Synthesis Perspective

Karen Pieper
R&D Manager, HDL Compiler

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What is SystemVerilog?
Verification
Comprehensive
Testbench Assertions
APIs
Design
Communication Enhanced Concise Design Datatypes
Interfaces Verilog Features (C)
Verilog 2001
Verilog 1995

ƒ Speeds operations – 3-5X concise code

ƒ Unifying design verification – simplifies flow, teamwork
ƒ Evolution from Verilog – rapid incremental, adoption

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Concise Coding Constructs for Design
ƒ Interfaces – Define once, use many times
– Encapsulates communication between modules
– Can be designed/verified separately
– Supports multiple levels of abstraction – signal level,
transaction
ƒ Structures and user defined data types
– Improves data modeling, simplifies port lists
ƒ Assignment operators, array slices, etc.

Less code – Same synthesis results as Verilog

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Interfaces Capture Chip Infrastructure
interface chip_bus (input wire clk); CPU RAM
wire request, grant, ready; clk clk
wire [47:0] address; data data
wire [63:0] data; Connection details address address
are in the interface request request
endinterface grant grant
ready ready

module CPU (chip_bus io); chip_bus

...
endmodule Modules do not duplicate
connection detail

module RAM (chip_bus pins);

...
endmodule

module top; Netlists do not duplicate connection detail

wire clk;
chip_bus a(clk); //instantiate the interface
RAM mem(a); //connect interface to module instance
CPU cpu(a); //connect interface to module instance
endmodule

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More than Just a Bundle of Wires
– Declarations
• Variables, parameters and other data that is shared
– Tasks and functions
• Operations on the interface connections
– Always blocks
• Actions at the highest instantiation level of the bus
– Modports
• Specification of port directions
– Assertions
• Protocol checking and other verification
ƒ Allows simple replacement of a bus
– Serial to parallel, parallel to serial
ƒ Allows a single owner of bus description

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Interface Synthesis
ƒ Interfaces distribute hardware
– The appropriate contents of an interface are inlined in
modules using it
• Names are scoped appropriately
• Tasks and functions generate hardware at the callsite
– Embedded always blocks exist in the instantiating
module
– Changing an interface requires resynthesizing all
modules referring to that interface

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Structs and User Defined Data Types –
Improves Readability and Debug
Verilog SystemVerilog
module fifo (clk, rstp, din_src, Define Once
din_dst, din_data,readp,writep, typedef struct {
dout_src,dout_dst, dout_data, bit [7:0] src;
emptyp, fullp); bit [7:0] dst;
input clk; bit [31:0] data;
input rstp; } packet_t;
input bit [7:0] din_src;
input bit [7:0] din_dst;
input bit [31:0] din_data;
input readp; module fifo ( Use many times
input writep; input clk,
output bit [7:0] dout_src; input rstp;
output bit [7:0] dout_dst; input packet_t din,
output bit [31:0] dout_data; input readp;
output logic emptyp; input writep; Easy to
output logic fullp; output packet_t dout; read and
. output logic emptyp; debug
. output logic fullp
. );

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Type Synthesis
ƒ Most type extensions are straightforward
ƒ Structures
– Similar to synthesizing VHDL
– Unpacked arrays are preferred for synthesis
• Aliasing for packed arrays
ƒ Unions
– Support only packed unions for synthesis today
• Ensures a single interpretation independent of the
implementation
• Unpacked unions have no guarantee of alignment

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Additional Concise Structures
ƒ Port connections
ƒ Return, break, continue, do … while
ƒ Assignment operators
ƒ Multi-dimensional array slices

ƒ All have more verbose Verilog 2001

equivalents
ƒ All are synthesized today

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Unifying Design and Verification
ƒ Reducing the infamous “simulation synthesis
mismatch”
– Unique, priority
ƒ Ensuring that what was intended is what was
written
– Always_comb, always_latch, always_ff
ƒ Documenting and checking assumptions as the
design is coded
– Assertions

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Unique and Priority
ƒ Reduces simulation/synthesis mismatches
ƒ Unique is parallel_case and full_case
– Simulation error if there is more than one true
condition
– Simulation error if condition is not enumerated
ƒ Priority is the same as full_case
– Simulation error if condition is not enumerated
ƒ Apply to both case statements and if..else if
chains

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Always_* Forms
ƒ Always_comb -- represents combinational logic
– Simulation activation better matches synthesis activation
– Warning if latches or flip-flops are inferred
ƒ Always_latch -- represents latch logic
– Simulation activation better matches synthesis activation
– Warning if a latch is not present
ƒ Always_ff @(exp) -- represents flip-flop logic
– Limits always block to one activation
– Warning if a flip-flop is not present

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Synthesis QoR Impact
ƒ An example Verilog design rewritten using SV
constructs
– Typedefs
– Structures
– Interfaces
– Modports
– Always_* forms

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Synthesis QoR Verilog SystemVerilog

Levels of Logic 10.00 10.00

Critical Path Length 6.38 6.38
Critical Path Slack -6.38 -6.38
Total Negative Slack -701.23 -701.91
No. of Violating Paths 204.00 204.00
Hierarchical Cell Count 242 242
Leaf Cell Count 6261 6266
Combinational Area 10590 10590
Noncombinational Area 14903 14907
Net Area 0 0
Cell Area 25493 25497
Design Area 25493 25497
Overall Compile Time 105.60 105.67

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Summary
ƒ Migration to SystemVerilog is easy
– Verilog designs will largely work unchanged
ƒ SystemVerilog raises the abstraction level
improving productivity
– 3x to 5x code size reduction
– Better verification with synthesis
– Faster verification through tighter integration with
testbenches

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EDA and IP Suppliers:
ƒ For more information on SystemVerilog and
synthesis, join the SystemVerilog Catalyst
Program
ƒ www.synopsys.com/partners/systemverilog

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