SEC5203 TESTING OF VLSI CIRCUITS UNIT –V TESTABLE MEMORY DESIGN

PREPARED BY : G.I.SHAMINI

Syllabus

RAM fault model – Test algorithm for RAMs. GALPAT – March Test – Detection of pattern
sensitive faults built in self test techniques for RAM chips. Self testable SRAM architecture.
Test generation and BIST for Embedded RAMs.

1. RAM fault model.

Classical fault models are not sufficient to represent all important failure
modes in RAM. Sequential ATPG is not possible for RAM. Functional fault models
are commonly used for memories: they define functional behavior of faulty memories.
New fault models are being proposed to cover new defects and failures in modern
memories.

1. SAF Stuck-At Fault

2. TF Transition Fault

3. CF Coupling Fault

4. NPSF Neighbourhood Pattern Sensitive Fault

5. AF Address decoding fault

1. Stuck-At Fault (SAF)

Cell (line) SA0 or SA1

– A stuck-at fault (SAF) occurs when the value of a cell or line is always 0 (a stuck-
at-0 fault) or always 1 (a stuckat-1 fault).
– A test that detects all SAFs guarantees that from each cell, a 0 and a 1 must be
read.
2. Transition Fault (TF)

Cell fails to transit from 0 to 1 or 1 to 0 in specified time period.

– A cell has a transition fault (TF) if it fails to transit from 0 to 1 (a<↑/0> TF) or from
1 to 0 (a<↓/1>TF).

3. Address-Decoder Fault (AF)

An address decoder fault (AF) is a functional fault in the address decoder that
results in one of four kinds of abnormal behaviour:
– Given a certain address, no cell will be accessed
– A certain cell is never accessed by any address

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– Given a certain address, multiple cells are accessed

– A certain cell can be accessed by multiple addresses.
4. Stuck-Open Fault (SOF)

A stuck-open fault (SOF) occurs when the cell cannot be accessed due to, e.g.,
a broken word line. A read to this cell will produce the previously read value.

5. Coupling Fault (CF)

A coupling fault (CF) between two cells occurs when the logic value of a cell
is influenced by the content of, or operation on, another cell.
6. State Coupling Fault (CFst)
Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in given
state.
7. Inversion Coupling Fault (CFin)
Transition in coupling cell complements (inverts) coupled cell.
8. Idempotent Coupling Fault (CFid)
Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to 0.
9. Disturb Fault (DF)
Victim cell forced to 0 or 1 if we (successively) read or write aggressor cell
(may be the same cell)
10. Hammer test Read Disturb Fault (RDF)

There is a read disturb fault (RDF) if the cell value will flip when being read
(successively).

11. Data Retention Fault (DRF)

DRAM
– Refresh Fault
– Leakage Fault
SRAM
– Leakage Fault Static Data Losses-defective pull-up.

2. RAM Test Algorithm

A test algorithm (or simply test) is a finite sequence of test elements: A test element contains

 a number of memory operations (access commands)

 Data pattern (background) specified for the Read and Write operation
 Address (sequence) specified for the Read and Write operations

2.1 March test algorithm

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A march test algorithm is a finite sequence of march elements: A march

element is specified by an address order and a finite number of Read/Write
operations. The march test notations are given by:

⇑: address sequence is in the ascending order

⇓: address changes in the descending order

: address sequence is either ⇑ or ⇓

r: the Read operation Reading an expected 0 from a cell (r0); reading an expected
1 from a cell (r1)

w: the Write operation Writing a 0 into a cell (w0); writing a 1 into a cell (w1)

Example (MATS+): { c(w );0 ⇑ (r ,0 w );1 ⇓(r ,1 w0)}

Another example of march test { (w1); (r1, w0)}

Initial state

Addressing cell 0 Addressing cell 1 Addressing cell 2 Addressing cell 3

(w1)
Addressing cell 0 Addressing cell 1 Addressing cell 2 Addressing cell 3

(r1,w0)

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2.1.1 March Tests for SAFs & TFs

MATS+:{ (w0); ⇑ (r0,w1); ⇓ (r1,w0)}

 MATS+ detection of SA0 fault

Good memory after M0 Good memory after M1 Good memory after M2

Bad memory after M0 Bad memory after M1 Bad memory after M2

 MATS+ detection of SA1 fault

Good memory after M0 Good memory after M1 Good memory after M2

Bad memory after M0 Bad memory after M1 Bad memory after M2

MATS+ detection of TFu&TFd can be proved in the same way. SAFs & TFs can be
detected by a march test which contains the following two march elements (or single march
element containing both elements).

(…,w0,r0,…) to detect SA1 faults and TFd

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(…,w1,r1,…) to detect SA0 faults and TFu

2.1.2 March Tests for CFs

March C : { (w0); ⇑ (r0,w1); ⇑ (r1,w0); ⇓ (r0,w1); ⇓ (r1,w0); (r0)}

Detection of CFs :

M1 is executed

Cell 0 is Cell 1 is Cell 2 is Cell 3 is Cell 8 is

Addressed addressed addressed addressed addressed

M3 is executed

Cell 0 is Cell 1 is Cell 2 is Cell 3 is Cell 8 is

Addressed addressed addressed addressed addressed

Conditions for detecting CFs :− A march test which contains one of the two pairs of march
elements of Case A & Case B can detect simple CFs (CFin, CFst, CFid).
 Case A

1.

2.

 Case B

1.

2.

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A.1 (A.2) will sensitize the CFs, and it will detect the fault, when the value of the
fault effect is x’ (x), by the rx (rx’) operation of the first (second) march element when the
coupled cell has a higher (lower) address than the coupling cell.
2.1.3 March Tests for DRFs
Data retention faults (DRFs) two subtypes:
 A stored ‘1’ will become a ‘0’ after a time T
 A stored ‘0’ will become a ‘1’ after a time T
Conditions for detecting DRFs
 Any march test can be extended to detect DRFs
 The detection of each of the two DRF subtypes requires that a memory cell be
written into the corresponding logic states
If we are detecting only simple DRFs then the delay elements can be placed between any two
pairs of march elements, e.g.,⇑ (rx’,. . . ,wx) ; Del; ⇓(rx’,. . . ,wx).
2.1.4 March Tests for AFs
Conditions for detecting AFs are as follows:
1. Read the value x from cell 0, then write x’ to cell 0, …, read the value x from
cell n-1, then write x’ to cell n-1.
2. Read the value x’ from cell n-1, then write x to cell n- 1, …, read the value x’
from cell 0.
Sufficiency of the conditions for detecting AFs
1. Fault A & B: Detected by every test that detects SAFs. When address A x is
written and read, Cx will appear either SA0 or SA1.
2. Fault C: Detected by first initializing the entire memory to an expected value
x or x’. Any subsequent march element operation that reads the expected
value x and ends by writing x’ detects fault C.
3. Fault D:
 The memory my return a random result. The fault must be generated
when Ax is written, and detected when either Aw and Av is read
 Condition 1 detects fault D1 and D2
 Condition 2 detects fault D1 and D3
Necessity of the conditions for detecting AFs

 Remove rx from Condition 1 : A test cannot detect fault A or B for the case they
always return x’
 Remove rx’ from Condition 2 : A test cannot detect fault A or B for the case they
always return x
 Remove rx or wx’ from Condition 1 : A test cannot detect fault D2
 Remove rx’ or wx from Condition 2 : A test cannot detect fault D3

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 Remove both write operations : A test cannot detect fault C and fault D1

2.2 Detection of pattern sensitive faults

The basic concept of pattern sensitive is the victim cell is forced to 0 or 1 if a certain
number of neighbors show a particular pattern. The PSF is the most general k-coupling fault
with k=n. With the Neighborhood Pattern Sensitive Fault (NPSF), the neighborhood is
limited to all the cells in a single position surrounding the base cell which is represented in
figure 1.

Figure 1: Neighbourhood Pattern Sensitive Fault.

It is equivalent to an N-coupling fault involving more than one aggressor (up to 8

adjacent locations).It is extremely hard to detectfor each memory cell: the effect of all the
possible combinations (28) of the adjacent cells should be tested.

There are several methods and algorithms to perform tests for Neighborhood Pattern
Sensitive Faults (NPSFs). A type 1 neighborhood contains five cells that is the base cell and
the four cells physically adjacent to the base cell which is shown in figure 2 . Usually the type
1 neighborhood is used because the deleted neighborhood of the type 1 neighborhood is most
likely to influence the base cell (since all neighborhood share a row or a column with the base
cell) and because of its simplicity and smaller test time. The type-2 NPSF is with 8
neighborhood cells which is shown in figure 3.

Figure 2: Type 1 Figure 3: Type 2

Cells N,W,B,E,S is represented as 0,1,2,3,4 and 5. The main types of NPSFs are Active
NPSF, Passive NPSF and static NPSF.

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1. Active NPSF (ANPSF):

 Change of the base cell due to a transition in the neighborhood cells
 Each base cell must be read in state 0 and in state 1, for all possible
changes in the neighborhood pattern

2. Passive NPSF (PNPSF):

 The change of the base cell is impossible due to a certain neighborhood

cells configuration
 Each base cell must be written and read in state 0 and in state 1, for all
permutations in the neighborhood pattern

3. Static NPSF (SNPSF):

 The content of the base cell is forced to a certain state due to a certain
neighborhood pattern
 Each base cell must be read in state 0 and in state 1, for all permutations in
the neighborhood pattern

It is essential to minimize the number of writes during NPSF testing. SNPSF patterns are
produced following an Hamiltonian sequence (hamiltonian distance of 1 between patterns,
Gray code for example): k+2k-1 writes. ANPSF and PNPSF patterns are produced following
an Euleriansequence : k+k.2k writes . The number of writes furtherreduced by testing the
neighborhoodssimultaneously. It isperformed by twomethods. That are Tilingmethod and
Two group Method.

2.2.1 Tilingmethod

The tiling method totally covers memory with nonoverlappingneighborhoods. Figure

4a and 4b depicts this for a 5-element Type-1 neighborhood. Cell 2 is always the base cell,
and the deleted neighborhood cells are numbered shown. When all static neighborhood
patterns (SNPs) are applied simultaneously to the neighborhoods of all base cells-2, they are
automatically applied to the neighborhoods of all base cells in the memory .This reduces the
pattern length from n*2k patterns to (n/k)* 2k patterns.

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(a)Type 1 tilingneighbour (b) Neighbourhoods of base cells 0,1,2,3

and 4

Figure 4 : Tilingmethod

2.2.2 Two-group method:

For the two-group method, a cell is simultaneously a base cell in one group and a
deleted neighbourhood cell in the other group, and vice versa. With this duality property, cells
are divided into two groups, group-1 and group-2, in a checkerboard pattern; depicted in
Figure 5. Base cells of group-1 are deleted neighbourhood cells of group-2, and vice versa.
Each group has n/2 base cells b and n/2 deleted neighbourhood cells formed by 4 subgroups
A, B, C and D. This only works for Type-1 neighbourhoods.

Figure 5 : Cell labels in two group method

3. Self testable SRAM architecture

The architecture of the testable RAM isshown in figure 6. The control signals c1 and
c2 are used to select the mode of operation of the RAM as follows

C1 C2 Mode of operation

0 0 normal

0 1 BIST

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1 x Scan

During the BIST mode,theaddresscountergenerates the addresssequence 0,…..,n-1 of the

RAM array.Thewaitcounteriscombinedwith the addresscounter,anditisused to test for data
retentionfaults.Thedetection of such a faultrequiresthat a 0(1), bewritteninto a memorycell
and after a certain time, the content of the cellbeverified. The waitcountergenerates the
necessaryamount of wait or delay time for the data retention test.

The function of the data generatoris to generate certain data words and their
compliments inorder to detect the possible couplingfaultsbetween cella at the
sameaddress.The data produced by the SRAM during the READ operation are accepted by
the data receptor(parallel signature analyzer), and compressed to generate a unique signature.
Once the signature has been generated,the signature generatoris set in a hold mode, and the
signature isseriallyshiftedout.Itisthencomparedwith the reference signature calculated by
using a dedicated software tool.The signature generatureconsists of a minimum of
eightmemoryelements to ensure a satisfactoryfaultcoverage.The test
logiccanbefullytestedusing the builtin scan capability.

Figure 6 : Self testable SRAM architecture

4. Test generation and BIST for Embedded RAMs.

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Embedded RAMS are widely used in digital integrated Systems such as

telecommunications ASICs and broadband ISDN, in processors for implementing cache
memories and registers, and in DSP chips for storage of weights. It is not possible to test an
embedded RAM simply by applying test patterns directly to the chip’s 1/0 pins, because the
embedded RAM’S address, data, and control signals are not directly accessible through the
1/0 pins (Figure 7).

Figure 7: Embedded RAM

Instead, their inputs and outputs have to be accessed through the logic in which the
memories are embedded. Many of the RAM test algorithms involve applying test vectors in a
particular sequence, and it would be difficult to apply the test vectors in the correct sequence
through the embedding logic, let alone generate all of the required test vectors.

Sample Questions

1. With neat diagram, Explain about Self Testable SRAM architecture.

2. How to detect the pattern sensitive faults in random access memory and explain built
in self test techniques for RAM chips.
3. Draw the fault model for RAM. Explain any one testing algorithm to test random
access memory.
4. Explain the various test algorithms for RAM’s.
5. Explain in detail about test generation and BIST for Embedded RAM’s with necessary
diagrams.

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