Scribd
Upload
63 views14 pages

Peripheral IO: Pads, ESD, IO Circuits: Design of Neuromorphic Electronic Systems

Pads interface the chip to the outside world and protect against electrostatic discharge (ESD). They provide openings for bonding wires and include ESD protection structures to dissipate high voltages from ESD and prevent gate oxide breakdown. Different pad types exist for various functions like power, analog/digital input/output, and biasing. Pads are a critical part of chip design and require careful consideration of ESD protection and drive requirements.

Uploaded by

Surendra Lovely Surendra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
63 views14 pages

Peripheral IO: Pads, ESD, IO Circuits: Design of Neuromorphic Electronic Systems

Pads interface the chip to the outside world and protect against electrostatic discharge (ESD). They provide openings for bonding wires and include ESD protection structures to dissipate high voltages from ESD and prevent gate oxide breakdown. Different pad types exist for various functions like power, analog/digital input/output, and biasing. Pads are a critical part of chip design and require careful consideration of ESD protection and drive requirements.

Uploaded by

Surendra Lovely Surendra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 14

Peripheral IO:

Pads, ESD, IO circuits


Design of Neuromorphic Electronic
Systems
What are pads and what do they do?
• Interface circuits to outside world
• Provide opening in overglass and metal area for
attaching bonding wires
• Protect against ESD (electro static discharge)
ESD
• Your body has a capacitance of a few hundred pF
• You can become charged with static electricity to
~10kV
• SiO2 has a breakdown field of ~600V/µm; a 10nm gate
oxide (0.5µm process) will pop with a voltage of more
than 6V
• ESD protection structures dissipate the ESD and prevent
gate overvoltage
• The ESD protection structure must be able to dissipate
an energy of CV2=10mJ
HBM (human body model) for ESD

~10kV
Hand-held ESD tester
The bond pad

OG OG
M2
M1

N-well

P-substrate
ESD grounded-
gate protection
structure

PN junctions forward bias for


over- or under-voltages.
Energy is dissipated in
junctions.

Series resistor dissipates energy


Protection transistor layout

~100 um
Pad frame
Strain relief
Types of pads
• Power pads (padGND, padVDD)
• Analog input pads (padIn, padInOr)
• Analog output pads (padWide)
• Digital IO pads (padDigIn, padDigOut)
• Special pads (padBias)
Digital IO
Wide range analog output pad

-
N
+

-
P
+
Summary
• Pads are chip IO points
• They protect CMOS from ESD and drive large
off-chip loads at high speed
• Pad type depends on requirements (Power,
analog input or output, digital input or output)
• It is best to start with a qualified set of pads and
make changes very conservatively

You might also like