COPROCESSORS

INTRODUCTION

A co-processors is a high-speed numeric microprocessor designed to work with a match-

ing MPU, and usually installed in an empty IC socket specifically provided for it by the
system board manufacturer. It extends the system’s arithmetic and instruction set to provide
for high-speed mathematical calculation capabilities.

THE 8087 NUMERIC DATA CO-PROCESSOR

The 8087 high-speed math coprocessor works in parallel with the 8088/8086 and extends
its instruction set to include 68 additional arithmetic, trigonometric and logarithmic instruc-
tions for seven different types of data. These data types include: 16, 32 and 64-bit integers;
32, 64 and 80-bit floating-point numbers; and 18-digit BCD numbers. The 8087 performs
these operations up to 100 times faster than the 8088 alone could.

To the system, the 8087 appears as a very large set of accessible registers. The most notice-
able of these is a stack of eight, individually addressable, 80-bit registers (R1 through R8).
The 8087’s math computations are performed in these registers. Different types of instruc-
tions may be used to access the various registers independently or as a normal microproces-
sor stack register would be accessed.

The data registers are theoretically divided

into three fields, as depicted in Figure 1. The
actual use of these fields varies with the type
of data being operated on. When the 8087 re-
ceives numeric data words, it stores and holds
them in a format called temporary real form.
This is the form described in the figure. The
number is expressed as the product of a 64-bit
significand (base) and a 15-bit exponent. The
MSB of the register is reserved as a sign bit
(indicating a positive or negative number). In-
structions presented to the 8087 automatically
convert into this format when loading the reg-
isters and back to the other formats when re-
turning them to the system’s memory unit.

Instructions may also be used to alter the for-

mat of the numbers inside the 8087. When this
is done, the fields of the register involved are
also redefined to accommodate the desired
format.
Figure 1: 8088/8087 System

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 A two-bit register, called the TAG field, is attached to each data register. The 8087 uses
these fields to mark the contents of each data register as valid, zero, special, or empty.

Like the 8088 and other common microprocessors, the 8087 contains several control regis-
ters. In particular, the 8087 contains a control register, a status register, and an instruction
pointer register. The control register holds a 16-bit control word written into the 8087 by the
software. The lower-order byte of the control word configures the 8087’s interrupts and ex-
ception masks. Exceptions are interrupt routines, which decide the 8087’s course of action
after the occurrence of an error condition. The 8087 recognizes 6 different exception condi-
tions, all of which will cause an interrupt to occur if they are unmasked and enabled. The
higher-order byte of the control word configures the 8087’s operating mode, including it’s
numerical precision level and rounding control.

The operation of the 8087’s Status Register is very similar to the 8088’s flag register, in that
its bits reflect the state of the coprocessor’s internal operation. Six of the status word’s 16 bits
are used to indicate the occurrence of the 8087’s six exception conditions. Three of the status
bits are used to identify the data register which is currently being used as the top-of-stack lo-
cation. Four flag-bits reflect the outcome of 8087 operations. In addition, one bit is used as an
interrupt request bit and the remaining bit is used as a BUSY bit, which the 8087 sets when it
begins to execute an instruction.

The 8087 uses the instruction and data pointer registers to hold the current instruction ad-
dress, op-code and operand address.

Figure 2 depicts the function blocks of the 8087. Basically the processor can be broken into
two units: (1) a numeric execution unit (NEU) containing the data register stack, and (2) the
control unit (CU) containing a data bus buffer, and the status and control registers. These
units duplicate the functions performed by any mP’s control and ALU blocks. However, un-
like conventional microprocessors, the 8087’s NEU and CU can work independently of one
another. The CU works to maintain synchronization with the 8088 while the NEU is per-
forming numeric operations.

Figure 2: Block Diagram - 8087 Numeric Data Co-processor

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The 8088 and 8087 actually work in parallel. The 8087 maintains an instruction queue which
is the mirror image of the one in the 8088. However, the 8087 is only activated by special ES-
CAPE CODE instructions in the software. When an Escape instruction appears in the soft-
ware stream, both the 8088 and 8087 receive and decode the instruction.

The two processors execute the ESCAPE instruction simultaneously. If the instruction word
consists simply of an op code (no operand address), the 8088 simply advances to the next in-
struction while the 8087 executes the ESCAPE instruction. These instructions call for some
manipulation of the 8087’s internal registers and do not require any additional data from the
system’s memory unit.

If the ESCAPE instruction contains operand addresses, the 8088 performs a normal Read op-
eration at the location indicated, with the exception that it ignores the data placed on the data
bus. When the 8087 detects one of these “dummy Read” operations in progress, it latches and
saves the address placed on the bus by the 8088. The 8087 also obtains the data byte from the
data bus and places it in one of its data registers. If the numerical data is longer than a single
byte, the 8088 and 8087 part company, while the 8087 obtains control of the buses and
READS the additional data bytes.

If the ESCAPE instruction calls for the 8087 to store data in the memory unit, the 8087
latches the address supplied by the 8088, but it ignores the data placed on the data bus by the
8088’s dummy Read operation. Instead, it begins breaking-up the data in its selected regis-
ter(s) into 8-bit words. When the 8087 is ready to Write the data into memory, it obtains con-
trol of the buses from the 8088 and begins Writing the data, starting at the location latched
from the address bus. The 8087 continues writing data bytes into sequential memory loca-
tions, least significant byte first, until all of the data specified has been written into the mem-
ory.

Figure 3 shows the connection scheme between the 8088 and the 8087. The 8087 monitors
the 8088’s operation through its S3–S6 status lines and QS0–QS1 queue status lines. The
S3-S6 lines monitor the 8088’s S0–S2 and S6 status lines to determine when an instruction is
being fetched from memory. The 8087 updates its internal instruction queue by monitoring
the 8088’s QS0-QS1 queue status lines. In this way, the 8087 maintains an instruction queue
that is identical to the one in the 8088. When the 8087 assumes control of the system’s buses,
it controls the 8288 bus controller through its own S0–S2 status lines in the same manner as
the 8088 does during normal operations.

Figure 3:
8088/8087
Connection

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 When an ESCAPE instruction calls for the 8087 to gain control of the buses, it issues a Re-
quest pulse on the RQ/GT0 line and then waits for a reciprocal Grant pulse from the 8088 on
the same line. Upon receipt of the Grant pulse, the 8087 begins executing the instruction and
places a high logic level on its BUSY pin. This line is connected to the 8088’s TEST-pin and
informs it that the 8087 is executing an instruction. The 8088 enters a WAIT state for the du-
ration of the 8087’s bus activities. When the 8087 completes the bus operation, it will acti-
vate RQ/GT0 once again to indicate the release of the bus, giving control again to the 8088.
The 8087 also drops its busy signal, so that both processors can resume parallel operation.

The 8087 also has the capability to interrupt the 8088 via its interrupt (INT) line when it de-
tects the occurrence of an exception state. In the XT compatible, this line is usually con-
nected to the system’s non-maskable interrupt (NMI) circuitry. The remainder of the 8087’s
pins are the normal pins associated with any microprocessor. These include multiplexed ad-
dress/data pins AD0-AD15, and address/status pins A16-A19/S3-S6, in addition to
READY, RESET, CLOCK and power supply pins. One other special pin, called the Bus
High Enable (BHE/S7) pin, controls the upper half of the data bus (D8-D15). In 8-bit ori-
ented systems, like the 8088 uses, this line is tied to a high logic level voltage (disabled).

THE 80287 CO-PROCESSOR

The math co-processor designed to operate in conjunction with the 80286 microprocessor is
the 80287 depicted in Figure 4. Just as the 8087 extended the 8088/86 microprocessors’ ar-
chitecture, the 80287 adds high-performance floating point, extended integer, and BCD data
manipulation to 80286-based architecture. In all, the 80287 adds over fifty mnemonics to the
80286’s instruction set.

Figure 4: The 80287 Microprocessor Packages

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By comparing the 80287’s internal register structure with that of the 8087’s (depicted in Fig-
ures 1 and 2), it can be seen that they are identical. However, there are some operational dif-
ferences between the 8087 and the 80287. Like the 80286 microprocessor, the 80287
operates in Real and Protected addressing modes. In real mode, the 80286/80287 combina-
tion is completely compatible with the 8088/87 or 8086/87 set. However, when the 80287 is
switched into protected mode, all address references follow the memory management and
protection guidelines established for the 80286 microprocessor.

Although the 80287 may be connected to the same clock source as its host microprocessor
(the 80287 can also be used in 80386-based systems), it does not operate at that speed. The
80287 internally divides the external clock frequency by one third. In many system’s, the
80287 is clocked from a dedicated co-processor clock.

80387DX AND 80387SX CO-PROCESSORS

Just as the 80287 improved on the basic 8087 co-processor by operating in protected mode,
the 80387DX and 80387SX coprocessors improve on the 80287 design by producing up to
seven times as much output. These co-processors are code-compatible with the 80287 and,
therefore, should run all software written for the 80287. However, systems using an 80287
coprocessor may not run programs that have been optimized to work directly with 80387DX
or 80387SX co-processors.

Like the 386DX and 386SX, the 387DX and 387SX differ basically when it comes to their
bus sizes. The 387SX is designed to operate with a 16-bit bus instead of the 32-bit bus of the
387DX. Except for this minor difference, both ICs conform to the same block diagram
shown in Figure 5.

Figure 5: Inside the 80387DX and 80387SX

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 Externally, the two IC’s are quite different. The 80387DX is available in a 68-pin Pin Grid
Array (PGA) package similar to that of the 80386DX microprocessor, only smaller. The
80387SX comes only in Plastic Leadless Chip Carrier (PLCC) packages. The 387SX’s
package differs considerably from that of the surface-mount package used with the 386SX
microprocessor.

The 80387 co-processors are available in a variety of operating speeds. Like the 80286,
80386DX, 80386SX, and the 80287, the recommended operating speed of the device is
specified on the package by a number given after the chip’s type number (i.e., an 80387DX-
25 is a 387 rated for operation at 25 MHz or less). However, the 80387’s design allows it to be
operated asynchronously or synchronously with the system’s processor’s clock. When the
387’s CKM pin is tied high, the co-processor will operate in synchronous mode and should
use the system’s processor clock. If the CKM pin is tied low, the co-processor operates in
asynchronous mode using its own clock source. The two devices’ operating speeds should be
as compatible as possible. A 33 MHz 386DX can be operated with a 33 MHz or 25MHz
387DX co-processor, and a 25MHz 386 can accommodate a 20 MHz or 25 MHz co-
processor.

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