<Amee_Gorajiya>

<Dhaval_Sanepara>
<Riya_Patel>
<Shrushti_Boraniya>
<Group 4>

eiTRA PROJECT REPORT - <Floating Point Arithmetic>

Sr.No Topic Page. No.
1. PROJECT STATEMENT 3
2. FUNCTIONAL SPECIFICATIONS 3
INTRODUCTION 3
BASIC CONCEPT 3
SYSTEM DIAGRAM 5
3. WORKING 6
4. SIMULATIONS 10
5. RTL SCHEMATIC 12
6 REFERENCES 13
3 Project Report - <Floating Point Arithmetic>

PROJECT STATEMENT
Design a Floating point Arithmetic

FUNCTIONAL SPECIFICATIONS

Introduction
Floating-point units (FPU) colloquially are a math coprocessor which is designed
specially to carry out operations on floating point numbers. Typically FPUs can handle
operations like addition, subtraction, multiplication and division. FPUs can also
perform various transcendental functions such as exponential or trigonometric
calculations, though these are done with software library routines in most modern
processors.

Floating Point Arithmetic represent a very good compromise for most numerical
applications.

Arithmetic functions on floating point numbers consist of addition, subtraction,

multiplication and division. The functions are done with algorithms similar to those
used on sign magnitude integers (because of the similarity of representation) --
example, only add numbers of the same sign. If the numbers are of opposite sign, must
do subtraction. Floating Point numbers are frequently used for numerical calculations
in computing systems.

Basic Concept

The term floating point implicates that there is no fixed number of digits before and
after the decimal point; i.e. the decimal point can float. Floating-point representations
are slower and less accurate than fixed-point representations, but can handle a larger
range of numbers. Because mathematics with floating-point numbers requires a great
deal of computing power, many microprocessors come with a chip, called a floating
point unit (FPU), specialized for performing floating-point arithmetic.

FPUs are also called math coprocessors and numeric co- processors. Usage of binary
numeration and powers of 2 resulted in floating point numbers being represented as
single precision (32-bit) and double precision (64-bit) floating-point numbers.
4 Project Report - <Floating Point Arithmetic>
The floating point numbers representation is based on the scientific notation: the
decimal point is not set in a fixed position in the bit sequence, but its position is
indicated as a base power.

Figure 1 Representation of Floating Point

All the floating point numbers are composed by three components:

• Sign: it indicates the sign of the number (0 positive and 1 negative)
• Mantissa: it sets the value of the number
• Exponent: it contains the value of the base power (biased)
• Base: the base (or radix) is implied and it is common to all the numbers (2 for binary
numbers)

• The Standard IEEE 754

The first question that comes to mind is “What’s IEEE?”. The Institute of Electrical and
Electronics Engineers (IEEE) is a non-profit professional association dedicated to
advancing technological innovations and excellence. It was founded in 1884 as the
AIEE (American Institute of Electrical Engineers). The IEEE was formed in 1963 when
AIEE merged with IRE (Institute of Radio Engineers). One of its many functions is
leading standards development organization for the development of industrial
standards in a broad range of disciplines as telecommunications, consumer electronics
or nanotechnology.

IEEE 754 is one of these standards.

• Overview
Standard IEEE 754 specifies formats and methods in order to operate with
floating point arithmetic. These methods for computational with floating point
numbers will yield the same result regardless the processing is done in hardware,
software or a combination for the two or the implementation.

The standard specifies:

• Formats for binary and decimal floating point data for computation and data
interchange.
• Different operations as addition, subtraction, multiplication and other operations.
• Conversion between integer-floating point formats and the other way around.
5 Project Report - <Floating Point Arithmetic>
• Different properties to be satisfied when rounding numbers during arithmetic and
conversions.
• Floating point exceptions and their handling (NaN, ±∞ or zero).

IEEE 754 specifies four different formats to representing the floating point values:
• Simple Precision (32 bits)
• Double precision (64 bits)
• Simple Extended Precision (≥43 bits but not too used)
• Double Extended Precision (≥79 bits, usually represented by 80)

IEEE 754 representation of 32bit single-precision is given as follows:

Figure 2 32-bit Single Precision Format

System Diagram

Figure 3 System Diagram

6 Project Report - <Floating Point Arithmetic>

WORKING
Floating-point Addition/Subtraction
Given two floating-point numbers, the sum is
(F 1 x 2 E1 ) + (F 2 x 2 E2 ) = F x 2 E
Addition:

AS

ES

BS EX1=EX2 CS

FS HS
ADDER

DS GS
OUTPUT

Figure 4 State Diagram for Addition

• Calculation for Addition:

Following figure describes the working finite sate for addition. Steps related to it are
as follows:
1) The Data in1 and Data in2 both are fed to the hardware ALU.
2) When whole data of 32 bits is filled then the signals full1 and full2 will get high.
After that the rest of the state goes high. It will move to AS state.
3) In AS state comparison of exponent is done and it will move to ES state.
4) When the EXP1=EXP2 are equal then it will pass to FS state
5) When EXP1>EXP2 it will pass to BS state.
6) When EXP<EXP2 it will pass to CS state.
7) The state BS and CS state will multiply the mantissa by 10 each time the loop is
executed.
8) The output of BS and CS states will pass to FS state.
9) FS State will get the new data and main data (nmd,ndc) and will perform the
required operation.
7 Project Report - <Floating Point Arithmetic>
10) Addition is performed in the DS state.
11) If the value is negative then 2's complement is done in the successive stage
and the output data is transferred to IEEE 754 Standard.
12) The final data output is achieved in the HS State.

Subtraction:

AS

ES

EX1=EX2
BS CS

FS
Subtractor HS

DS GS
OUTPUT

Figure 5 State Diagram for Subtraction

• Calculation for Subtraction:

Following figure describes the working finite sate for subtraction. Steps related to it
are as follows:

1) The Data in1 and Data in2 both are fed to the hardware ALU.
2) When whole data of 32 bits is filled then the signals full1 and full2 will get high.
After that the rest of the state goes high.It will move to AS state.
3) In AS state comparison of exponent is done and it will move to ES sstate.
4) When the EXP1=EXP2 are equal then it will pass to FS state
5) when EXP1>EXP2 it will pass to BS state.
6) When EXP<EXP2 it will pass to CS state.
7) The state BS and CS state will multiply the mantissa by 10 each time the loop is
executed.
8) the output of BS and CS process goes to FS
9) FS State will get the new data and main data (nmd,ndc) and will perform the
required operation.
10) Subtraction is performed in the DS state.
8 Project Report - <Floating Point Arithmetic>
11) If the value is negative then 2's complement is done in the successive stage
and the output data is transferred to IEEE 754 Standard.
12) The final data output is achieved in the HS State.

• Floating-point Multiplication
In this designed the single-precision multiplier for floating-point numbers. Use 23
bit fractions and 9 bit exponents, with negative numbers represented in 2’s
complement.
Given two floating-point numbers, the product is
(F 1 ×2 E1 ) × (F 2 × 2 E2 ) = (F 1 × F 2 ) × 2 (E1+E2) = F × 2 E

aluin1 aluin2
MAS

Multiplier

MBS
Overfow

MCS

out

Figure 6 State Diagram for Multiplication

• Calculation for Multiplication:

Following figure describes the working finite sate for multiplication. Steps related to it
are as follows:
1) MUL consist of three states: MAS,MBS,MCS.
2) The Inputs aluin1 and aluin2 are given to the multiplier through the serial in
parallel out and will perform the following operation specified in the following
states.
3) In MAS state, this state will compare the exponent sign. When the sign of
exponentis {+,+} it will perform addition, when {+,-} it will perform subtraction
and will assign the sign of greater number, when {-,-} it will perform addition and
9 Project Report - <Floating Point Arithmetic>
assigned the sign of greater number. When {-,+} it will perform subtraction and
and the sign of greater number is assigned.
4) In MBS state it will multiply the data and in case the data is negative then it will
perform 2's complement.
5) In MCS state when the data is greater then 2^23, overflow condition occurs. So,
overflow flag gets high and the output in aluiout will be in form of xxxx.

• Floating-point Division
In this designed the single-precision divider for floating-point numbers. Used 23 bit
fractions and 9 bit exponents, with negative numbers represented in 2’s
complement.
Given two floating-point numbers, the product is
(F 1 ×2 E1 ) ÷ (F 2 × 2 E2 ) = (F 1 ÷ F 2 ) × 2 (E1-E2) = F × 2 E

aluin1 aluin2
DAS
EX1 - EX2

UnderFlow

DBS
Divider

DCS out

Figure 7 State Diagram for Division

• Calculation for Division:

Following figure describes the working finite sate for multiplication. Steps related to it are
as follows:
1) Division consist of three states: DAS,DBS,DCS.
2) The Inputs aluin1 and aluin2 are given to the multiplier through the serial in
parallel out and will perform the following operation specified in the
following states.
10 Project Report - <Floating Point Arithmetic>
3) In DAS state, this state will compare the exponent sign. When the sign of
exponentis {+,+} it will perform addition, when {+,-} it will perform
subtraction and will assign the sign of greater number, when {-,-} it will
perform addition and assigned the sign of greater number. When {-,+} it will
perform subtraction and and the sign of greater number is assigned.
4) In DBS state it will DIVIDE the following operand if data is negative then it
will perform 2's complement
5) In DCS state when the data is divided by zero, underflow condition occurs.
So, underflow flag gets high and the output in aluout will be in form of xxxx.

• NOTE:
The fraction part of the division is the division of fractions, and the exponent part
of the division is the subtraction of exponents. Assumed that F 1 and F 2 are
properly normalized; if they are not normalized than first normalize the fraction
part of division.

SIMULATIONS
data:
-5x 1062 and 225 x 1056
ADD:

Figure 8 Simulation of Addition

11 Project Report - <Floating Point Arithmetic>

SUB:
data:
-500x 1062 and -225 x 1056

Figure 9 Simulation of Subtraction

MUL:
data:
-500x 1062 and -225 x 1062

Figure 10 Simulation of Multiplication

12 Project Report - <Floating Point Arithmetic>

DIV:
data:
-500x 1062 and -225 x 1062

Figure 11 Simulation of Division

RTL SCHEMATIC

Figure 12 Schematic Design

13 Project Report - <Floating Point Arithmetic>

REFERENCES

[1] Floating Point Arithmetic Unit Using Verilog--Lalita Gangwar 1 and Rajan
Chaudhary 2_1,2 Department of Electronics and Communication, Future Institute of
Engineering and Technology_Bareilly, India.

[2] MASTER THESIS_DESIGN OF SINGLE PRECISION FLOAT ADDER (32-BIT

NUMBERS)_ACCORDING TO IEEE 754 STANDARD USING VHDL-- Arturo Barrabés
Castillo __Bratislava, April 25 th 2012__Supervisors: Dr. Roman Zálusky__Prof. Viera
Stopjaková__Fakulta Elecktrotechniky a Informatiky Slovenská Technická Univerzita v
Bratislave

[3] SINGLE PRECISION FLOATING POINT DIVISION__1 NAJIB GHATTE, 2 SHILPA

PATIL, 3 DEEPAK BHOIR__1,2,3Fr. Conceicao Rodrigues College of Engineering, Fr. Agnel
Ashram, Bandstand, Bandra (W), Mumbai: 400 050, India.

[4] A Floating-Point Unit for Arithmetic Operations__Jeff Walden – 6.111__13.12.06

[5] AN EFFICIENT IEEE 754 COMPLIANT FLOATING POINT UNIT USING VERILOG__A
Thesis Submitted For The Partial Fulfilment Of Requirements For Degree Of Bachelor Of
Technology IN Computer Science and Engineering BY LIPSA SAHU (108CS038) & RUBY
DEV (108CS069)__DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY ROURKELA_ROURKELA - 769008, INDIA

[6] Floating Point Adder/Subtractor__(ALTFP_ADD_SUB)__Megafunction User

Guide__Altera.