HA_N_BIT.

vhd Wed Nov 05 16:56:00 2014

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity HA_N_BIT is
5 generic(n:integer:=3);
6 Port ( A,B : in STD_LOGIC_VECTOR(n downto 0);
7 S : out STD_LOGIC_VECTOR(n downto 0);
8 C: out STD_LOGIC_VECTOR(n downto 0));
9 end HA_N_BIT;
10
11 architecture DTFL of HA_N_BIT is
12
13 begin
14 S <= A xor B;
15 C <= A and B;
16
17 end DTFL;
18
19

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 TB_HA.vhd Wed Nov 05 16:56:17 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_HA IS
5 END TB_HA;
6
7 ARCHITECTURE dtfl OF TB_HA IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT HA_N_BIT
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 S : OUT std_logic;
16 C : OUT std_logic
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal A : std_logic := '0';
23 signal B : std_logic := '0';
24
25 --Outputs
26 signal S : std_logic;
27 signal C : std_logic;
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 X: HA_N_BIT PORT MAP (
33 A => A,
34 B => B,
35 S => S,
36 C => C
37 );
38 INPUT1:process
39 begin
40 A <= '0';
41 wait for 1000 ns;
42 A <= '1';
43 wait for 1000 ns;
44 end process;
45
46 INPUT2:process
47 begin
48 B <= '0';
49 wait for 500 ns;
50 B <= '1';
51 wait for 500 ns;
52 end process;
53 END;
54

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 HA_BEH.vhd Wed Nov 05 16:57:03 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity HA_BEH is
5 Port ( A,B : in STD_LOGIC;
6 S,C : out STD_LOGIC);
7 end HA_BEH;
8
9 architecture Behavioral of HA_BEH is
10
11 begin
12 PROCESS(A,B)
13 BEGIN
14 if (A/=B) then S<='1';
15 else S<='0';
16 end if;
17 end process;
18
19 process(A,B)
20 begin
21 if ((A='1') and (B='1')) then C <= '1';
22 else C <= '0';
23 end if;
24 end process;
25 end Behavioral;
26
27

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 TB_HA_BEH.vhd Wed Nov 05 16:57:18 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_HA_BEH IS
5 END TB_HA_BEH;
6
7 ARCHITECTURE behavior OF TB_HA_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT HA_BEH
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 S : OUT std_logic;
16 C : OUT std_logic
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal A : std_logic := '0';
23 signal B : std_logic := '0';
24
25 --Outputs
26 signal S : std_logic;
27 signal C : std_logic;
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 uut: HA_BEH PORT MAP (
33 A => A,
34 B => B,
35 S => S,
36 C => C
37 );
38 INPUT1:process
39 begin
40 A <= '0';
41 wait for 1000 ns;
42 A <= '1';
43 wait for 1000 ns;
44 end process;
45
46 INPUT2:process
47 begin
48 B <= '0';
49 wait for 500 ns;
50 B <= '1';
51 wait for 500 ns;
52 end process;
53
54 END;
55

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 HA.vhd Wed Nov 05 16:57:37 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity andgate is
5 port ( x,y : in std_logic;
6 z: out std_logic);
7 end andgate;
8
9 architecture behavioral of andgate is
10 begin
11 z <= x and y;
12 end behavioral;
13 ---------------------------------
14 library IEEE;
15 use IEEE.STD_LOGIC_1164.ALL;
16
17 entity xorgate is
18 port ( m,n : in std_logic;
19 p: out std_logic);
20 end xorgate;
21
22 architecture behavioral of xorgate is
23 begin
24 p <= m xor n;
25 end behavioral;
26 ---------------------------------
27 library IEEE;
28 use IEEE.STD_LOGIC_1164.ALL;
29
30 entity HA is
31 generic(n:integer:=3);
32 Port ( A : in STD_LOGIC_VECTOR((n-1) downto 0);
33 Cin : in std_logic;
34 SumwithCarry : out STD_LOGIC_VECTOR(n downto 0);
35 Cout : out STD_LOGIC);
36 end HA;
37
38 architecture structural of HA is
39
40 SIGNAL C : std_logic_vector (n downto 0);
41 SIGNAL S : std_logic_vector ((n-1) downto 0);
42
43 component andgate is
44 port ( x,y: in std_logic;
45 z: out std_logic);
46 end component;
47
48 component xorgate is
49 port ( m,n: in std_logic;
50 p: out std_logic);
51 end component;
52
53
54 begin
55
56 C(0) <= Cin;
57

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 HA.vhd Wed Nov 05 16:57:37 2014
58 G1: for i in 0 to n-1 generate
59 X1: andgate port map (A(i),C(i),C(i+1));
60 X2: xorgate port map (A(i),C(i),S(i));
61 end generate;
62
63 SumwithCarry <= (C(n) & S);
64 Cout <= C(n);
65
66 end structural;
67
68

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 TB_HA_STRUCT.vhd Wed Nov 05 16:57:48 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_HA_STRUCT IS
5 END TB_HA_STRUCT;
6
7 ARCHITECTURE behavior OF TB_HA_STRUCT IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT HA is
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 S : OUT std_logic;
16 C : OUT std_logic
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal A : std_logic := '0';
23 signal B : std_logic := '0';
24
25 --Outputs
26 signal S : std_logic;
27 signal C : std_logic;
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 uut: HA PORT MAP (
33 A => A,
34 B => B,
35 S => S,
36 C => C
37 );
38
39 INPUT1:process
40 begin
41 A <= '0';
42 wait for 1000 ns;
43 A <= '1';
44 wait for 1000 ns;
45 end process;
46
47 INPUT2:process
48 begin
49 B <= '0';
50 wait for 500 ns;
51 B <= '1';
52 wait for 500 ns;
53 end process;
54
55 END;
56

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 FA_DTFL.vhd Wed Nov 05 16:58:09 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity FA_DTFL is
5 generic(n:integer:=3);
6 Port ( A,B,C : in STD_LOGIC_VECTOR(n downto 0);
7 S,Co : out STD_LOGIC_VECTOR(n downto 0));
8 end FA_DTFL;
9
10 architecture DTFL of FA_DTFL is
11
12 begin
13 S <= A xor B xor C;
14 Co <= (A and B) or (B and C) or (A and C) ;
15
16
17 end DTFL;
18
19

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 TB_FA_DTFL.vhd Wed Nov 05 16:58:22 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_FA_DTFL IS
5 END TB_FA_DTFL;
6
7 ARCHITECTURE behavior OF TB_FA_DTFL IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT FA_DTFL
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 C : IN std_logic;
16 S : OUT std_logic;
17 Co : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal A : std_logic := '0';
24 signal B : std_logic := '0';
25 signal C : std_logic := '0';
26
27 --Outputs
28 signal S : std_logic;
29 signal Co : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: FA_DTFL PORT MAP (
35 A => A,
36 B => B,
37 C => C,
38 S => S,
39 Co => Co
40 );
41
42 INPUT1:process
43 begin
44 A <= '0';
45 wait for 2000 ns;
46 A <= '1';
47 wait for 2000 ns;
48 end process;
49
50 INPUT2:process
51 begin
52 B <= '0';
53 wait for 1000 ns;
54 B <= '1';
55 wait for 1000 ns;
56 end process;
57

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 TB_FA_DTFL.vhd Wed Nov 05 16:58:22 2014
58 INPUT3:process
59 begin
60 C <= '0';
61 wait for 500 ns;
62 C <= '1';
63 wait for 500 ns;
64 end process;
65 END;
66

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 FA_BEH.vhd Wed Nov 05 16:59:17 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity FA_BEH is
5 Port ( A,B,C : in std_logic;
6 S,Co : OUT STD_LOGIC);
7 end FA_BEH;
8
9 architecture Behavioral of FA_BEH is
10
11 signal F: std_logic_vector(2 downto 0);
12
13 begin
14 process(A,B,C,F)
15 begin
16 F(2) <= A;F(1) <= B; F(0) <= C;
17 case F is
18 when "000"=> S <='0'; Co <= '0';
19 when "001"=> S <='1'; Co <= '0';
20 when "011"=> S <='0'; Co <= '1';
21 when "100"=> S <='1'; Co <= '0';
22 when "101"=> S <='0'; Co <= '1';
23 when "110"=> S <='0'; Co <= '1';
24 when "111"=> S <='1'; Co <= '1';
25 when others=> null;
26 end case;
27 end process;
28 end Behavioral;
29
30

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 TB_FA_BEH.vhd Wed Nov 05 16:59:36 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_FA_BEH IS
5 END TB_FA_BEH;
6
7 ARCHITECTURE behavior OF TB_FA_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT FA_BEH
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 C : IN std_logic;
16 S : OUT std_logic;
17 Co : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal A : std_logic := '0';
24 signal B : std_logic := '0';
25 signal C : std_logic := '0';
26
27 --Outputs
28 signal S : std_logic;
29 signal Co : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: FA_BEH PORT MAP (
35 A => A,
36 B => B,
37 C => C,
38 S => S,
39 Co => Co
40 );
41 INPUT1:process
42 begin
43 A <= '0';
44 wait for 2000 ns;
45 A <= '1';
46 wait for 2000 ns;
47 end process;
48
49 INPUT2:process
50 begin
51 B <= '0';
52 wait for 1000 ns;
53 B <= '1';
54 wait for 1000 ns;
55 end process;
56
57 INPUT3:process

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 TB_FA_BEH.vhd Wed Nov 05 16:59:36 2014
58 begin
59 C <= '0';
60 wait for 500 ns;
61 C <= '1';
62 wait for 500 ns;
63 end process;
64 END;
65

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 FA_STRUCT.vhd Wed Nov 05 17:00:30 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity orgate is
5 port ( w,x,y : in std_logic;
6 z: out std_logic);
7 end orgate;
8
9 architecture behavioral of orgate is
10 begin
11 z <= w or x or y;
12 end behavioral;
13 ---------------------------------
14 library IEEE;
15 use IEEE.STD_LOGIC_1164.ALL;
16
17 entity andgate is
18 port ( x,y : in std_logic;
19 z: out std_logic);
20 end andgate;
21
22 architecture behavioral of andgate is
23 begin
24 z <= x and y;
25 end behavioral;
26 ---------------------------------
27 library IEEE;
28 use IEEE.STD_LOGIC_1164.ALL;
29
30 entity xorgat is
31 port ( w,x,y : in std_logic;
32 z : out std_logic);
33 end xorgat;
34
35 architecture behavioral of xorgat is
36 begin
37 z <= w xor x xor y;
38 end behavioral;
39 ---------------------------------
40 library IEEE;
41 use IEEE.STD_LOGIC_1164.ALL;
42
43 entity FA_STRUCT is
44 generic(n:integer:=3);
45 Port ( A,B : in STD_LOGIC_VECTOR((n-1) downto 0);
46 Cin : in STD_LOGIC;
47 SumWITHcarry : out STD_LOGIC_VECTOR((n) downto 0);
48 Cout : out STD_LOGIC);
49 end FA_STRUCT;
50
51 architecture STRUCTURAL of FA_STRUCT is
52
53 SIGNAL P,Q,R,S : std_logic_vector ((n-1) downto 0);
54 SIGNAL C : std_logic_vector (n downto 0);
55
56 component andgate is
57 port ( x,y: in std_logic;

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 FA_STRUCT.vhd Wed Nov 05 17:00:30 2014
58 z: out std_logic);
59 end component;
60
61 component xorgat is
62 port ( w,x,y: in std_logic;
63 z: out std_logic);
64 end component;
65
66 component orgate is
67 port ( w,x,y: in std_logic;
68 z: out std_logic);
69 end component;
70
71 begin
72
73 C(0) <= Cin;
74 G1: for i in 0 to n-1 generate
75 X1: xorgat port map (A(i),B(i),C(i),S(i));
76 X2: andgate port map (A(i),B(i),P(i));
77 X3: andgate port map (B(i),C(i),Q(i));
78 X4: andgate port map (A(i),C(i),R(i));
79 X5: orgate port map (P(i),Q(i),R(i),C(i+1));
80 end generate;
81
82 SumWITHcarry <= (C(n) & S);
83 Cout <= C(n);
84
85 end structural;
86
87
88

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 TB_FA_STRUCT.vhd Wed Nov 05 17:00:45 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_FA_STRUCT IS
5 END TB_FA_STRUCT;
6
7 ARCHITECTURE behavior OF TB_FA_STRUCT IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT FA_STRUCT
12 PORT(
13 A : IN std_logic;
14 B : IN std_logic;
15 C : IN std_logic;
16 S : OUT std_logic;
17 Co : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal A : std_logic := '0';
24 signal B : std_logic := '0';
25 signal C : std_logic := '0';
26
27 --Outputs
28 signal S : std_logic;
29 signal Co : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: FA_STRUCT PORT MAP (
35 A => A,
36 B => B,
37 C => C,
38 S => S,
39 Co => Co
40 );
41
42 INPUT1:process
43 begin
44 A <= '0';
45 wait for 2000 ns;
46 A <= '1';
47 wait for 2000 ns;
48 end process;
49
50 INPUT2:process
51 begin
52 B <= '0';
53 wait for 1000 ns;
54 B <= '1';
55 wait for 1000 ns;
56 end process;
57

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 TB_FA_STRUCT.vhd Wed Nov 05 17:00:45 2014
58 INPUT3:process
59 begin
60 C <= '0';
61 wait for 500 ns;
62 C <= '1';
63 wait for 500 ns;
64 end process;
65 END;
66

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 FA_FUNCTION.vhd Wed Nov 05 17:01:07 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity FA_FUNCTION is
5 generic(n:integer:=3);
6 Port ( A,B : in STD_LOGIC_VECTOR (n-1 downto 0);
7 S : out STD_LOGIC_VECTOR (n downto 0));
8 end FA_FUNCTION;
9
10 architecture Behavioral of FA_FUNCTION is
11 function adder (a,b:std_logic_vector)
12 return std_logic_vector is
13 variable s:std_logic_vector (n downto 0);
14 variable c:std_logic:='0';
15 begin
16 for i in a'range loop
17 s(i):= a(i) xor b(i) xor c;
18 c := (a(i) and b(i)) or (c and b(i)) or (a(i) and c) ;
19 end loop;
20 s(n) :=c;
21 return s;
22 end adder;
23 begin
24 s<= adder(a,b);
25 end Behavioral;
26
27

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 TB_FA_FUNCTION.vhd Wed Nov 05 17:01:19 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_FA_FUNCTION IS
5 END TB_FA_FUNCTION;
6
7 ARCHITECTURE behavior OF TB_FA_FUNCTION IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT FA_FUNCTION
12 PORT(
13 A : IN std_logic_vector(2 downto 0);
14 B : IN std_logic_vector(2 downto 0);
15 S : OUT std_logic_vector(3 downto 0)
16 );
17 END COMPONENT;
18
19
20 --Inputs
21 signal A : std_logic_vector(2 downto 0) := (others => '0');
22 signal B : std_logic_vector(2 downto 0) := (others => '0');
23
24 --Outputs
25 signal S : std_logic_vector(3 downto 0);
26 -- No clocks detected in port list. Replace <clock> below with
27 -- appropriate port name
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 uut: FA_FUNCTION PORT MAP (
33 A => A,
34 B => B,
35 S => S
36 );
37 BITA2:process
38 begin
39 A(2) <= '0';
40 wait for 16000 ns;
41 A(2) <= '1';
42 wait for 16000 ns;
43 end process;
44
45 BITA1:process
46 begin
47 A(1) <= '0';
48 wait for 8000 ns;
49 A(1) <= '1';
50 wait for 8000 ns;
51 end process;
52
53 BITA0:process
54 begin
55 A(0) <= '0';
56 wait for 4000 ns;
57 A(0) <= '1';

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 TB_FA_FUNCTION.vhd Wed Nov 05 17:01:19 2014
58 wait for 4000 ns;
59 end process;
60
61 BITB2:process
62 begin
63 B(2) <= '0';
64 wait for 2000 ns;
65 B(2) <= '1';
66 wait for 2000 ns;
67 end process;
68
69 BITB1:process
70 begin
71 B(1) <= '0';
72 wait for 1000 ns;
73 B(1) <= '1';
74 wait for 1000 ns;
75 end process;
76
77 BITB0:process
78 begin
79 B(0) <= '0';
80 wait for 500 ns;
81 B(0) <= '1';
82 wait for 500 ns;
83 end process;
84 END;
85

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 FA_PROCEDURE.vhd Wed Nov 05 17:01:37 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity FA_PROCEDURE is
5 generic(n:integer:=3);
6 Port ( A,B : in STD_LOGIC_VECTOR (n-1 downto 0);
7 S : out STD_LOGIC_VECTOR (n-1 downto 0);
8 Cout : out STD_LOGIC);
9 end FA_PROCEDURE;
10
11 architecture Behavioral of FA_PROCEDURE is
12 procedure adder (a,b : in std_logic_vector;
13 signal s : out std_logic_vector;
14 signal cout: out std_logic) is
15 variable c: std_logic :='0';
16 begin
17 for i in 0 to n-1 loop
18 s(i)<= a(i) xor b(i) xor c;
19 c := (a(i) and b(i)) or (c and b(i)) or (a(i) and c);
20 end loop;
21 cout<=c;
22 end adder;
23 begin
24 adder(A,B,S,Cout);
25 end Behavioral;
26
27

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 TB_FA_PROCEDURE.vhd Wed Nov 05 17:01:48 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_FA_PROCEDURE IS
5 END TB_FA_PROCEDURE;
6
7 ARCHITECTURE behavior OF TB_FA_PROCEDURE IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT FA_PROCEDURE
12 PORT(
13 A : IN std_logic_vector(2 downto 0);
14 B : IN std_logic_vector(2 downto 0);
15 S : OUT std_logic_vector(2 downto 0);
16 Cout : OUT std_logic
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal A : std_logic_vector(2 downto 0) := (others => '0');
23 signal B : std_logic_vector(2 downto 0) := (others => '0');
24
25 --Outputs
26 signal S : std_logic_vector(2 downto 0);
27 signal Cout : std_logic;
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 uut: FA_PROCEDURE PORT MAP (
33 A => A,
34 B => B,
35 S => S,
36 Cout => Cout
37 );
38 BITA2:process
39 begin
40 A(2) <= '0';
41 wait for 16000 ns;
42 A(2) <= '1';
43 wait for 16000 ns;
44 end process;
45
46 BITA1:process
47 begin
48 A(1) <= '0';
49 wait for 8000 ns;
50 A(1) <= '1';
51 wait for 8000 ns;
52 end process;
53
54 BITA0:process
55 begin
56 A(0) <= '0';
57 wait for 4000 ns;

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 TB_FA_PROCEDURE.vhd Wed Nov 05 17:01:49 2014
58 A(0) <= '1';
59 wait for 4000 ns;
60 end process;
61
62 BITB2:process
63 begin
64 B(2) <= '0';
65 wait for 2000 ns;
66 B(2) <= '1';
67 wait for 2000 ns;
68 end process;
69
70 BITB1:process
71 begin
72 B(1) <= '0';
73 wait for 1000 ns;
74 B(1) <= '1';
75 wait for 1000 ns;
76 end process;
77
78 BITB0:process
79 begin
80 B(0) <= '0';
81 wait for 500 ns;
82 B(0) <= '1';
83 wait for 500 ns;
84 end process;
85 END;
86

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 CLA_DTFL.vhd Wed Nov 05 17:04:38 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity CLA_DTFL is
5 generic (n : integer := 3);
6 Port ( A,B : in std_logic_vector((n-1) downto 0);
7 Cin : in std_logic;
8 SUM : out std_logic_vector((n-1) downto 0);
9 Cout : out STD_LOGIC);
10 end CLA_DTFL;
11
12 architecture dtfl of CLA_DTFL is
13
14 signal C : std_logic_vector(n downto 0);
15 signal P,G,S : std_logic_vector((n-1) downto 0);
16
17 begin
18
19 C(0) <= Cin;
20 F1: for i in 0 to n-1 generate
21
22 C(i+1) <= (P(i) and C(i)) or G(i);
23 P(i) <= A(i) xor B(i);
24 G(i) <= A(i) and B(i);
25 S(i) <= P(i) xor C(i);
26
27 end generate;
28
29 Cout <= C(n);
30 SUM <= S;
31
32 end dtfl;
33
34

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 TB_CLA_DTFL.vhd Wed Nov 05 17:04:49 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_CLA_DTFL IS
5 generic (n : integer := 3);
6 END TB_CLA_DTFL;
7
8 ARCHITECTURE behavior OF TB_CLA_DTFL IS
9
10 -- Component Declaration for the Unit Under Test (UUT)
11
12 COMPONENT CLA_DTFL
13 PORT(
14 A : IN std_logic_vector((n-1) downto 0);
15 B : IN std_logic_vector((n-1) downto 0);
16 Cin : IN std_logic;
17 SUM : OUT std_logic_vector((n-1) downto 0);
18 Cout : OUT std_logic
19 );
20 END COMPONENT;
21
22
23 --Inputs
24 signal A : std_logic_vector((n-1) downto 0) := (others => '0');
25 signal B : std_logic_vector((n-1) downto 0) := (others => '0');
26 signal Cin : std_logic := '0';
27
28 --Outputs
29 signal SUM : std_logic_vector((n-1) downto 0);
30 signal Cout : std_logic;
31
32 BEGIN
33
34 -- Instantiate the Unit Under Test (UUT)
35 uut: CLA_DTFL PORT MAP (
36 A => A,
37 B => B,
38 Cin => Cin,
39 SUM => SUM,
40 Cout => Cout
41 );
42
43 INPUT1i:process
44 begin
45
46 A(2) <= '0';
47 wait for 10000 ns;
48 A(2) <= '1';
49 wait for 10000 ns;
50
51 end process;
52
53 INPUT1ii:process
54 begin
55
56 A(1) <= '0';
57 wait for 5000 ns;

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 TB_CLA_DTFL.vhd Wed Nov 05 17:04:49 2014
58 A(1) <= '1';
59 wait for 5000 ns;
60
61 end process;
62
63 INPUT1iii:process
64 begin
65
66 A(0) <= '0';
67 wait for 2500 ns;
68 A(0) <= '1';
69 wait for 2500 ns;
70
71 end process;
72
73
74 INPUT2i:process
75 begin
76
77 B(2) <= '0';
78 wait for 2000 ns;
79 B(2) <= '1';
80 wait for 2000 ns;
81
82 end process;
83
84 INPUT2ii:process
85 begin
86
87 B(1) <= '0';
88 wait for 1000 ns;
89 B(1) <= '1';
90 wait for 1000 ns;
91
92 end process;
93
94 INPUT2iii:process
95 begin
96
97 B(0) <= '0';
98 wait for 500 ns;
99 B(0) <= '1';
100 wait for 500 ns;
101
102 end process;
103
104 INPUT3:process
105 begin
106
107 Cin<= '0';
108 wait for 1000 ns;
109 Cin <= '1';
110 wait for 1000 ns;
111
112 end process;
113 END;
114

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 ENCODER_DTFL.vhd Wed Nov 05 17:05:08 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity ENCODER_DTFL is
5 Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
6 Y : out STD_LOGIC_VECTOR (2 downto 0));
7 end ENCODER_DTFL;
8
9 architecture DTFL of ENCODER_DTFL is
10
11 begin
12 Y(2) <= D(4) OR D(5) OR D(6) OR D(7);
13 Y(1) <= D(2) OR D(3) OR D(6) OR D(7);
14 Y(0) <= D(1) OR D(3) OR D(5) OR D(7);
15 end DTFL;

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 TB_ENCODER_DTFL.vhd Wed Nov 05 17:05:19 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_ENCODER_DTFL IS
5 END TB_ENCODER_DTFL;
6
7 ARCHITECTURE behavior OF TB_ENCODER_DTFL IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT ENCODER_DTFL
12 PORT(
13 D : IN std_logic_vector(7 downto 0);
14 Y : OUT std_logic_vector(2 downto 0)
15 );
16 END COMPONENT;
17
18
19 --Inputs
20 signal D : std_logic_vector(7 downto 0) := (others => '0');
21
22 --Outputs
23 signal Y : std_logic_vector(2 downto 0);
24
25 BEGIN
26
27 -- Instantiate the Unit Under Test (UUT)
28 uut: ENCODER_DTFL PORT MAP (
29 D => D,
30 Y => Y
31 );
32
33 INPUT:process
34 begin
35
36 D <= "00000001";wait for 1000 ns;
37 D <= "00000010";wait for 1000 ns;
38 D <= "00000100";wait for 1000 ns;
39 D <= "00001000";wait for 1000 ns;
40 D <= "00010000";wait for 1000 ns;
41 D <= "00100000";wait for 1000 ns;
42 D <= "01000000";wait for 1000 ns;
43 D <= "10000000";wait for 1000 ns;
44
45 end process;
46
47 END;
48

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 ENCODER_BEH.vhd Wed Nov 05 17:05:36 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity ENCODER_BEH is
5 Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
6 P : OUT STD_LOGIC;
7 Y : out STD_LOGIC_VECTOR (2 downto 0));
8 end ENCODER_BEH;
9
10 architecture Behavioral of ENCODER_BEH is
11
12 begin
13 process(D)
14 begin
15 if D(0) = '1' then Y <= "000";P <='0';
16 elsif D(1) = '1' then Y <= "001";P <='1';
17 elsif D(2) = '1' then Y <= "010";P <='1';
18 elsif D(3) = '1' then Y <= "011";P <='0';
19 elsif D(4) = '1' then Y <= "100";P <='1';
20 elsif D(5) = '1' then Y <= "101";P <='0';
21 elsif D(6) = '1' then Y <= "110";P <='0';
22 else Y <= "111";P <= '1';
23 end if;
24 end process;
25 end Behavioral;

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 TB_ENCODER_BEH.vhd Wed Nov 05 17:05:47 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_ENCODER_BEH IS
5 END TB_ENCODER_BEH;
6
7 ARCHITECTURE behavior OF TB_ENCODER_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT ENCODER_BEH
12 PORT(
13 D : IN std_logic_vector(7 downto 0);
14 P : OUT STD_LOGIC;
15 Y : OUT std_logic_vector(2 downto 0)
16 );
17 END COMPONENT;
18
19
20 --Inputs
21 signal D : std_logic_vector(7 downto 0) := (others => '0');
22 signal P : std_logic:= '0';
23
24 --Outputs
25 signal Y : std_logic_vector(2 downto 0);
26
27 BEGIN
28
29 -- Instantiate the Unit Under Test (UUT)
30 uut: ENCODER_BEH PORT MAP (
31 D => D,
32 P => P,
33 Y => Y
34 );
35
36 INPUT:process
37 begin
38 D <= "00000001";wait for 1000 ns;
39 D <= "00000010";wait for 1000 ns;
40 D <= "00000100";wait for 1000 ns;
41 D <= "00001000";wait for 1000 ns;
42 D <= "00010000";wait for 1000 ns;
43 D <= "00100000";wait for 1000 ns;
44 D <= "01000000";wait for 1000 ns;
45 D <= "10000000";wait for 1000 ns;
46 end process;
47 END;

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 PRIORITY_ENC_BEH.vhd Wed Nov 05 17:06:13 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity PRIORITY_ENC_BEH is
5 Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
6 Y : out STD_LOGIC_VECTOR (2 downto 0));
7 end PRIORITY_ENC_BEH;
8
9 architecture Behavioral of PRIORITY_ENC_BEH is
10
11 begin
12 process(D)
13 begin
14 if D(7) = '1' then Y <= "111";
15 elsif D(6) = '1' then Y <= "110";
16 elsif D(5) = '1' then Y <= "101";
17 elsif D(4) = '1' then Y <= "100";
18 elsif D(3) = '1' then Y <= "011";
19 elsif D(2) = '1' then Y <= "010";
20 elsif D(1) = '1' then Y <= "001";
21 else Y <= "000";
22 end if;
23 end process;
24 end Behavioral;
25
26

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 TB_PRIORITY_ENC_BEH.vhd Wed Nov 05 17:06:25 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_PRIORITY_ENC_BEH IS
5 END TB_PRIORITY_ENC_BEH;
6
7 ARCHITECTURE behavior OF TB_PRIORITY_ENC_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT PRIORITY_ENC_BEH
12 PORT(
13 D : IN std_logic_vector(7 downto 0);
14 Y : OUT std_logic_vector(2 downto 0)
15 );
16 END COMPONENT;
17
18
19 --Inputs
20 signal D : std_logic_vector(7 downto 0) := (others => '0');
21
22 --Outputs
23 signal Y : std_logic_vector(2 downto 0);
24
25 BEGIN
26
27 -- Instantiate the Unit Under Test (UUT)
28 uut: PRIORITY_ENC_BEH PORT MAP (
29 D => D,
30 Y => Y
31 );
32
33 BIT0:process
34 begin
35 D(0) <= '0';
36 wait for 10 ns;
37 D(0) <= '1';
38 wait for 10 ns;
39 end process;
40
41 BIT1:process
42 begin
43 D(1) <= '0';
44 wait for 20 ns;
45 D(1) <= '1';
46 wait for 20 ns;
47 end process;
48
49 BIT2:process
50 begin
51 D(2) <= '0';
52 wait for 40 ns;
53 D(2) <= '1';
54 wait for 40 ns;
55 end process;
56
57

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 TB_PRIORITY_ENC_BEH.vhd Wed Nov 05 17:06:25 2014
58 BIT3:process
59 begin
60 D(3) <= '0';
61 wait for 80 ns;
62 D(3) <= '1';
63 wait for 80 ns;
64 end process;
65
66 BIT4:process
67 begin
68 D(4) <= '0';
69 wait for 160 ns;
70 D(4) <= '1';
71 wait for 160 ns;
72 end process;
73
74 BIT5:process
75 begin
76 D(5) <= '0';
77 wait for 320 ns;
78 D(5) <= '1';
79 wait for 320 ns;
80 end process;
81
82
83 BIT6:process
84 begin
85 D(6) <= '0';
86 wait for 640 ns;
87 D(6) <= '1';
88 wait for 640 ns;
89 end process;
90
91 BIT7:process
92 begin
93 D(7) <= '0';
94 wait for 1280 ns;
95 D(7) <= '1';
96 wait for 1280 ns;
97 end process;
98
99 END;
100

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 SR_FF_BEH.vhd Wed Nov 05 19:04:12 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity SR_FF_BEH is
5 Port ( S,R,CLK : in STD_LOGIC;
6 Q,Qb : out STD_LOGIC);
7 end SR_FF_BEH;
8
9 architecture Behavioral of SR_FF_BEH is
10 signal A: std_logic;
11 begin
12 process(clk)
13 begin
14 if rising_edge(clk) then
15 if (S='0' and R='0') then A <= A;
16 elsif (S='0' and R='1') then A <= '0';
17 elsif (S='1' and R='0') then A <= '1';
18 else A <= 'Z';
19 end if;
20 end if;
21 end process;
22 Q <= A;
23 Qb <= not A;
24 end Behavioral;
25
26

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 TB_SR_FF_BEH.vhd Wed Nov 05 19:04:30 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_SR_FF_BEH IS
5 END TB_SR_FF_BEH;
6
7 ARCHITECTURE behavior OF TB_SR_FF_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT SR_FF_BEH
12 PORT(
13 S : IN std_logic;
14 R : IN std_logic;
15 CLK : IN std_logic;
16 Q : OUT std_logic;
17 Qb : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal S : std_logic := '0';
24 signal R : std_logic := '0';
25 signal CLK : std_logic := '0';
26
27 --Outputs
28 signal Q : std_logic;
29 signal Qb : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: SR_FF_BEH PORT MAP (
35 S => S,
36 R => R,
37 CLK => CLK,
38 Q => Q,
39 Qb => Qb
40 );
41
42 SET:process
43 begin
44 S <= '0'; wait for 1000 ns;
45 S <= '1'; wait for 1000 ns;
46 end process;
47
48 RESET:process
49 begin
50 R <= '0'; wait for 500 ns;
51 R <= '1'; wait for 500 ns;
52 end process;
53
54 CLOCK:process
55 begin
56 CLK <= '0'; wait for 250 ns;
57 CLK <= '1'; wait for 250 ns;

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 TB_SR_FF_BEH.vhd Wed Nov 05 19:04:30 2014
58 end process;
59
60 END;
61

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 SR_FF_DTFL.vhd Wed Nov 05 19:07:21 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity SR_FF_DTFL is
5 Port ( S,R,CLK : in STD_LOGIC;
6 Q,Qb : out STD_LOGIC);
7 end SR_FF_DTFL;
8
9 architecture DTFL of SR_FF_DTFL is
10 signal A : std_logic;
11 begin
12 with clk select
13 A <= S or ((not R) and A) when '1';
14
15 Q <= A;
16 Qb <= not A;
17
18 end DTFL;
19
20

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 TB_SR_FF_DTFL.vhd Wed Nov 05 19:07:33 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_SR_FF_DTFL IS
5 END TB_SR_FF_DTFL;
6
7 ARCHITECTURE behavior OF TB_SR_FF_DTFL IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT SR_FF_DTFL
12 PORT(
13 S : IN std_logic;
14 R : IN std_logic;
15 CLK : IN std_logic;
16 Q : OUT std_logic;
17 Qb : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal S : std_logic := '0';
24 signal R : std_logic := '0';
25 signal CLK : std_logic := '0';
26
27 --Outputs
28 signal Q : std_logic;
29 signal Qb : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: SR_FF_DTFL PORT MAP (
35 S => S,
36 R => R,
37 CLK => CLK,
38 Q => Q,
39 Qb => Qb
40 );
41 SET:process
42 begin
43 S <= '0'; wait for 1000 ns;
44 S <= '1'; wait for 1000 ns;
45 end process;
46
47 RESET:process
48 begin
49 R <= '0'; wait for 500 ns;
50 R <= '1'; wait for 500 ns;
51 end process;
52
53 CLOCK:process
54 begin
55 CLK <= '0'; wait for 250 ns;
56 CLK <= '1'; wait for 250 ns;
57 end process;

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 TB_SR_FF_DTFL.vhd Wed Nov 05 19:07:33 2014
58
59 END;
60

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 SR_FF_STRUCT.vhd Wed Nov 05 19:07:49 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity NANDGATE is
5 Port ( X,Y : in STD_LOGIC;
6 Z : out STD_LOGIC);
7 end NANDGATE;
8
9 architecture BEH of NANDGATE is
10 begin
11 Z <= X NAND Y;
12 end BEH;
13 -------------------------------------------
14 library IEEE;
15 use IEEE.STD_LOGIC_1164.ALL;
16
17 entity SR_FF_STRUCT is
18 Port ( S,R,CLK : in STD_LOGIC;
19 Q,Qb : out STD_LOGIC);
20 end SR_FF_STRUCT;
21
22 architecture STRUCT of SR_FF_STRUCT is
23 SIGNAL F: std_logic_vector(3 downto 0);
24
25 component NANDGATE is
26 Port ( X,Y : in STD_LOGIC;
27 Z : out STD_LOGIC);
28 end component;
29
30 begin
31 X1: nandgate port map (S,CLK,F(0));
32 X2: nandgate port map (CLK,R,F(1));
33 X3: nandgate port map (F(0),F(3),F(2));
34 X4: nandgate port map (F(1),F(2),F(3));
35 Q <= F(2);
36 Qb <= F(3);
37 end STRUCT;
38
39

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 TB_SR_FF_STRUCT.vhd Wed Nov 05 19:08:00 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_SR_FF_STRUCT IS
5 END TB_SR_FF_STRUCT;
6
7 ARCHITECTURE behavior OF TB_SR_FF_STRUCT IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT SR_FF_STRUCT
12 PORT(
13 S : IN std_logic;
14 R : IN std_logic;
15 CLK : IN std_logic;
16 Q : OUT std_logic;
17 Qb : OUT std_logic
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal S : std_logic := '0';
24 signal R : std_logic := '0';
25 signal CLK : std_logic := '0';
26
27 --Outputs
28 signal Q : std_logic;
29 signal Qb : std_logic;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: SR_FF_STRUCT PORT MAP (
35 S => S,
36 R => R,
37 CLK => CLK,
38 Q => Q,
39 Qb => Qb
40 );
41
42 SET:process
43 begin
44 S <= '0'; wait for 1000 ns;
45 S <= '1'; wait for 1000 ns;
46 end process;
47
48 RESET:process
49 begin
50 R <= '0'; wait for 500 ns;
51 R <= '1'; wait for 500 ns;
52 end process;
53
54 CLOCK:process
55 begin
56 CLK <= '0'; wait for 250 ns;
57 CLK <= '1'; wait for 250 ns;

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 TB_SR_FF_STRUCT.vhd Wed Nov 05 19:08:01 2014
58 end process;
59
60 END;
61

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 MSJK_FF_BEH.vhd Wed Nov 05 19:10:09 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity MSJK_FF_BEH is
5 Port ( J,K,CLK : in STD_LOGIC;
6 Reset : in STD_LOGIC;
7 Q,Qb : out STD_LOGIC);
8 end MSJK_FF_BEH;
9
10 architecture Behavioral of MSJK_FF_BEH is
11 signal A: std_logic;
12 begin
13 process(clk)
14 begin
15 if Reset='1' then A <= '0';
16 elsif (clk' event and clk='1') then
17 if(J='0' and K='0') then A <= A;
18 elsif (J='0' and K='1') then A <= '0';
19 elsif (J='1' and K='0') then A <= '1';
20 elsif (J='1' and k='1') then A <= not(A);
21 end if;
22 end if;
23 end process;
24 Q <= A;
25 Qb <= not A;
26 end Behavioral;
27
28
29
30

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 TB_MSJK_FF_BEH.vhd Wed Nov 05 19:10:21 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_MSJK_FF_BEH IS
5 END TB_MSJK_FF_BEH;
6
7 ARCHITECTURE behavior OF TB_MSJK_FF_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT MSJK_FF_BEH
12 PORT(
13 J : IN std_logic;
14 K : IN std_logic;
15 CLK : IN std_logic;
16 Reset : IN std_logic;
17 Q : OUT std_logic;
18 Qb : OUT std_logic
19 );
20 END COMPONENT;
21
22
23 --Inputs
24 signal J : std_logic := '0';
25 signal K : std_logic := '0';
26 signal CLK : std_logic := '0';
27 signal Reset : std_logic := '0';
28
29 --Outputs
30 signal Q : std_logic;
31 signal Qb : std_logic;
32
33 -- Clock period definitions
34 constant CLK_period : time := 10 ns;
35
36 BEGIN
37
38 -- Instantiate the Unit Under Test (UUT)
39 uut: MSJK_FF_BEH PORT MAP (
40 J => J,
41 K => K,
42 CLK => CLK,
43 Reset => Reset,
44 Q => Q,
45 Qb => Qb
46 );
47
48 -- Clock process definitions
49 CLK_process :process
50 begin
51 CLK <= '0';
52 wait for CLK_period/2;
53 CLK <= '1';
54 wait for CLK_period/2;
55 end process;
56
57 JOHN:process

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 TB_MSJK_FF_BEH.vhd Wed Nov 05 19:10:21 2014
58 begin
59 J <= '0'; wait for 1000 ns;
60 J <= '1'; wait for 1000 ns;
61 end process;
62
63 KILBY:process
64 begin
65 K <= '0'; wait for 500 ns;
66 K <= '1'; wait for 500 ns;
67 end process;
68
69 END;
70

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 RING_COUNTER_BEH.vhd Wed Nov 05 19:11:41 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity RING_COUNTER_BEH is
5 generic (n : integer := 4);
6 Port ( CLK,RESET,PRESET : in STD_LOGIC;
7 Q : out STD_LOGIC_VECTOR (n-1 downto 0));
8 end RING_COUNTER_BEH;
9
10 architecture Behavioral of RING_COUNTER_BEH is
11 signal F: std_logic_vector(3 downto 0):="1000";
12 begin
13 process(CLK)
14 begin
15 if (RESET='1') then F <= (others => '0');
16 elsif (PRESET='1') then F <= (others => '1');
17 elsif (CLK' event and CLK='1') then
18 F(n-1 downto 1) <= F(n-2 downto 0);
19 F(0) <= F(n-1);
20 end if;
21 end process;
22 Q <= F;
23 end Behavioral;
24
25

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 TB_RING_COUNTER_BEH.vhd Wed Nov 05 19:11:51 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_RING_COUNTER_BEH IS
5 END TB_RING_COUNTER_BEH;
6
7 ARCHITECTURE behavior OF TB_RING_COUNTER_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT RING_COUNTER_BEH
12 PORT(
13 CLK : IN std_logic;
14 RESET : IN std_logic;
15 PRESET : IN std_logic;
16 Q : OUT std_logic_vector(3 downto 0)
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal CLK : std_logic := '0';
23 signal RESET : std_logic := '0';
24 signal PRESET : std_logic := '0';
25
26 --Outputs
27 signal Q : std_logic_vector(3 downto 0);
28
29 -- Clock period definitions
30 constant CLK_period : time := 10 ns;
31
32 BEGIN
33
34 -- Instantiate the Unit Under Test (UUT)
35 uut: RING_COUNTER_BEH PORT MAP (
36 CLK => CLK,
37 RESET => RESET,
38 PRESET => PRESET,
39 Q => Q
40 );
41
42 -- Clock process definitions
43 CLK_process :process
44 begin
45 CLK <= '0';
46 wait for CLK_period/2;
47 CLK <= '1';
48 wait for CLK_period/2;
49 end process;
50 END;

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 JHONSON_COUNTER_BEH.vhd Wed Nov 05 19:12:04 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity JHONSON_COUNTER_BEH is
5 generic (n : integer := 4);
6 Port ( CLK,RESET,PRESET,DIR : in STD_LOGIC;
7 Q : out STD_LOGIC_VECTOR (n-1 downto 0));
8 end JHONSON_COUNTER_BEH;
9
10 architecture Behavioral of JHONSON_COUNTER_BEH is
11 signal F: std_logic_vector(3 downto 0):=(others => '0');
12 begin
13 process(CLK)
14 begin
15 if (RESET='1') then F <= (others => '0');
16 elsif (PRESET='1') then F <= (others => '1');
17 elsif (CLK' event and CLK='1') then
18 if(DIR='1') then
19 F(n-1 downto 1) <= F(n-2 downto 0);
20 F(0) <= not F(n-1);
21 else
22 F(n-2 downto 0) <= F(n-1 downto 1);
23 F(n-1) <= not F(0);
24 end if;
25 end if;
26 end process;
27 Q <= F;
28 end Behavioral;

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 TB_JHONSON_COUNTER_BEH.vhd Wed Nov 05 19:12:16 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_JHONSON_COUNTER_BEH IS
5 generic (n : integer := 4);
6 END TB_JHONSON_COUNTER_BEH;
7
8 ARCHITECTURE behavior OF TB_JHONSON_COUNTER_BEH IS
9
10 -- Component Declaration for the Unit Under Test (UUT)
11
12 COMPONENT JHONSON_COUNTER_BEH
13 PORT(
14 CLK : IN std_logic;
15 RESET : IN std_logic;
16 PRESET : IN std_logic;
17 DIR : IN std_logic;
18 Q : OUT std_logic_vector(n-1 downto 0)
19 );
20 END COMPONENT;
21
22
23 --Inputs
24 signal CLK : std_logic := '0';
25 signal RESET : std_logic := '0';
26 signal PRESET : std_logic := '0';
27 signal DIR : std_logic := '0';
28
29 --Outputs
30 signal Q : std_logic_vector(n-1 downto 0);
31
32 -- Clock period definitions
33 constant CLK_period : time := 10 ns;
34
35 BEGIN
36
37 -- Instantiate the Unit Under Test (UUT)
38 uut: JHONSON_COUNTER_BEH PORT MAP (
39 CLK => CLK,
40 RESET => RESET,
41 PRESET => PRESET,
42 DIR => DIR,
43 Q => Q
44 );
45
46 -- Clock process definitions
47 CLK_process :process
48 begin
49 CLK <= '0';
50 wait for CLK_period/2;
51 CLK <= '1';
52 wait for CLK_period/2;
53 end process;
54
55 DIR_process :process
56 begin
57 DIR <= '0';

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 TB_JHONSON_COUNTER_BEH.vhd Wed Nov 05 19:12:16 2014
58 wait for CLK_period*2*n;
59 DIR <= '1';
60 wait for CLK_period*2*n;
61 end process;
62 END;

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 ASYNC_BIN_RESET_COUNTER_BEH.vhd Wed Nov 05 19:14:39 2014
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.std_logic_unsigned.all;
4 use ieee.std_logic_arith.all;
5
6 entity ASYNC_BIN_RESET_COUNTER_BEH is
7 generic (n : integer := 4);
8 port(CLK,Reset, UP_DOWN : in std_logic;
9 Q : out std_logic_vector(n-1 downto 0));
10 end ASYNC_BIN_RESET_COUNTER_BEH;
11
12 architecture Behavioral of ASYNC_BIN_RESET_COUNTER_BEH is
13 signal A: std_logic_vector(n-1 downto 0);
14 begin
15 process (CLK,Reset)
16 begin
17 if (Reset='1') then
18 A <= (others => '0');
19 elsif (CLK'event and CLK='1') then
20 if (UP_DOWN='1') then
21 A <= A + 1;
22 else
23 A <= A - 1;
24 end if;
25 end if;
26 end process;
27 Q <= A;
28 end Behavioral;
29
30

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 TB_ASYNC_BIN_RESET_COUNTER_BEH.vhd Wed Nov 05 19:14:48 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_ASYNC_BIN_RESET_COUNTER_BEH IS
5 END TB_ASYNC_BIN_RESET_COUNTER_BEH;
6
7 ARCHITECTURE behavior OF TB_ASYNC_BIN_RESET_COUNTER_BEH IS
8
9 COMPONENT ASYNC_BIN_RESET_COUNTER_BEH
10 PORT(
11 CLK : IN std_logic;
12 Reset : IN std_logic;
13 UP_DOWN : IN std_logic;
14 Q : OUT std_logic_vector(3 downto 0)
15 );
16 END COMPONENT;
17
18
19 --Inputs
20 signal CLK : std_logic := '0';
21 signal Reset : std_logic := '0';
22 signal UP_DOWN : std_logic := '0';
23
24 --Outputs
25 signal Q : std_logic_vector(3 downto 0);
26
27 -- Clock period definitions
28 constant CLK_period : time := 10 ns;
29
30 BEGIN
31
32 -- Instantiate the Unit Under Test (UUT)
33 uut: ASYNC_BIN_RESET_COUNTER_BEH PORT MAP (
34 CLK => CLK,
35 Reset => Reset,
36 UP_DOWN => UP_DOWN,
37 Q => Q
38 );
39
40 -- Clock process definitions
41 CLK_process :process
42 begin
43 CLK <= '0';
44 wait for CLK_period/2;
45 CLK <= '1';
46 wait for CLK_period/2;
47 end process;
48
49 UD: process
50 begin
51 UP_DOWN <= '0'; wait for 160 ns;
52 UP_DOWN <= '1'; wait for 160 ns;
53 end process;
54
55 clear:process
56 begin
57 Reset <= '1'; wait for 160 ns;

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 TB_ASYNC_BIN_RESET_COUNTER_BEH.vhd Wed Nov 05 19:14:48 2014
58 Reset <= '0'; wait for 640 ns;
59 end process;
60 END;
61

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 ASYNC_BCD_RESET_COUNTER_BEH.vhd Wed Nov 05 19:15:11 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use ieee.std_logic_unsigned.all;
4
5 entity ASYNC_BCD_RESET_COUNTER_BEH is
6 Port ( CLK,Reset,UP_DOWN : in STD_LOGIC;
7 Q : out STD_LOGIC_VECTOR (3 downto 0));
8 end ASYNC_BCD_RESET_COUNTER_BEH;
9
10 architecture Behavioral of ASYNC_BCD_RESET_COUNTER_BEH is
11 signal A,B: std_logic_vector(3 downto 0);
12 begin
13 P1: process(CLK,Reset)
14 begin
15 if (Reset='1') then A <= "0000";
16 elsif (CLK' event and CLK='1') then
17 A <= B;
18 end if;
19 end process;
20 P2: process(A,UP_DOWN)
21 begin
22 if (UP_DOWN='1') then
23 if (A=9) then
24 B <= "0000";
25 else
26 B <= A + 1;
27 end if;
28 else
29 if (A=0) then
30 B <= "1001";
31 else
32 B <= A - 1;
33 end if;
34 end if;
35 end process;
36 Q <= A;
37 end Behavioral;
38
39

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 TB_ASYNC_BCD_RESET_COUNTER_BEH.vhd Wed Nov 05 19:15:26 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_ASYNC_BCD_RESET_COUNTER_BEH IS
5 END TB_ASYNC_BCD_RESET_COUNTER_BEH;
6
7 ARCHITECTURE behavior OF TB_ASYNC_BCD_RESET_COUNTER_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT ASYNC_BCD_RESET_COUNTER_BEH
12 PORT(
13 CLK : IN std_logic;
14 Reset : IN std_logic;
15 UP_DOWN : IN std_logic;
16 Q : OUT std_logic_vector(3 downto 0)
17 );
18 END COMPONENT;
19
20
21 --Inputs
22 signal CLK : std_logic := '0';
23 signal Reset : std_logic := '0';
24 signal UP_DOWN : std_logic := '0';
25
26 --Outputs
27 signal Q : std_logic_vector(3 downto 0);
28
29 -- Clock period definitions
30 constant CLK_period : time := 10 ns;
31
32 BEGIN
33
34 -- Instantiate the Unit Under Test (UUT)
35 uut: ASYNC_BCD_RESET_COUNTER_BEH PORT MAP (
36 CLK => CLK,
37 Reset => Reset,
38 UP_DOWN => UP_DOWN,
39 Q => Q
40 );
41 -- Clock process definitions
42 CLK_process :process
43 begin
44 CLK <= '0';
45 wait for CLK_period/2;
46 CLK <= '1';
47 wait for CLK_period/2;
48 end process;
49
50 UD: process
51 begin
52 UP_DOWN <= '0'; wait for 100 ns;
53 UP_DOWN <= '1'; wait for 100 ns;
54 end process;
55
56 clear:process
57 begin

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 TB_ASYNC_BCD_RESET_COUNTER_BEH.vhd Wed Nov 05 19:15:26 2014
58 Reset <= '1'; wait for 100 ns;
59 Reset <= '0'; wait for 200 ns;
60 end process;
61 END;
62

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 ALU_8_BIT_BEH.vhd Wed Nov 05 19:17:19 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.NUMERIC_STD.ALL;
4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
5
6 entity ALU_8_BIT_BEH is
7 Port ( CLK : in std_logic;
8 A,B : in STD_LOGIC_VECTOR (7 downto 0);
9 SEL : in BIT_VECTOR (1 downto 0);
10 Y : out STD_LOGIC_VECTOR (7 downto 0));
11 end ALU_8_BIT_BEH;
12
13 architecture Behavioral of ALU_8_BIT_BEH is
14 signal Fa,Fb,Fy: std_logic_vector(7 downto 0);
15 --signal C : std_logic;
16 --signal Div : std_logic_vector(22 downto 0);
17 begin
18 -- P1:process(CLK)
19 -- begin
20 -- if (rising_edge(clk)) then
21 -- Div <= Div + 1;
22 -- end if;
23 -- end process P1;
24 -- C <= Div(22);
25
26 P2:process(Fa,Fb,Fy,SEL,CLK)
27 begin
28 if (rising_edge(CLK)) then
29 case SEL is
30 when "00" => Fy <= Fa + Fb;---addition
31 when "01" => Fy <= Fa - Fb;---subtraction
32 when "10" => Fy <= Fa and Fb;---and
33 when "11" => Fy <= Fa or Fb;---or
34 when others => Null;
35 end case;
36 end if;
37 end process P2;
38
39 Fa <= A;
40 Fb <= B;
41 Y <= Fy;
42 end Behavioral;
43
44

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 TB_ALU_8_BIT_BEH.vhd Wed Nov 05 19:17:28 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_ALU_8_BIT_BEH IS
5 END TB_ALU_8_BIT_BEH;
6
7 ARCHITECTURE behavior OF TB_ALU_8_BIT_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT ALU_8_BIT_BEH
12 PORT(
13 CLK : IN std_logic;
14 A : IN std_logic_vector(7 downto 0);
15 B : IN std_logic_vector(7 downto 0);
16 SEL : IN bit_vector(1 downto 0);
17 Y : OUT std_logic_vector(7 downto 0)
18 );
19 END COMPONENT;
20
21
22 --Inputs
23 signal CLK : std_logic := '0';
24 signal A : std_logic_vector(7 downto 0) := (others => '0');
25 signal B : std_logic_vector(7 downto 0) := (others => '0');
26 signal SEL : bit_vector(1 downto 0) := (others => '0');
27
28 --Outputs
29 signal Y : std_logic_vector(7 downto 0);
30
31 -- Clock period definitions
32 constant CLK_period : time := 10 ns;
33
34 BEGIN
35
36 -- Instantiate the Unit Under Test (UUT)
37 uut: ALU_8_BIT_BEH PORT MAP (
38 CLK => CLK,
39 A => A,
40 B => B,
41 SEL => SEL,
42 Y => Y
43 );
44
45 -- Clock process definitions
46 CLK_process :process
47 begin
48 CLK <= '0';
49 wait for CLK_period/2;
50 CLK <= '1';
51 wait for CLK_period/2;
52 end process;
53
54 SEL1process :process
55 begin
56 SEL(1) <= '0';
57 wait for 40 ns;

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 TB_ALU_8_BIT_BEH.vhd Wed Nov 05 19:17:28 2014
58 SEL(1) <= '1';
59 wait for 40 ns;
60 end process;
61
62 SEL0process :process
63 begin
64 SEL(0) <= '0';
65 wait for 20 ns;
66 SEL(0) <= '1';
67 wait for 20 ns;
68 end process;
69
70 stim_proc: process
71 begin
72 wait for Clk_period*1;
73 A <= "00010010";
74 B <= "00001010";
75 end process;
76 END;

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 BIN_MUL_UNSIGNED_BEH.vhd Wed Nov 05 19:18:05 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_UNSIGNED.ALL;
4 use IEEE.STD_LOGIC_ARITH.ALL;
5 use IEEE.NUMERIC_STD.ALL;
6
7 entity BIN_MUL_UNSIGNED_BEH is
8 Port ( CLK,START : in BIT;
9 Mplier : in std_logic_vector(3 downto 0);
10 Mcand : in std_logic_vector(3 downto 0);
11 Done : out BIT;
12 PRODUCT : out std_logic_vector (7 downto 0));
13 end BIN_MUL_UNSIGNED_BEH;
14
15 architecture Behavioral of BIN_MUL_UNSIGNED_BEH is
16 signal state: integer range 0 to 9;
17 signal ACC: std_logic_vector (8 downto 0);
18 alias M: std_logic is ACC(0);
19 begin
20 process(CLK)
21 begin
22 M <= ACC(0);
23 if (CLK' event and CLK='1') then
24 case state is
25 when 0 =>
26 if START='1' then
27 ACC(8 downto 4) <= "00000";
28 ACC(3 downto 0) <= Mplier(3 downto 0);
29 state <= 1;
30 end if;
31 when 1|3|5|7 =>
32 if (M='1') then
33 ACC(8 downto 4) <= ('0'& ACC(7 downto 4)) +('0' & Mcand);
34 state <= state + 1;
35 else
36 ACC <= ('0' & ACC(8 downto 1));
37 state <= state + 2;
38 end if;
39 when 2|4|6|8 =>
40 ACC <= ('0' & ACC(8 downto 1));
41 state <= state + 1;
42 when 9 =>
43 state <= 0;
44 end case;
45 end if;
46 end process;
47
48 Done <= '1' when state=9 else '0';
49 PRODUCT <= ACC(7 downto 0) when state=9;
50 end Behavioral;
51
52

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 TB_BIN_MUL_UNSIGNED_BEH.vhd Wed Nov 05 19:18:16 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_BIN_MUL_UNSIGNED_BEH IS
5 END TB_BIN_MUL_UNSIGNED_BEH;
6
7 ARCHITECTURE behavior OF TB_BIN_MUL_UNSIGNED_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT BIN_MUL_UNSIGNED_BEH
12 PORT(
13 CLK : IN BIT;
14 START : IN BIT;
15 Mplier : IN std_logic_vector(3 downto 0);
16 Mcand : IN std_logic_vector(3 downto 0);
17 Done : OUT BIT;
18 PRODUCT : OUT std_logic_vector(7 downto 0)
19 );
20 END COMPONENT;
21
22
23 --Inputs
24 signal CLK : BIT := '0';
25 signal START : BIT := '0';
26 signal Mplier : std_logic_vector(3 downto 0) := (others => '0');
27 signal Mcand : std_logic_vector(3 downto 0) := (others => '0');
28
29 --Outputs
30 signal Done : BIT;
31 signal PRODUCT : std_logic_vector(7 downto 0);
32
33 -- Clock period definitions
34 constant CLK_period : time := 10 ns;
35
36 BEGIN
37
38 -- Instantiate the Unit Under Test (UUT)
39 uut: BIN_MUL_UNSIGNED_BEH PORT MAP (
40 CLK => CLK,
41 START => START,
42 Mplier => Mplier,
43 Mcand => Mcand,
44 Done => Done,
45 PRODUCT => PRODUCT
46 );
47
48 -- Clock process definitions
49 CLK_process :process
50 begin
51 CLK <= '0';
52 wait for CLK_period/2;
53 CLK <= '1';
54 wait for CLK_period/2;
55 end process;
56
57 START_process :process

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 TB_BIN_MUL_UNSIGNED_BEH.vhd Wed Nov 05 19:18:16 2014
58 begin
59 START <= '0';
60 wait for CLK_period/2;
61 START <= '1';
62 wait;
63 end process;
64
65
66 Stim_process :process
67 begin
68 Mplier <= "1111";
69 Mcand <= "1111";
70 wait;
71 end process;
72 END;

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 BIN_MUL_SIGNED_BEH.vhd Wed Nov 05 19:18:29 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_UNSIGNED.ALL;
4 use IEEE.STD_LOGIC_ARITH.ALL;
5 use IEEE.NUMERIC_STD.ALL;
6
7 entity BIN_MUL_SIGNED_BEH is
8 Port ( CLK,START : in STD_LOGIC;
9 Mcand,Mplier : in STD_LOGIC_VECTOR (3 downto 0);
10 Product : out STD_LOGIC_VECTOR (7 downto 0);
11 Done : out STD_LOGIC);
12 end BIN_MUL_SIGNED_BEH;
13 architecture Behavioral of BIN_MUL_SIGNED_BEH is
14 signal state: integer range 0 to 9;
15 signal ACC: std_logic_vector (7 downto 0);
16 alias M: std_logic is ACC(0);
17
18 begin
19 process(CLK)
20 begin
21 if (CLK' event and CLK='1') then
22 case state is
23 when 0 =>
24 if START='1' then
25 ACC(7 downto 4) <= "0000";
26 ACC(3 downto 0) <= Mcand(3 downto 0);
27 state <= 1;
28 end if;
29 when 1|3|5 =>
30 if (M='1') then
31 ACC(7 downto 4) <= ACC(7 downto 4) + Mplier;
32 state <= state + 1;
33 else
34 ACC <= (ACC(7) & ACC(7 downto 1));
35 state <= state + 2;
36 end if;
37 when 2|4|6|8 =>
38 ACC <= (ACC(7) & ACC(7 downto 1));
39 state <= state + 1;
40 when 7 =>
41 if (M='1') then
42 ACC(7 downto 4) <= ACC(7 downto 4) - Mplier;
43 state <= 8;
44 else
45 ACC <= (ACC(7) & ACC(7 downto 1));
46 state <= 9;
47 end if;
48 when 9 =>
49 state <= 0;
50 end case;
51 end if;
52 end process;
53 Done <= '1' when state=9 else '0';
54 PRODUCT <= ACC(7 downto 0) when state=9;
55 end Behavioral;

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 TB_BIN_MUL_SIGNED_BEH.vhd Wed Nov 05 19:18:40 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_BIN_MUL_SIGNED_BEH IS
5 END TB_BIN_MUL_SIGNED_BEH;
6
7 ARCHITECTURE behavior OF TB_BIN_MUL_SIGNED_BEH IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT BIN_MUL_SIGNED_BEH
12 PORT(
13 CLK : IN std_logic;
14 START : IN std_logic;
15 Mplier : IN std_logic_vector(3 downto 0);
16 Mcand : IN std_logic_vector(3 downto 0);
17 Product : OUT std_logic_vector(7 downto 0);
18 Done : OUT std_logic
19 );
20 END COMPONENT;
21
22
23 --Inputs
24 signal CLK : std_logic := '0';
25 signal START : std_logic := '0';
26 signal Mplier : std_logic_vector(3 downto 0) := (others => '0');
27 signal Mcand : std_logic_vector(3 downto 0) := (others => '0');
28
29 --Outputs
30 signal Product : std_logic_vector(7 downto 0);
31 signal Done : std_logic;
32
33 -- Clock period definitions
34 constant CLK_period : time := 10 ns;
35
36 BEGIN
37
38 -- Instantiate the Unit Under Test (UUT)
39 uut: BIN_MUL_SIGNED_BEH PORT MAP (
40 CLK => CLK,
41 START => START,
42 Mplier => Mplier,
43 Mcand => Mcand,
44 Product => Product,
45 Done => Done
46 );
47
48 -- Clock process definitions
49 CLK_process :process
50 begin
51 CLK <= '0';
52 wait for CLK_period/2;
53 CLK <= '1';
54 wait for CLK_period/2;
55 end process;
56
57 START_process :process

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 TB_BIN_MUL_SIGNED_BEH.vhd Wed Nov 05 19:18:40 2014
58 begin
59 START <= '0';
60 wait for CLK_period/2;
61 START <= '1';
62 wait;
63 end process;
64
65 Stim_process :process
66 begin
67 Mcand <= "1100";
68 Mplier <= "0100";
69 wait;
70 end process;
71 END;

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 TRAFFIC_LIGHT_TWO_STREETS.vhd Thu Nov 06 20:50:30 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity TRAFFIC_LIGHT_TWO_STREETS is
5 Port ( CLK,Sa,Sb : in STD_LOGIC;
6 Ra,Rb,Ga,Gb,Ya,Yb : inout STD_LOGIC);
7 end TRAFFIC_LIGHT_TWO_STREETS;
8
9 architecture Behavioral of TRAFFIC_LIGHT_TWO_STREETS is
10 signal state: integer range 0 to 12;
11 type light is (R, Y, G);
12 signal lightA,lightB: light;
13 begin
14 process(clk,state,Ra,Rb)
15 begin
16 Ra <= '0';
17 Rb <= '0';
18 Ga <= '0';
19 Gb <= '0';
20 Ya <= '0';
21 Yb <= '0';
22 if (CLK' event and CLK='1') then
23 case state is
24 when 0 to 4 => Ga <='1';
25 Rb <='1';
26 state <= state + 1;
27
28 when 5 => Ga <='1';
29 Rb <='1';
30 if (Sb='1') then
31 state <= 6;
32 else
33 state <= 5;
34 end if;
35
36 when 6 => Ya <='1';
37 Rb <='1';
38 state <= 7;
39
40 when 7 to 10 => Ra <='1';
41 Gb <='1';
42 state <= state + 1;
43
44 when 11 => Ra <='1';
45 Gb <='1';
46 if (Sa='1' or Sb='0') then
47 state <= 12;
48 end if;
49
50 when 12 => Ra <='1';
51 Yb <='1';
52 state <= 0;
53 end case;
54 end if;
55 end process;
56 lightA <= R when Ra='1' else Y when Yb='1' else G when Ga='1';
57 lightB <= R when Rb='1' else Y when Yb='1' else G when Gb='1';

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 TRAFFIC_LIGHT_TWO_STREETS.vhd Thu Nov 06 20:50:31 2014
58 end Behavioral;
59
60

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 N_BIT_GTOB_BTOG.vhd Tue Nov 11 21:02:16 2014
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity N_BIT_GTOB_BTOG is
5 generic (n : integer := 4);
6 Port ( NUM : in STD_LOGIC_VECTOR ((n-1) downto 0);
7 SEL : in BIT;
8 Y : out STD_LOGIC_VECTOR ((n-1) downto 0);
9 GRAYCODE,BINARYCODE : out STD_LOGIC_VECTOR ((n-1) downto 0));
10 end N_BIT_GTOB_BTOG;
11 ---------------------------------------------------------
12 ----------if SEL is 1 then B TO G else G TO B------------
13 ---------------------------------------------------------
14 architecture DTFL of N_BIT_GTOB_BTOG is
15 signal A: std_logic_vector((n-1) downto 0);
16 begin
17
18 A(n-1) <= NUM(n-1);
19 A(n-2 downto 0) <= NUM(n-1 downto 1) xor NUM(n-2 downto 0) when SEL ='1'
20 else A(n-1 downto 1) xor NUM(n-2 downto 0 );
21 Y <= A;
22
23 GRAYCODE <= A WHEN SEL ='1' else NUM;
24 BINARYCODE <= NUM WHEN SEL ='1' else A;
25
26 end DTFL;

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 TB_N_BIT_GTOB_BTOG.vhd Tue Nov 11 21:04:13 2014
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY TB_N_BIT_GTOB_BTOG IS
5 END TB_N_BIT_GTOB_BTOG;
6
7 ARCHITECTURE behavior OF TB_N_BIT_GTOB_BTOG IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT N_BIT_GTOB_BTOG
12 PORT(
13 NUM : IN std_logic_vector(3 downto 0);
14 SEL : IN BIT;
15 Y : OUT std_logic_vector(3 downto 0);
16 GRAYCODE,BINARYCODE : out STD_LOGIC_VECTOR (3 downto 0));
17 END COMPONENT;
18
19
20 --Inputs
21 signal NUM : std_logic_vector(3 downto 0) := (others => '0');
22 signal SEL : BIT := '0';
23
24 --Outputs
25 signal Y : std_logic_vector(3 downto 0);
26 signal GRAYCODE : std_logic_vector(3 downto 0);
27 signal BINARYCODE : std_logic_vector(3 downto 0);
28
29 BEGIN
30
31 -- Instantiate the Unit Under Test (UUT)
32 uut: N_BIT_GTOB_BTOG PORT MAP (
33 NUM => NUM,
34 SEL => SEL,
35 Y => Y,
36 BINARYCODE => BINARYCODE,
37 GRAYCODE => GRAYCODE
38 );
39
40 BIT3:process
41 begin
42 NUM(3) <= '0';
43 wait for 1600 ns;
44 NUM(3) <= '1';
45 wait for 1600 ns;
46 end process;
47
48 BIT2:process
49 begin
50 NUM(2) <= '0';
51 wait for 800 ns;
52 NUM(2) <= '1';
53 wait for 800 ns;
54 end process;
55
56 BIT1:process
57 begin

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 TB_N_BIT_GTOB_BTOG.vhd Tue Nov 11 21:04:13 2014
58 NUM(1) <= '0';
59 wait for 400 ns;
60 NUM(1) <= '1';
61 wait for 400 ns;
62 end process;
63
64 BIT0:process
65 begin
66 NUM(0) <= '0';
67 wait for 200 ns;
68 NUM(0) <= '1';
69 wait for 200 ns;
70 end process;
71
72 SEL_LINE:process
73 begin
74 SEL <= '0';
75 wait for 100 ns;
76 SEL <= '1';
77 wait for 100 ns;
78 end process;
79
80 END;
81

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