A CMOS Bandgap Reference
A CMOS Bandgap Reference
A CMOS Bandgap Reference
1 , JANUARY 1991 41
Abstract -A switched-capacitor fully differential bandgap reference is BJT’s forces the sensing of the emitter instead of the collec-
presented that employs a standard double-poly CMOS process. It gener- tor currents, which in turn leads to errors caused by the
ates a differential reference voltage of 6.2 V with a standard deviation of
about 24 mV and a typical temperature stability of 15.2 ppm/”C over an finite current gains. The combination of these effects pre-
extended temperature range from - 40 to + 85°C. These performance vents the achievement of references with good accuracy and
results are obtained without using any trimming in mass production. temperature stability.
The bandgap reference only occupies 730 mil’ and dissipates 4.8 mW at An approach [ I l l that overcomes most of the limiting
k 5-V power supplies. A measured power supply rejection of about 90 dB factor of the CMOS bandgap implementation uses offset
until 500 k H z is the best ever reported at high frequency.
cancellation techniques, base current and base resistance
cancellation, and curvature compensation. Drawbacks of this
solution are the required double trimming (one for the value
I. INTRODUCTION of the absolute voltage of the uncompensated reference and
the other for tailoring the value of the curvature-compensa-
A KEY ELEMENT of analog-to-digital (A/D) and digi-
tal-to-analog (D/A) converters is a precise voltage ref-
erence with good temperature stability.
tion term), and the need for a complex circuit to generate all
the bias currents, thus consuming a large quantity of area
In bipolar technologies one of the most popular imple- and power.
mentations uses the extrapolated energy bandgap voltage of Other approaches utilize MOS transistors in weak inver-
silicon [11, [2]. Bandgap references using trimming techniques sion to produce a bipolar-like behavior and CMOS-compati-
and curvature compensation achieving high performance have ble lateral bipolar transistors, respectively [12]-[14]. Al-
been reported [3]-[6]. though these techniques avoid the limitation of the substrate
In MOS technologies, early implementations of voltage BJT regarding the access to the collector, the resulting
references were based on the difference between the thresh- references have poor power supply rejection (PSR) at audio
old voltages of enhancement- and depletion-mode MOS and above-audio frequencies, that is, from a few kilohertz to
transistors [7]. Although this technique leads to a low tem- 100 kHz; thus it is better to find other solutions for applica-
perature coefficient, as a solution it suffers in that the output tions where good PSRR is of great importance, such as
voltage is poorly controlled because of its direct dependence telephony or audioprocessing systems.
on the dose of ion-implantation steps. Another solution Fully differential circuits are a solution for many of the
exploits the gate voltage difference of two MOS transistors problems presented by the coexistence of massive portions of
of the same type but having polysilicon gates with opposite digital circuitry and high-performance analog interfaces.
doping and biased at identical drain currents [8]. The result- Power supply coupling, substrate coupling, single supply op-
ing voltage turns out to be close to the silicon bandgap. The eration, and high dynamic range are just a few of the
shortcomings of this solution are the need for an extra mask challenges encountered in the VLSI design arena. O p amps,
for selective doping of the polysilicon and a resulting voltage comparators, filters, and A / D and D / A converters are
with poor temperature stability. typical examples of circuits that can be implemented using
The trend of higher system integration coupled with the differential techniques [151-[171.
constant development efforts to reduce device dimensions This paper describes the design of a fully differential
have made CMOS the clear choice for VLSI implementa- CMOS bandgap reference having a very good PSRR with a
tions. Analog and digital subsystems are required to coexist range of u p to a few hundred kilohertz. The design demon-
on the same die sharing the same device resources. In order strates that it is possible to implement both high-precision
to take advantage of the bandgap technique in mixed-mode and temperature-stable bandgap voltage references without
systems 191, [lo], the presence of the parasitic bipolar struc- the use of any trimming in the mass production phase of the
ture in every CMOS process has been exploited. Unless integrated circuit. As will be seen, it is sufficient to deter-
certain precautions are taken, these circuits suffer from the mine the correct value of the output voltage using a “trim-
weaknesses encountered in CMOS circuits, e.g., high op-amp ming” procedure only during the design or the preproduc-
offset. Furthermore, the lack of access to the collector of the tion phases, for example, by exploiting the results of a test
pattern. Although the lack of trimming for curvature com-
pensation prevents the circuit in question from achieving
Manuscript received January 17, 1990; revised July 25, 1990. ultimate performance levels [Ill, the savings in area and
G. Nicollini is with the MOS Telecom Group, ST Microelectronics
SPA, 20041 Agrate Brianza, Italy. power coupled with the reduction of the production testing
D. Senderowicz is with SynchroDesign Inc., Berkeley, CA 94704-1210. time result in a favorable trade-off in large production envi-
IEEE L o g Number 9040724. ronments.
11. THEBANDCAP
REFERENCE
The operation of the bandgap voltage reference is based
I
(a)
n- substrate
COLLECTOR ( V o o 1
s
positive T C voltage is the difference of two emitter-base
voltages biased at different current densities. In a conven-
tional CMOS process it is possible to use the parasitic n-wal I
substrate n-p-n or p-n-p transistors in the case of p-well and
n-well, respectively (Fig. 1). These transistors, unlike conven-
tional BJT's, have intrinsic limitations that can pose some p- substrate
problems in the development of high-performance voltage
references. One example of a typical bandgap realization in (b)[
c ksl
1
1I L, -
PI
AVBE= V, In A + V, 12
In - + V, In -
I1 1+-
P2
(3)
where VBE is the emitter-base voltage of Ql,AVBE is the
t3
difference between the emitter-base voltages of Q2 and
Q l , Vos is the op-amp input offset voltage, V , is the thermal
voltage k T / q , I , and I, are the emitter currents of Ql and
Q2, respectively, I,, is the saturation current, P , and P 2 are
R2 i
the dc current gains of Q l and Q2, respectively, rb is the
base resistance, and A is the area factor between Q1
and Q2. Fig. 2. Example of a conventional CMOS bandgap reference with
The offset voltage is the main error source because it is associated nonidealities.
+
amplified by 1 R 2 / R , , leading to a large variation in the
output reference voltage and consequently to a very large
degradation of its temperature stability. The output voltage [ll]). This error term must be cancelled to ensure good
of a bandgap reference is generally trimmed to a predeter- reproducibility in the output TC.
mined value in order to give an ideally zero variation of the Fig. 3 depicts the solution utilized to remove the offset
output with respect to temperature. Therefore after the from the output voltage. In Fig. 3(a) the switched-capacitor
trimming operation, the resulting op-amp offset yields an bandgap reference is in the offset storage d1 phase while in
erroneous value, which further triggers a T C error that can Fig. 3(b) it is in the amplification and useful d2 phase. The
be very large (for example, with a typical amplification factor charge injected by switches SW1 and SW2 into the summing
of 10 this error is about 26 ppm/"C per millivolt of offset node ideally results in a common-mode signal, thus the
NICOLLINI AND SENDEROWICZ: CMOS BANDGAP REFERENCE 43
VDD * SWl-
I OP.AMP.
vss
I
.
+s w- 2 -
Q2
/I-'
vss
(b)
Fig. 3. Switched-capacitor bandgap reference. (a) Offset storage phase. (b) Amplification @ 2 phase.
differential output voltage is not affected by this clock- and cannot be eliminated by using any offset cancellation
related error term. A very small differential error may be techniques. This term has always been neglected in previous
present due to the mismatches of the switches, but as will be bandgap reference implementations (where it arised from
shown in the next section, this error is acceptable for our op-amp offset Vas, shown in Fig. 2 for example) because it
purposes. represents a fairly low error of about 1.3 ppm/"C per milli-
A second error term comes from the different current volt of offset on the TC of the output voltage, but assuming a
values I , and I,. In Fig. 3 this effect comes into play in 4a value of 25 mV for the offset, it is better to find a
conjunction with the offset between transistors M1 and M 2 solution in order to eliminate this error source.
44 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 1, JANUARY 1991
nate this error source. The currents I , and I,, which are
mirrored from a PTAT biasing circuit, can of course be
different because of the offset Vos, between the transistors
M1 and M 2 , but the “cross-coupled’’ switching formed by 0 2
M 3 - M 6 assures that VBEland V,,, are biased by the same
current even at different phases. This along with the switch- 1
“EEl
ing scheme of Fig. 3 allows the upper and the lower halves of
the bandgap reference to only ‘‘see’’ the currents I , and I , ,
respectively. 0
The complete circuit operation and the effect of offsets “EEa
VR, =-
2
$L$j$ vEl
v ss
=c,-vos
2
+ ( C , +C,) -vi,, + -
where VB)EI(V&A)and VE;IE1(VgrEA)
2 i
are the values of
1 Fig. 4. Offset independent V,, biasing circuit.
Cl I c2
= -VT In - + -V, In A
c3 Is, c
3
Cl I c 2
= - -VT In - - -V , In A
c
3 Is, c
3
I
= VT In -
10Iss
NICOLLINI AND SENDEROWICZ: CMOS BANDGAP REFERENCE 45
VDD
(;I )
*Another potential error factor is due to the charge mis- dummy-plate guard ring, etc.) and choosing geometries of
match between switches SW1 and SW2 of Fig. 3 in the 40 x 40 p m ' for unit capacitor size, the mismatch is less than
amplification phase. If we consider that half the switch 0 1% [20]. These combined effect\ are reflected in a refer-
charge is injected into the op-amp inputs and model this ence output change of about 0.17%.
effect by a capacitor C , , (that is, a very simple model of The total relative error on the voltage value of the bandgap
charge sharing), it can be shown that reference can be obtained from the last result and from (9),
(10). (12), and (13):
1 LC,,.
dV,,, =- ~ Vc,,rk = 1.5 mV ( 13)
1 + C, C.SW
C.SH,
if W = 4 p m and L = 4 p m for the reset switches, C, = 1 pF, which means an accuracy of about f0.07 dB in the worst
and considering a maximum mismatch of S%. case.
*Finally, the precision of the output voltage is directly The degradation of TC due to process variations, assuming
related to the op-amp open-loop gain value and to the that (13) is independent from temperature in the first order,
mismatch of capacitor ratio C , to C2. becomes approximately
A simulated minimum open-loop gain of 40 000 leads to a
0.07% error on the output accuracy. By exploiting known
techniques [191 to minimize systematic errors on capacitor for a temperature range of -40 to +85"C. Therefore, con-
ratios (array design with constant area-to-perimeter ratio. sidering that the absence of curvature correction leads to a
NICOLLINI AND SENDEROWICZ. CMOS BANDGAP REFERENCE 41
INCM+ INCM-
vs s
(C)
Fig. 5. Op-amp schematic: (b) CMFB circuit, and (c) biasing circuit for CMFB inputs.
TC of about 17 ppm/"C in the above temperature range, the where V z and V< are the power supply noise superimposed
worst possible T C of the proposed bandgap reference is: to V,, and Vss, respectively, g m p l is the BJT transconduc-
TC,,, = 37 ppm/"C tance, and go(,, and goMl are the output conductances of
C, and C, and the cascoded pair M , and M , , respectively.
for a temperature range of -40 to +85"C. To analyze the VE,,effect on the reference output during
These calculated results are quite Satisfactory for PCM
codec filter chips, where this reference is used, and for most
the useful phase +,,
we can use charge balancing equations:
high-performance audioprocessing IC's. c, c2 c2
V&F,,( t, = -VE,,( t, +- - -VE,,(t 1)
c
3 c3 c3
IV. POWERSUPPLY REJECTION (PSR) OF THE
BANDGAP REFERENCE
The biasing currents I , and I , present a very large PSR
due to the choice of the poly resistor for determining the
PTAT current. In addition, VEEland VEE,,of the parasitics
BJT's are referred to ground producing a high decoupling of where V E J t l )is the sampled value of VE,,at the end of the
the power supply variations and noise. In fact, for frequen- + I phase and VE,$t)are the "continuous" values of VE,
cies much less than the f , of the BJT's, the power supply
during the 4, phase.
noise coupling VE,,is approximately given by Other power supply noise couplings at the bandgap output
can only arise from switch and op-amp mismatches since the
common-mode noise is rejected by the differential nature of
the reference voltage processing.
48 IEEE J O U R N A L Of- SOLID-ST.ZTE CIRCUITS, VOL. 26. NO. 1, J A N U A R Y 1991
typically 4.8 mW with +5-V power supplies. The switched-capacitor fully differential CMOS bandgap
Fig. 7 shows the output waveform of the switched-capaci- reference described in this paper was realized without the
tor bandgap reference. A clock period of 125 ps was used. use of any trimming during mass production. In a tempera-
which gives to the dl and +2 phases a logical '.high" period ture range of -40 to +85"C and with power supplies of
of 7.8125 and 117.1875 p s , respectively. once the disoverlap- k 5 V f 5%. it is capable of achieving a worst-case absolute
ping time is subtracted. accuracy and temperature drift of 0.1 1 dB and 40.3 ppm/"C,
In Table I. statistical data from more than 10000 PCM respectively .
codec chips are presented. Temperature coefficients are Smaller area and lower power dissipation in comparison to
given for an extended temperature range from - 40 to + 85°C previous solutions. combined with a very good power supply
and for k 5-V k 5% power supplies. rejection even at high frequency, makc this handgap suitable
NICOLLINI AND SENDEROWICZ: ChnOS BANDGAP REFERENCE 49
1 +0.002
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