Programmable Logic: Adapted From Slides by R. H. Katz
Programmable Logic: Adapted From Slides by R. H. Katz
Inputs
Outputs
PALs and PLAs
Key to Success: Shared Product Terms
Equations
F0 = A + B' C'
Example: F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:
1 = asserted in term
Personality Matrix
0 = negated in term
Product Inputs Outputs - = does not participate
term A B C F0 F1 F2 F3
Output Side:
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1 Reuse 1 = term connected to output
of 0 = no connection to output
AC 1 - 0 0 1 0 0
terms
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1
PALs and PLAs
Example Continued
Short-hand notation
so we don't have to
draw all the wires!
A
F1 = A B C
B
F2 = A + B + C C
A
F3 = A B C
B
F4 = A + B + C C
ABC
F5 = A xor B xor C
ABC
F6 = A xnor B xnor C ABC
ABC
ABC
ABC
ABC
F1 F2 F3 F4 F5 F6
PALs and PLAs
What is the difference between Programmable Array Logic (PAL) and
Programmable Logic Array (PLA)?
00 0 1 X 0 00 0 0 X 1
01 0 1 X 0 01 1 0 X 0
Minimized Functions: D D
11 1 1 X X 11 0 1 X X
C C
W=A+BD+BC 10 1 1 X X 10 1 0 X X
X = B C'
Y=B+C B B
Z = A'B'C'D + B C D + A D' + B' C D' K-map for Y K-map for Z
PALs and PLAs
Programmed PAL:
ABCD
\A \A
A 1
\B
4
\C
B D
2 3 W
D
B
C 3
B 2
C D
4 4 Z
A
5
B D 1 \D
22 1 X \B
C 1
C 3
\C \D
A A
AB AB
ABCD
CD 00 01 11 10 CD 00 01 11 10
00 1 0 0 0 00 0 1 1 1 ABCD
01 0 1 0 0 01 1 0 1 1 ABCD
D D
11 0 0 1 0 11 1 1 0 1 ABCD
C C
10 0 0 0 1 10 1 1 1 0 AC
B B AC
K-map for EQ K-map for NE
BD
A A BD
AB AB
CD 00 01 11 10 CD 00 01 11 10
ABD
00 0 0 0 0 00 0 1 1 1
BCD
01 1 0 0 0 01 0 0 1 1
D D ABC
11 1 1 0 1 11 0 0 0 0
C C BCD
10 1 1 0 0 10 0 0 1 0
B B
K-map for LT K-map for GT
EQ NE LT GT
PALs and PLAs
active-low output
• PAL16L8 I1 O1
I2 I/O1
I3
I/O2
I4
I5 I/O3
Programmable
AND array
I6 I/O4
I7
I/O5
I8
I9 I/O6
I10 O2
PALs and PLAs
• Advanced PAL Architectures
Programmable Output Polarity/XOR PALs
CLK OE
input 1 OLMC
input 2 ... input/output 1
. E2CMOS
. ... OLMC input/output 2
programmable
. AND array .
.
.
from
programmable 1-of-4
array multiplexer I/O
flip-flop
S1 S0
to 1-of-2
programmable multiplexer
array
OLMC
S1
• GAL16V8
– can emulate a number of PALs
OE
MUX
VCC
XOR
MUX
combinational configuration
Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
n
2 -1
Bit Lines
0 n-1
Address
Internal Organization
Read-Only Memories
Example: Combination Logic Implementation
A B C F0 F1 F2 F3
address outputs
Read-Only Memories
n address m output
lines lines
ROM problem: size doubles for each additional input, can't use don't cares