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Homework #4: EE 382M VLSI Testing Homework #4

This document contains homework problems about VLSI testing. Problem 1 involves calculating the number of clock cycles needed to test a circuit using external testers with different scan chain configurations and numbers of channels. Problem 2 calculates clock cycles to test a chip on a board using boundary scan with and without bypass mode. Problem 3 calculates expected fault coverage for a circuit using different numbers of pseudo-random patterns. Problem 4 uses a cutting algorithm to find the tightest probability range for a signal in a combinational logic circuit.

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44 views

Homework #4: EE 382M VLSI Testing Homework #4

This document contains homework problems about VLSI testing. Problem 1 involves calculating the number of clock cycles needed to test a circuit using external testers with different scan chain configurations and numbers of channels. Problem 2 calculates clock cycles to test a chip on a board using boundary scan with and without bypass mode. Problem 3 calculates expected fault coverage for a circuit using different numbers of pseudo-random patterns. Problem 4 uses a cutting algorithm to find the tightest probability range for a signal in a combinational logic circuit.

Uploaded by

siew
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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EE 382M VLSI Testing Homework #4

Homework #4

Problem 1:

Consider a circuit with 30 primary inputs, 25 primary outputs, and a scan chain of length 
200.
(A)  How many clock cycles would it take to test this circuit with 100 test vectors 
using an external tester?  Assume the tester directly connects to the primary input and 
primary output pins.
(B)  If the scan chain was broken into four scan chains of length 50 each (instead of 
one long one of length 200), how many clock cycles would it take to test this circuit with 
100 test vectors using an external tester?  Assume the tester directly connects to the 
primary input and primary output pins, and that the tester has 4 scan channels.
(C)  If the scan chain was broken into four scan chains where the lengths are 30, 70, 
40, and 60, how many clock cycles would it take to test this circuit with 100 test vectors 
using an external tester?  Assume the tester directly connects to the primary input and 
primary output pins, and that the tester has 4 scan channels.
(D)  Now assume there is a boundary scan around the primary inputs and outputs 
(connected as one long chain with 55 boundary scan elements), and that the internal scan 
chain is one long chain with 200 elements.  How many clock cycles would it take the 
tester to test this circuit with 100 test vectors using the boundary scan to access the 
primary inputs and primary outputs.  Assume the tester has one channel for the internal 
scan chain and one channel for the boundary scan chain.
(E)  Assume there is a boundary scan around the primary inputs and outputs 
(connected as one long chain with 55 boundary scan elements), and that the internal scan 
chain is broken into four scan chains of length 50 each, how many clock cycles would it 
take the tester to test this circuit with 100 test vectors using the boundary scan to access 
the primary inputs and primary outputs.  Assume the tester has four channels for the 
internal scan chains and one channel for the boundary scan chain.

Problem 2:

Consider a board with 4 chips having boundary scan.  The boundary scan is configured in the
following order:  Chip 1, Chip 2, Chip 3, Chip 4.

8/31/18 1
EE 382M VLSI Testing Homework #4

(A)  Assume four Chips have 100 boundary scan elements in them.  How many clock 
cycles will it take to test Chip 3 with 100 test vectors.  Assume the boundary scan does 
not have a bypass mode.
(B)  If the boundary does have a bypass mode, how many clock cycles will it take to 
test Chip 3 with 100 test vectors.

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EE 382M VLSI Testing Homework #4

Problem 3:

Consider a 18­input circuit that has 200 faults.  The following is the detectability profile for 
the lowest detectability faults:

k = (30, 72, 186, 452)
Hk = (1, 1, 1, 6)

(A) What is the expected fault coverage if 1000 pseudo­random patterns are used to test it?
(B) What is the expected fault coverage if 10000 pseudo­random patterns are used to test it?

Problem 4:

a & j
h
b
c
& g + m
e
i &
f k
d

For equiprobable random patterns, use the cutting algorithm to find the tightest range (cut the 
loops in all possible ways to obtain the smallest range) for the signal probability for m.

8/31/18 3

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