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Introduction To Vlsi: 1.1 Verilog

VLSI combines thousands of transistors into a single integrated circuit chip, allowing complex functions to be performed on one chip. It began development in the 1970s and enabled the microprocessor. VLSI design involves multiple levels from specifications through synthesis and layout. Verilog is a hardware description language like a programming language that can compactly describe large circuits. A Verilog design has a module hierarchy with modules communicating through ports. Modules contain nets, variables, statements and other module instances. Behavioral modeling at the highest level abstractly describes an algorithm without hardware details using statements like initial and always.

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79 views3 pages

Introduction To Vlsi: 1.1 Verilog

VLSI combines thousands of transistors into a single integrated circuit chip, allowing complex functions to be performed on one chip. It began development in the 1970s and enabled the microprocessor. VLSI design involves multiple levels from specifications through synthesis and layout. Verilog is a hardware description language like a programming language that can compactly describe large circuits. A Verilog design has a module hierarchy with modules communicating through ports. Modules contain nets, variables, statements and other module instances. Behavioral modeling at the highest level abstractly describes an algorithm without hardware details using statements like initial and always.

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hfytdyj
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INTRODUCTION TO VLSI

Very large scale integration (VLSI) is the process of creating an integrated circuit (IC)
by combining thousands of transistors into a single chip. VLSI began in the 1970s
when complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device. Before the introduction of VLSI technology, most
ICs had a limited set of functions they could perform. An electronic circuit might consist
of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into
one chip.

The various levels of design are numbered and the blocks show processes in the
design flow. Specifications comes first, they describe abstractly, the functionality,
interface, and the architecture of the digital IC circuit to be designed. Behavioral
description is then created to analyze the design in terms of functionality, performance,
compliance to given standards, and other specifications. RTL description is done using
HDLs. This RTL description is simulated to test functionality. From here onwards we
need the help of EDA tools. RTL description is then converted to a gate-level net-list
using logic synthesis tools. A gate level net-list is a description of the circuit in terms of
gates and connections between them, which are made in such a way that they meet
the timing, power and area specifications. Finally, a physical layout is made, which will
be verified and then sent to fabrication.

1.1 VERILOG
Hardware description languages such as Verilog are similar to software programming
languages because they include ways of describing the propagation time and signal
strengths (sensitivity). There are two types of assignment operators a blocking
assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment
allows designers to describe a state-machine update without needing to declare and
use temporary storage variables. Since these concepts are part of Verilog's language
semantics, designers could quickly write descriptions of large circuits in a relatively
compact and concise form.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design


hierarchy, and communicate with other modules through a set of declared input, output,
and bidirectional ports. Internally, a module can contain any combination of the

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following: net/variable declarations (wire, reg, integer, etc.), concurrent and
sequential statement blocks, and instances of other modules (sub-hierarchies).
Sequential statements are placed inside a begin/end block and executed in sequential
order within the block. However, the blocks themselves are executed concurrently,
making Verilog a dataflow language.

1.2 BASICS CONCEPTS


The basics block of Verilog programing is:

Modules: A module is the basic building block in Verilog. A module can be an element
or a collection of lower-level design blocks. Typically, elements are grouped into
modules to provide common functionality that is used at many places in the design. A
module provides the necessary functionality to the higher-level block through its port
interface (inputs and outputs), but hides the internal implementation. This allows the
designer to modify module internals without affecting the rest of the design.

Syntax:
module <module-name> (<module-terminal-list>) ;
<module internals ...
...
endmodule

1.3 TYPES OF MODELING


Gate level :
The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level logic
diagram.

Dataflow :
At this level the module is designed by specifying the data flow. The designer is aware
of how data flows between hardware registers and how the data is processed in the
design.

Behavioral :

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This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the hardware
implementation details. Designing at this level is very similar to C programming.

Basics blocks of behavioral type of modeling:


Initial statement:
The initial statement is executed only once during a simulation, beginning at time 0 and
then suspends forever. An initial statement provides a method to initialize and monitor
variables before the variables are used in a module.
Syntax:
initial [optional timing control]
procedural statement or
block of procedural statements

Always statement:
The always statement executes the behavioral statements within the always block
repeatedly in a looping manner and begins execution at time zero. Execution of the
statements continues indefinitely until the simulation is terminated.
Syntax:
always [optional timing control]
procedural statement or
block of procedural statements

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