Harmonic Limiting Standards

and Power Factor Correction

Techniques

P. Tenti and G. Spiazzi

Department of Electronics and Informatics

University of Padova
Via Gradenigo 6/a, 35131 Padova - ITALY
Phone: +39-49-8277503 Fax: +39-49-8277599
e-mail:
[email protected]
[email protected]
6th European Conference on Power Electronics and Applications - EPE '95

OUTLINE

- BASICS OF POWER FACTOR CORRECTION

- REVIEW OF HARMONIC STANDARDS

- BASICS OF SINGLE-PHASE PFC TOPOLOGIES AND

CONTROL

- CONTROL TECHNIQUES FOR SINGLE-PHASE PFC'S AND

COMMERCIAL CONTROL IC'S

- INSULATED TOPOLOGIES

- TECHNIQUES FOR IMPROVING OUTPUT VOLTAGE

CONTROL SPEED

- BASICS OF SOFT-SWITCHING TECHNIQUES

- SMALL-SIGNAL MODELING

- SINGLE-PHASE APPLICATION EXAMPLES

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6th European Conference on Power Electronics and Applications - EPE '95

POWER FACTOR DEFINITION

Input voltage and current are periodic waveforms with period Ti.

Power factor PF:

P
PF ≡
Vi,rms ⋅ I i,rms

where P is the average power:

1
P = ⋅ ò v i i i dt
Ti T i

and Vi,rms and Ii,rms are :

1 1
Vi, rms ≡ ò i dt I i, rms ≡ ò i dt
2 2
v i
Ti Ti
Ti Ti

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POWER FACTOR DEFINITION

Being voltage and current periodic waveforms we can write in

Fourier series:
∞
v i = V0 + å 2Vk sin (kωi + φ k )
k =1
∞
i i = I 0 + å 2I k sin (kωi + γ k )
k =1

V0 , I0 = average values
Vk , Ik = RMS values of harmonics

The average power is:

P = V0 I 0 + å Vk I k cos(φ k − γ k )

CONSEQUENCE:
Current harmonic terms contributes to active power only in the
presence of voltage harmonic terms of the same frequency.
POWER FACTOR DEFINITION

0 ≤ PF ≤ 1

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PF = 1 only if current and voltage are proportional

Power Factor Correction

An ideal Power Factor Corrector (PFC) takes from the supply a

current which is proportional to the supply voltage

vi
R em = emulated resistance
ii

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POWER FACTOR DEFINITION

PARTICULAR CASE: SINUSOIDAL INPUT VOLTAGE

V1 I 1 cos(φ1 )
⋅ cos(φ1 )
I1
PF = =
V1 ⋅ I i ,rms I i,rms

Il
D. F.= = DISTORTION FACTOR
I i,rms

cos(φ1) = DISPLACEMENT FACTOR

I i,rms − I1
2 2
1
D.F. = , THD =
1 + (THD )
2 I1

(THD = Total Harmonic Distortion)

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POWER FACTOR REQUIREMENTS

PF = 1 implies:

o zero displacement between voltage and current fundamental

component (φ1 = 0)

o zero current harmonic content

EXAMPLES:

cos(φ1) = 0, D.F. ≠ 0

cos(φ1) ≠ 0, D.F. = 0

In both cases PF<1

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WHY POWER FACTOR CORRECTION

o Increased source efficiency

- lower losses on source impedance
- lower voltage distortion (cross-coupling)
- higher power available from a given source

o Reduced low-frequency harmonic pollution

o Compliance with limiting standards (IEC 555-2, IEEE 519 etc.)

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BASICS OF ACTIVE POWER FACTOR

CORRECTION

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POWER FACTOR CORRECTION TECHNIQUES

PASSIVE METHODS: LC filters

o power factor not very high

o bulky components

o high reliability

o suitable for very small or high power levels

ACTIVE METHODS: high-frequency converters

o high power factor (approaching unity)

o possibility to introduce a high-frequency insulating transformer

o layout dependent high-frequency harmonics generation (EMI

problems)

o suitable for small and medium power levels

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ACTIVE POWER FACTOR CORRECTION

DEFINITION:

Power Factor Corrector (PFC):

AC/DC converter with sinusoidal current absorption
(Current Proportional To Supply Voltage)
v i = Vi sen (ϑ)
i i = I i sen (ϑ),ϑ = ωi t

The converter behaves like an equivalent resistance Rem given by:

Vi
R em =
Ii

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ACTIVE POWER FACTOR CORRECTION:

BASIC CONSIDERATIONS

Input power:
p i (ϑ) = v i (ϑ) ⋅ i i (ϑ) = 2 ⋅ Vi,rms I i,rms sin 2 (ϑ) =
= Vi,rms I i,rms (1 − cos(2ϑ))

Considering unity efficiency:

Vi,rms ⋅ I i,rms = P = V ⋅ I

P = output power

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PFC WITH CAPACITIVE FILTER

ASSUMPTIONS:

o constant output voltage

o unity efficiency

o no low-frequency pulsating energy stored in the dc/dc stage

Þ p i (ϑ) = V ⋅ i ' (ϑ)

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PFC WITH CAPACITIVE FILTER

p i (ϑ)
i ′(ϑ) = = 2Isin 2 (ϑ)
V

i ' (ϑ) = average value of i' (ϑ) in a switching period

Voltage conversion ratio M':

i g (ϑ)
M ′(ϑ) =
V
=
v g (ϑ) i ′(ϑ)

Load seen by the dc/dc stage:

v g (ϑ)
R ′(ϑ) = = M ′(ϑ) ⋅ = M ′(ϑ)2 ⋅ R em
V 2

i ′(ϑ) i g (ϑ)

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PFC WITH CAPACITIVE FILTER

R ′(ϑ) =
R
2 ⋅ sin 2 (ϑ)
M ′(ϑ) =
M V
,M =
sin (ϑ) Vg

For a PFC we have:

R ′(ϑ)
= R em
M ′ (ϑ)
2

a dc/dc converter when used as rectifier operates as a PFC with

constant control if : M ′(ϑ) ∝ R ′(ϑ)

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PFC WITH CAPACITIVE FILTER

OUTPUT FILTER DESIGN

Output filter capacitor current:

i c (ϑ) = i ' (ϑ) − I = − I ⋅ cos(2ϑ)

If ∆V is the desired peak-to-peak output voltage ripple, then:

I
C≥
ω i ∆V

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PFC WITH INDUCTIVE FILTER

ASSUMPTIONS:

o constant output current

o unity efficiency

o no low-frequency pulsating energy stored in the dc/dc stage

p i (ϑ)
v ' (ϑ) = = 2Vsin 2 (ϑ)
I
v ' (ϑ) = average value of v ' (ϑ) in a switching period

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PFC WITH INDUCTIVE FILTER

Voltage conversion ratio M':

v ' (ϑ) i g (ϑ)
M ′(ϑ) = = = 2 M sin (ϑ)
v g (ϑ) I

Load seen by the dc/dc stage:

v ' (ϑ)
R ′(ϑ) = = 2 Rsin 2 (ϑ)
I

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POWER FACTOR CORRECTORS: STANDARD

CONFIGURATION

TWO STAGE PFC: CASCADE CONNECTION

PREREGULATORS: AC/DC converters with high power factor

and poor output voltage regulation

LOW EFFICIENCY: THE SAME POWER IS PROCESSED TWICE

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BASIC PREREGULATORS: BOOST TOPOLOGY

CHARACTERISTICS:

o Inherent input filter (low input current harmonic content)

o Simple topology

o high power factor

o Output voltage greater than peak input voltage

o no start-up or short circuit protection

o no high-frequency insulation

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BASIC PREREGULATORS: BOOST TOPOLOGY

CCM OPERATION

Assumption:

switching frequency much greater than line frequency

(quasi-stationary approach).

Main waveforms in a switching period

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BASIC PREREGULATORS: BOOST TOPOLOGY

OPERATION AS DC/DC CONVERTER

1
Voltage conversion ratio : M=
1− d
d = duty-cycle

OPERATION AS AC/DC CONVERTER

In order to draw a sinusoidal current the duty-cycle must be

modulated during the line period:
Vg sin (ϑ)
d (ϑ) = 1 −
V

(This is an approximation because CCM operation cannot

be maintained during the whole line period)

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BASIC PREREGULATORS: BUCK + BOOST

TOPOLOGY

CHARACTERISTICS:

o S1 and D1 provide start-up and short circuit protection

o buck-mode operation for vg higher than output voltage

and boost mode-operation for vg lower than output
voltage

o high conduction losses (four semiconductors in series)

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BASIC PREREGULATORS: FLYBACK TOPOLOGY

CHARACTERISTICS:

o Simple topology

o high power factor with constant duty-cycle in

Discontinuous Conduction Mode (DCM) operation

o inherent start-up and short circuit protection

o high-frequency insulation transformer

o high input current harmonic content

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BASIC PREREGULATORS: FLYBACK TOPOLOGY

DCM OPERATION

Main waveforms in a switching period

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BASIC PREREGULATORS: FLYBACK TOPOLOGY

DCM OPERATION

OPERATION AS DC/DC CONVERTER

d 2L
Voltage conversion ratio : M= , k=
k RTs
d = duty-cycle
L = transformer magnetizing inductance (primary side)
R = load resistance
Ts = switching period

M∝ R Þ automatic PFC when used as rectifier

OPERATION AS AC/DC CONVERTER

Average input current:

v g (ϑ)
i g (ϑ) = ⋅ d 2 Ts
L

At constant duty-cycle and switching frequency the input

current is sinusoidal

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CONTROL TECHNIQUES FOR SINGLE-PHASE

PFC'S AND COMMERCIAL CONTROL IC'S

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BOOST PREREGULATOR

PEAK CURRENT CONTROL

Input current waveform

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PEAK CURRENT CONTROL

CHARACTERISTICS:

o CONSTANT SWITCHING FREQUENCY

o CONTINUOUS CONDUCTION MODE (CCM) OPERATION

- low device current stresses

- low RMS current

- small EMI filter

o POSSIBILITY TO SENSE ONLY SWITCH CURRENT

- efficiency improvement

- possibility to implement a pulse-by-pulse current limit

o SUBHARMONIC OSCILLATIONS (for duty-cycle > 50%)

o LINE CURRENT DISTORTION (increases for high line

voltages, light load and high amplitude of compensating ramp)

o COMMUTATION NOISE SENSITIVITY

o HARD REVERSE RECOVERY OF FREEWHEELING DIODE

(increased commutation losses and EMI)

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PEAK CURRENT CONTROL

IDEAL REFERENCE CURRENT WAVEFORMS

3 I ref
I ref [A]
[A]
2
0.8

1
0.4

0 0
0 Ti 0 Ti

Vi=115Vrms Vi=230Vrms

DISTORTION REDUCTION TECHNIQUES

o ADDING A DC OFFSET TO CURRENT REFERENCE

(function of both line voltage and load current)

o PROGRAMMED DISTORTION CURRENT REFERENCE

- line dependent DC offset

- constant offset plus soft clamp

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CURRENT CLAMPING CONTROL

CHARACTERISTICS:

o VERY SIMPLE CONTROL STRUCTURE

o LINE CURRENT DISTORTION BELOW 10% FOR LIMITED

LOAD AND LINE VARIATIONS

o UNIVERSAL INPUT VOLTAGE OPERATION CANNOT BE

EASILY ACCOMPLISHED

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BOOST PREREGULATOR

AVERAGE CURRENT CONTROL

Input current waveform

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AVERAGE CURRENT CONTROL

CHARACTERISTICS:

o CONSTANT SWITCHING FREQUENCY

o CONTINUOUS CONDUCTION MODE (CCM) OPERATION

- low device current stresses

- low RMS current

- small EMI filter

o COMPLEX CONTROL SCHEME

- need of inductor current sensing

- need of a multiplier

o COMMUTATION NOISE IMMUNITY

o HARD REVERSE RECOVERY OF FREEWHEELING DIODE

(increased commutation losses and EMI)

o SEVERAL CONTROL IC's AVAILABLE

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BOOST PREREGULATOR

HYSTERETIC CURRENT CONTROL

Input current waveform

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HYSTERETIC CURRENT CONTROL

CHARACTERISTICS:

o WIDE SWITCHING FREQUENCY VARIATION

o CONTINUOUS CONDUCTION MODE (CCM) OPERATION

- low device current stresses

- low RMS current

- small EMI filter

o COMPLEX CONTROL SCHEME

- need of inductor current sensing

- need of a multiplier

o COMMUTATION NOISE SENSITIVITY

o HARD REVERSE RECOVERY OF FREEWHEELING DIODE

(increased commutation losses and EMI)

o SMALL INPUT CURRENT DISTORTION NEAR ZERO

CROSSING OF LINE VOLTAGE TO AVOID HIGH
SWITCHING FREQUENCY

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BOOST PREREGULATOR

BORDERLINE CONTROL
(Operation at the boundary between DCM and CCM)

Input current waveform

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BORDERLINE CONTROL

CHARACTERISTICS:

o AUTOMATIC PFC (CONSTANT SWITCH ON TIME)

o VARIABLE SWITCHING FREQUENCY (function of load

current and instantaneous line voltage)

o DISCONTINUOUS CONDUCTION MODE (DCM)

OPERATION

- high device current stresses

- high RMS current

- large EMI filter

- reduced switch turn on losses and increased turn off

losses

o SIMPLE CONTROL SCHEME

- no need for a multiplier (however some IC's make use

of it)

- need for sensing the instant of inductor current zeroing

o SOFT RECOVERY OF FREEWHEELING DIODE

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BOOST PREREGULATOR

DISCONTINUOUS CURRENT PWM CONTROL

Input current waveform

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DISCONTINUOUS CURRENT PWM CONTROL

CHARACTERISTICS:
o CONSTANT SWITCHING FREQUENCY

o DISCONTINUOUS CONDUCTION MODE (DCM)

OPERATION

- high device current stresses

- high RMS current

- large EMI filter

- reduced switch turn on losses and increased turn off

losses

o NO NEED OF CURRENT SENSING

o SIMPLE PWM CONTROL

o INPUT CURRENT DISTORTION (WITH BOOST

CONVERTER)

- distortion can be reduced by subtracting a fraction of

rectified line voltage from the error voltage or by
modulating the clock frequency with rectified line
voltage

o SOFT RECOVERY OF FREEWHEELING DIODE

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FLYBACK PREREGULATOR

DCM OPERATION

Input current waveform

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DCM OPERATION

CHARACTERISTICS:

o AUTOMATIC PFC (CONSTANT SWITCH ON TIME)

o CONSTANT SWITCHING FREQUENCY

o DCM OPERATION

- high device current stresses

- high RMS current

- large EMI filter

- reduced switch turn on losses and increased turn off

losses

o NO NEED OF CURRENT SENSING

o SIMPLE PWM CONTROL

o SOFT OF RECOVERY OF FREEWHEELING DIODE

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FLYBACK PREREGULATOR

CCM OPERATION - CHARGE CONTROL

Main waveforms

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CCM OPERATION - CHARGE CONTROL

CHARACTERISTICS:

o CONSTANT SWITCHING FREQUENCY

o CONTINUOUS CONDUCTION MODE (CCM) OPERATION

- low device current stresses

- low RMS current

- relatively large EMI filter (current ripple is small, but

input current is discontinuous)

o SUBHARMONIC OSCILLATIONS (for duty-cycle > 50%)

o COMPLEX CONTROL SCHEME

- need of inductor current sensing

- need of a multiplier

o COMMUTATION NOISE IMMUNITY

o HARD REVERSE RECOVERY OF FREEWHEELING DIODE

(increased commutation losses and EMI)

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CONTROL IC'S

Constant frequency peak ML4812 (Micro Linear)

current control TK84812 (Toko)
Constant frequency UC1854/A/B family (Unitrode)
average current control UC1855 (Unitrode)
TK3854A (Toko)
ML4821 (Micro Linear)
TDA4815, TDA4819 (Siemens)
TA8310 (Toshiba)
L4981A/B (SGS-Thomson)
LT1248, LT1249 (Linear Tech.)
Hysteretic control CS3810 (Cherry Semic.)
Borderline control TDA4814, TDA4816,
TDA4817, TDA4818 (Siemens)
SG3561 (Silicon General)
UC1852 (Unitrode)
MC33261,
MC33262(Motorola)
L6560 (SGS-Thomson)
Two stage PFC with UC1891/2/3/4 family (Unitrode)
average-current control ML4824, ML4826 (Micro Linear)
TK65030 (Toko)
Two stage PFC with ML4819 (Micro Linear)
peak-current control TK84819 (Toko)
Buck-boost constant ML4813 (Micro Linear)
frequency automatic
control

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INSULATED POWER FACTOR CORRECTOR

TOPOLOGIES

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

DCM OPERATION

Cuk converter

Sepic converter

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

DCM OPERATION

Inductor and diode current waveforms

during a switching period for a Sepic converter

DCM operation = diode current zeroes during switch turn off

interval

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

DCM OPERATION

Diode current = sum of inductor currents

CONSEQUENCE:

By choosing suitable values for inductors L1 and L2 it is possible to

obtain a low high-frequency input current ripple

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

Simulated waveforms of a Sepic preregulator

V
c1

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CUK PREREGULATORS
CHARACTERISTICS:

o CONSTANT SWITCHING FREQUENCY

o GOOD TRANSFORMER EXPLOITATION

o DCM OPERATION

- high device current stresses

- small EMI filter

- reduced switch turn on losses and increased turn off

losses

- soft diode turn off

o SIMPLE CONTROL SCHEME

- no need of current sensing

- no need of multiplier

o POSSIBILITY OF MAGNETIC COUPLING (REDUCTION OF

MAGNETIC STRUCTURE SIZE AND INPUT CURRENT
RIPPLE)

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SEPIC PREREGULATORS
CHARACTERISTICS:

o CONSTANT SWITCHING FREQUENCY

o POOR TRANSFORMER EXPLOITATION

o DCM OPERATION

- high device current stresses

- small EMI filter

- reduced switch turn on losses and increased turn off

losses

- soft diode turn off

o SIMPLE CONTROL SCHEME

- no need of current sensing

- no need of multiplier

o POSSIBILITY OF MAGNETIC COUPLING (REDUCTION OF

MAGNETIC STRUCTURE SIZE AND INPUT CURRENT
RIPPLE)

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

CCM OPERATION

EXAMPLE: Sepic converter with average current mode

control

PROBLEM: design of the inner current loop

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

CCM OPERATION

Transfer function between duty-cycle and input current:

I c D′ L′2 C1′ 2
1+ ′
L2 ⋅ s + ⋅s
G id (s ) = 2
DVD VD D D
⋅
D′ L′2 + D L1
2
æ L1 L′2 C1′ 2ö
s ⋅ çç1 + 2 ⋅ s ÷÷
è D′ L′2 + D L1
2
ø
where D'=1-D.

VD
APPROXIMATION: G id ( s ) ≈ VD depends on input voltage
sL1
V
(for the boost preregulator is: G id ( s ) ≈ , i.e. constant gain)
sL
Sepic Cuk
VD Vg + V n Vg + V n
I c I1 + I 2 I1 + n I 2
C1′ C1 Ca ⋅ n Cb
2

Ca + n Cb
2

L′2 L2 L2 n
2

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

CCM OPERATION

Transfer function plot

G id ( s )
60
dB

40
a)

20

b)
0

-20
1 10 100KHz
Frequency

∠G id ( s )
0
deg
a)

b)
-90

-180

-270
1 10 100KHz
Frequency

a) π=π/2, b) π=π/18

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PREREGULATORS BASED ON CUK AND SEPIC

CONVERTERS

CCM OPERATION
A damping Rd-Cd network across energy transfer capacitor
C1 is used to properly shape the transfer function
G id ( s )
60
dB

40
a)

20

b)
0

-20
1 10 100KHz
Frequency

∠G id ( s )
0
deg

a)

b)
-90

-180
1 10 100KHz
Frequency

a) π=π
π2, b) π=π
π/18

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INSULATED BOOST PREREGULATORS

FULL-BRIDGE BOOST CONVERTER

TWO-SWITCH BOOST CONVERTER

A coupling winding to the input inductor is added to implement

start-up and overload protection: during these conditions the
converter operates in flyback mode

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INSULATED BOOST PREREGULATORS

CHARACTERISTICS:

❏ DIFFICULT TRANSFORMER IMPLEMENTATION

- low leakage inductance is essential

❏ NEED OF A SUITABLE CLAMP CIRCUIT

❏ HIGH VOLTAGE STRESS IN THE TWO-SWITCH

IMPLEMENTATION

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PARALLEL RESONANT PREREGULATOR

OPERATION AS DC/DC CONVERTER

Voltage conversion ratio:

vp 1 f
M= = 2 , fn =
vg π j fr
⋅ 1 − fn + ⋅ fn
2
8 Q
1 Cp
fr = , Q=R
2π L r C p Lr

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PARALLEL RESONANT PREREGULATOR

GAIN CHARACTERISTICS

M 5
Q=5
4
4

3
3

2
2

1
1

0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
fn

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PARALLEL RESONANT PREREGULATOR

OPERATION AS AC/DC CONVERTER

R ' (θ)
Q(θ) =
R 1
= ⋅
Zr 2sin 2 (θ) Z r

Q factor variation during a half line cycle

20

Qmin=2
16

12
Q( θ)
8

0
0 π π
2
θ
❏ Near the zero crossing the circuit is lightly damped
Ø HIGH GAIN
❏ Near the peak of ac line the circuit is heavily damped
Ø LOW GAIN

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PARALLEL RESONANT PREREGULATOR

OPERATION AS AC/DC CONVERTER

CONSEQUENCE:

Good power factor (>90%) is obtained without active

control of the line current.

NOTE:
The same result holds also for the series/parallel (LCC) resonant
converter. For this converter, an active control is necessary to
maintain zero voltage switching condition (operation must remain on
the right side of resonant peaks in all operating conditions)

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FAST RESPONDING POWER FACTOR

CORRECTOR TOPOLOGIES

OBJECTIVES:

❏ COMPACTNESS

❏ HIGH POWER FACTOR

❏ TIGHT AND FAST OUTPUT VOLTAGE REGULATION

❏ HIGH-FREQUENCY INSULATION

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TWO STAGE PFC: PARALLEL CONNECTION

About 68% of input power goes directly to the output through stage
1, while stage 2 processes only 32% of input power

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TWO STAGE PFC: PARALLEL CONNECTION

Pi < P

• Boost converter controls power factor

• Forward converter regulates output
• CB stores energy
• CL is small

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TWO STAGE PFC: PARALLEL CONNECTION

Pi > P

• t2 controls power factor

• t3 regulates output

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SINGLE STAGE PFC: PARALLEL POWER

PROCESSING

o need for several switches

o complex control

o discontinuous input current at least for a part of the line cycle

(large EMI filter)

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SINGLE STAGE PFC: PARALLEL POWER

PROCESSING

EXAMPLE: FLYBACK CONVERTER

Pi < P

• t2 controls power factor

• t1 regulates output
• CB stores energy
• CL is small

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SINGLE STAGE PFC: PARALLEL POWER

PROCESSING

EXAMPLE: FLYBACK CONVERTER

Pi > P

• t1 controls power factor

• t2 regulates output

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SINGLE STAGE PFC: BIFRED

(Boost Integrated with Flyback Rectifier/Energy storage/DC-DC

converter)

Main waveforms

• DCM input current ensures high power factor

• duty-cycle regulates output
• CB stores energy
• CL is small
SINGLE STAGE PFC: BIBRED
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(Boost Integrated with Buck Rectifier/Energy storage/DC-DC

converter)

Main waveforms

• DCM input current ensures high power factor

• duty-cycle regulates output
• CB stores energy
• CL is small

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SINGLE STAGE PFC: BIFRED, BIBRED

CHARACTERISTICS:

o DCM OPERATION

- high device current stresses

- big EMI filter

o TANK CAPACITOR VOLTAGE VB IS LOAD AND LINE

DEPENDENT

- high device voltage stresses

- limited load range

SOLUTIONS:

o VARIABLE FREQUENCY CONTROL

- trade-off between voltage stress and frequency range of

control

o DISCONTINUOUS OUTPUT CURRENT OPERATION

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SINGLE STAGE PFC: S2IP2 FAMILY

(Single-Stage Isolated Power-factor corrected Power supplies)

COMBINING SWITCHES

a) when the off voltages are the same

b) when the off voltage of the left switch is always higher than the
off voltage of the right switch
c) when the off voltage of a switch can be higher or lower than
the off voltage of the other switch

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SINGLE STAGE PFC: S2IP2 FAMILY

EXAMPLE: BOOST+FLYBACK

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SINGLE STAGE PFC: S2IP2 FAMILY

CHARACTERISTICS:

o SINGLE POWER STAGE WITH SINGLE HIGH-SPEED

CONTROL LOOP (PWM CONTROL)

o TANK CAPACITOR VOLTAGE VB INDEPENDENT OF LOAD

CURRENT

o DCM OPERATION OF BOTH PFC AND CURRENT-FED

DC/DC CONVERTER STAGES

- high device current stresses

- big EMI filter

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SINGLE STAGE PFC: DITHER RECTIFIERS

CONCEPT

Adding to the low-frequency input signal a high-frequency signal

with amplitude higher than VB increases the conduction interval of
the dead-zone element (diode-capacitor rectifier)

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SINGLE STAGE PFC: DITHER RECTIFIERS

EXAMPLE: VOLTAGE DOUBLER + HALF-BRIDGE CONVERTER

The connection is moved from point A to point B. In this way, the

high-frequency signal present on the inverter leg is added to the
input voltage. An inductor is needed to smooth the input current.

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SINGLE STAGE PFC: DITHER RECTIFIERS

EXAMPLE: VOLTAGE DOUBLER + HALF-BRIDGE CONVERTER

CHARACTERISTICS:
o DCM OPERATION

- high device current stresses

- big EMI filter

o TANK CAPACITOR VOLTAGE VB IS LOAD AND LINE

DEPENDENT

- high device voltage stresses

- limited load range

o VARIABLE FREQUENCY CONTROL

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TECHNIQUES FOR IMPROVING OUTPUT

VOLTAGE CONTROL SPEED

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NATURE OF THE PROBLEM - 1

GOAL:

To improve the dynamic response of power factor preregulators by

manipulation of the output voltage feedback signal without

additional sensing and with limited increase of control complexity

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NATURE OF THE PROBLEM - 2

Output voltage behavior:

v (t ) = VDC + ∆v (t ) = VDC ⋅ sin (2ωi t )

P
−
2ω i CV

The voltage error signal contains a low-frequency ripple at twice the

line frequency

CONSEQUENCE:

the bandwidth of the voltage loop must be kept below the

line frequency in order to avoid input current distortion

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LINE FEEDFORWARD

The low-pass filter provides a voltage proportional to the RMS input

voltage which is squared and used in the multiplier to divide the
current reference

ß
this avoids heavy compensating actions by the voltage error
amplifier during line transients

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CONTROL SCHEME WITH NOTCH FILTER

A notch filter tuned at twice the line frequency is inserted in the

feedback path in order to remove the output voltage low-frequency

ripple from the feedback signal

COMMENTS:

❏ the filter must be well tuned with high quality factor

❏ the bandwidth is limited below twice the line frequency

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CONTROL SCHEME WITH SAMPLE & HOLD

By sampling the output voltage error signal at a rate equal to the

voltage ripple near zero crossing of the line voltage, the average

output voltage is sensed.

COMMENTS:

❏ a high power factor is maintained in both transient and

steady-state conditions

❏ the bandwidth is limited below twice the line frequency

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CONTROL SCHEME WITH RIPPLE

COMPENSATION
∆v (t ) = − ⋅ sin(2ωi t )
P
2ω i CV

The output voltage ripple is estimated and subtracted to the

feedback signal so that the error amplifier processes a ripple-free
signal

Under unity power factor condition, input power is given by:

ηP
p i (t ) = ηP − ⋅ cos(2ωi t )
2

where h is converter efficiency.

Error signal ∆v(t) can be estimated from input power signal through:

❏ Elimination of DC component
❏ Phase shifting of ninety degrees
❏ Multiplication by a proper gain

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CONTROL SCHEME WITH RIPPLE

COMPENSATION

G c (s ) = K c ⋅ s
COMMENTS:

❏ in the presence of distorted input voltage, network Gc(s) turns out

to be complicated

❏ a second multiplier is needed

❏ the bandwidth can be increased above twice the line frequency

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CONTROL SCHEME WITH "REGULATION BAND"

REGULATION BAND APPROACH TYPE 1

The current reference amplitude is kept constant as long as the

output voltage remains within a defined regulation band. When the
output voltage goes outside of this band a high gain controller
changes rapidly the current reference amplitude so as to bring the
output voltage back into the regulation band

COMMENTS:
❏ correct average output voltage is obtained only at nominal
condition in which the voltage ripple amplitude is equal to the
dead zone amplitude

❏ slow input current dynamic response at load step changes

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CONTROL SCHEME WITH "REGULATION BAND"

REGULATION BAND APPROACH TYPE 2

In order to overcome the problem represented by the steady-state

error on the output voltage of the previous control technique, a
low-bandwidth PI controller can be used which ensures stability and
no DC errors. When the output voltage goes outside the band, the
gain of the voltage error amplifier is increased in order to enhance
the corrective action

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COMPARISON OF CONTROL STRATEGIES

BOOST POWER FACTOR PREREGULATOR

TABLE 1 - Converter parameters

Vg=220VRMS V=380V fs=50kHz

L=2mH C=470µF P=600W

Error voltage amplifier transfer function

KI æ s ö
G v (s ) = ç
ç 1+ ÷
s è ω z ÷ø
TABLE 2 - Error voltage amplifier parameter values

S.C. N.F. S.H. B.#1 B.#2 R.C.

KI 8.8 73.4 8.7 100⋅Ka 8.8⋅Kd 223

ωz 69.2 188.5 62.8 166.7 69.2 354.4

(Ka=13.8, Kb=1, Kd=21.4)

S.C. = Standard Control N.F. = Notch Filter

S.H. = Sample & Hold B.#1 = Regulation Band TYPE 1
B.#2 = Regulation Band TYPE 2 R.C. = Ripple Compensation

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STANDARD CONTROL

LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)

[V]
VREF-Vo

[s]
Time
Output voltage error signal

[A]
ig

[s]
Time

Rectified input current

NOTCH FILTER
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LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)
[V]
VREF -Vo

[s]
Time
Output voltage error signal

[A]

ig

[s]
Time
Rectified input current

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SAMPLE & HOLD

LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)
[V]
VREF -Vo

[s]
Time
Output voltage error signal

[A]

ig

[s]
Time
Rectified input current

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REGULATION BAND TYPE 1

LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)
[V]
VREF -Vo

[s]
Time
Output voltage error signal

[A]

ig

[s]
Time
Rectified input current

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REGULATION BAND TYPE 2

LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)
[V]
VREF -Vo

[s]
Time
Output voltage error signal
[A]

ig

[s]
Time

Rectified input current

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RIPPLE COMPENSATION

LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER

AND VICE VERSA (SIMULATED RESULTS)
[V]
VREF -Vo

[s]
Time
Output voltage error signal

[A]
ig

[s]
Time
Rectified input current

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BASICS OF SOFT-SWITCHING
TECHNIQUES

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WHY SOFT TRANSITIONS?

o EMI (ELECTRO-MAGNETIC INTERFERENCE) REDUCTION

- compliance with EMC (Elettro-Magnetic Compatibility)
standards
- input filter size reduction

o INCREASE OF SWITCHING FREQUENCY

- converter size reduction
- fast dynamic (high loop bandwidth)

o INCREASE OF EFFICIENCY

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SOFT SWITCHING SOLUTIONS

o QUASI-RESONANT OR RESONANT TOPOLOGIES

- increased current and/or voltage stresses

- increased conduction losses (resonant components in

series with main power path)

- difficulties to maintain soft-switching condition for wide line

and load ranges

o AUXILIARY CIRCUIT

- "PWM like" current and voltage waveforms

- need of an auxiliary switch

- little increase of control complexity

- soft-switching condition easily maintained for wide line and

load ranges

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REVERSE RECOVERY PROBLEM IN BOOST

RECTIFIERS

o INCREASED SWITCHING LOSSES

o INCREASED EMI

o INCREASED DEVICE CURRENT STRESSES

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ZVT-PWM BOOST CONVERTER - 1

(ZVT: Zero Voltage Transition)

ASSUMPTIONS:
❏ constant boost inductor current during commutation

❏ constant output voltage

Main waveforms in a switching period

Sr

V
DS

IL

IS

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T0-T1)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T1-T2)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T2-T3)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T3-T4)

Sr

V
DS

IL

IS

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T4-T5)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T5-T6)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T
0 1 2 3 4 5 6

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ZVT-PWM BOOST CONVERTER - 1

PRINCIPLE OF OPERATION (T6-T0)

Sr

V
DS

IL

I
S

I
Lr

V
D

I
L

I
D

T T T T T T T T
0 1 2 3 4 5 6 0

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ZVT-PWM BOOST CONVERTER - 1

CHARACTERISTICS:

o SOFT-SWITCHING FOR BOTH MAIN SWITCH AND

RECTIFIER

o CONSTANT FREQUENCY OPERATION

o HIGH EFFICIENCY

o ZERO-CURRENT TURN ON OF THE AUXILIARY SWITCH

o HARD TURN OFF OF THE AUXILIARY SWITCH

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ZVT-PWM BOOST CONVERTER - 2

A "flying" capacitor C1 is added in order to achieve soft turn off of

the auxiliary switch.

Mode 1 (VC1max<V)

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ZVT-PWM BOOST CONVERTER - 3

An autotransformer is added in series to the resonant

inductor acting like a voltage source to bring the resonant

current to zero after the commutation

Þ Sr turns off at zero current

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SMALL-SIGNAL MODELING

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SMALL-SIGNAL MODEL OF A PFC

OPERATING IN CCM

Power balance: v i ⋅ ii = v 0 ⋅ i0
ì v i = Vi + v̂ i
where í (RMS values)
îi i = I i + î i
ì v 0 = V0 + v̂ 0
í
îi 0 = I 0 + î 0

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN CCM

Under PFC conditions the input current is sinusoidal and its RMS
value depends on control voltage Vc:
vi
ii = ⋅ v c
k
Substituting we obtain:
2
vi
⋅ v c = v 0 ⋅ i0
k

After perturbation and linearization (small-signal approximation):

2
i = 2Vi Vc ⋅ v + Vi ⋅ v − I 0 ⋅ v
0 kV0 i kV0 c V0 0
i = 2M ⋅ v + Vi ⋅ v − 1 ⋅ v
0 r0 i kM c r0 0
V0 V0
where M= , r0 =
Vi I0

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN CCM

In the same way, from the power balance, we obtain:

2
V
i = i ⋅ v + M
i ⋅ v i
k c r0

M ri gi r0 gf gc

V0 ro Vi V0 2M Vi
Vi M
2 k I0 ro kM

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN CCM

TRANSFER FUNCTION BETWEEN CONTROL VOLTAGE AND

OUTPUT VOLTAGE
rp
G vc (s ) =
v̂ 0
= gc ⋅
v̂ c 1 + sCrp
r0 ⋅ R L
rp =
r0 + R L

rp=RL/2 resistive load

rp=RL constant current load
rp=∞ constant power load

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN DCM
(FLYBACK, CUK, SEPIC)

Power balance: v i ⋅ ii = v 0 ⋅ i0
ì v i = Vi + v̂ i
where í (RMS values)
îi i = I i + î i
ì v 0 = V0 + v̂ 0
í
îi 0 = I 0 + î 0

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN DCM

Under PFC conditions the input current is sinusoidal and its RMS
value depends on duty-cycle δ:

Ts v i 2
ii = ⋅δ
2L eq

where Leq depends on converter topology.

Substituting we obtain:
2
v i Ts 2
⋅ δ = v 0 ⋅ i0
2L eq

After perturbation and linearization (small-signal approximation):

2 2
i = 2Vi Yi D ⋅ v + 2Vi Yi D ⋅ δ − I 0 ⋅ v
0 V0 i V0 V0 0
T
where Yi = s
2 Leq

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN DCM
2
i = 2Yi D ⋅ v + 2Vi Yi D ⋅ δ − 1 ⋅ v
0 M i M r0 0
V0 V0
where M= , r0 =
Vi I0

In the same way, from the power balance, we obtain:

i = 2V Y D ⋅ δ + D 2Y ⋅ v
i i i i i

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SMALL-SIGNAL MODEL FOR A PFC

OPERATING IN DCM

MODEL PARAMETERS

M ri gi r0 gf gc
V0 1 V0 2Yi D 2 2ViYi D
2DViYi
Vi D 2Yi I0 M M

FLYBACK CUK SEPIC

Leq L L1 ⋅ L2 L1 ⋅ L2
n 2 L1 + L2 L1 + L2
n=transformer turns ratio (N2/N1)

TRANSFER FUNCTION BETWEEN DUTY-CYCLE

AND OUTPUT VOLTAGE
rp
G v (s ) =
v̂ 0
= gc ⋅
ˆδ 1 + sCrp
r ⋅R
rp = 0 L
r0 + R L

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DESIGN OF BOOST PFC OPERATING IN

CCM WITH AVERAGE CURRENT MODE

CONTROL

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POWER STAGE SCHEME

' '
R D

i D
L

+
L
D1 D
2
Rp
1
+ J C
4
C V
f
Vin 1 C 0
f S Z
2 L

D D S Rp
3 4 R s
2 -

J J J J J
5 6
1 2 3

CHARACTERISTICS:

Input voltage: Vin = 90-260VRMS

Output voltage: Vo = 380V
Output power: Po = 600W
Switching frequency: fs = 70kHz

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POWER STAGE DESIGN

1) Inductor peak current (average value in a switching period)
Po = η ⋅ Pg
where η is converter efficiency
I L ⋅ V

η⋅
g
= Po Þ I = 2Po

(1)
2 L
ηV g
Worst case: minimum input voltage
2 ⋅ 600
I L = = 9.92 A
0.95 ⋅ 2 ⋅ 90

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POWER STAGE DESIGN

2) Input inductor value

Duty-cycle in CCM:
Vg (ϑ)
δ(ϑ) = 1 −
t on
,δ = ;ϑ = ωi t (2)
Vo Ts
Peak-to-peak input current ripple:
Vg (ϑ) Vg (ϑ)
∆i L (ϑ) = ⋅ t on = ⋅ δ(ϑ) (3)
L fs ⋅ L

The maximum ripple occurs at half the input voltage peak. From the
allowed ripple the input inductor value is found.
(example: relative ripple = 30% Þ L = 0.46 mH.

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POWER STAGE DESIGN

3) Output capacitor value

Io
C=
ω i ∆Vo (4)

where ∆Vo is the desired peak-to-peak voltage ripple and Io is the

output current.
(Example:
relative ripple <5% Þ C > 260 µF, we use C=470µF)

4) Switch peak current

∆i L (π 2 )
î s = Î L + = 10.9A (5)
2

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POWER STAGE DESIGN

5) Switch RMS current

RMS current is determined by first averaging the switch current over

a switching period and second averaging over the line period.
Neglecting the inductor current ripple we obtain:
I s,rms 1 1 4
≅ 2M − ⋅ (6)
Io 2 M 3π
Vo
where M = is voltage conversion ratio
Vg
Considering the minimum input voltage we obtain:
I s,rms = 5. 63A .
6) Freewheeling diode peak current (average value)
I D,avg = 2 ⋅ I o = 316
. A (7)

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CONTROL STAGE DESIGN

IC: SGS-THOMSON L4981A

COMPONENT VALUES

Vcc = 18V R7 = 3.3 kΩ R13 = 18 kΩ C4 = 100 nF

R2 = 150 kΩ R8 = 3.3 kΩ R14 = 5.6kΩ C5 = 1 nF
R3 = 1 MΩ R9 = 47 kΩ C6 = 68 pF
R4 = 560 kΩ R10 = 33 Ω C1 = 15 nF C7 = 10 µF
R5 = 33 kΩ R11 = 33 kΩ C2 = 220 nF C8 = 1 nF
R6 = 1.2 MΩ R12 = 1.5 MΩ C3 = 220 nF C9 = 10 µF

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CONTROL STAGE DESIGN

IC: SGS-THOMSON L4981A

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CONTROL STAGE DESIGN

1) Shunt resistance RS:

Choosing Rs = 0.054Ω the power loss is:

I L
2
PR S = R S ⋅ = 2. 65W (8)
2
2) Switching frequency:

C8 and R11 determine the switching frequency:

2. 4
fs = , hertz (9)
C 8 ⋅ R 11
Choosing C8=1nF gives R11=33kΩ

3 Reference current IAC:


V
=
g
I AC (10)
R6
The suggested value for R6 is 1.2MΩ. Correspondingly, IAC is
between 106µA at minimum line voltage and 306µA at maximum
line voltage.

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CONTROL STAGE DESIGN

4) Feedforward voltage VRMS:

R3, C3, R4, R5, C4 form a low pass filter which must give at pin 7 a
DC voltage between 1.5V and 6.5V. Suggested values are:
R3=1MΩ, R4=560kΩ, R5=33kΩ, C3=220nF, C4=100nF:
R5 2   = 1. 68 ÷ 4. 85V
VRMS = ⋅ ⋅V = α⋅V (11)
R3 + R4 + R5 π g g

This low-pass filter must give a good attenuation at twice the line
frequency.

5) Peak current limiter:

We choose Ipk,lim=11A:
R 14
I pk,lim = 100µA ⋅ (12)
RS
from which R14=5.6kΩ.

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CONTROL STAGE DESIGN

6) R7 and R8 values:

If the current error amplifier has enough gain at line frequency we

have:
R S ⋅ I L = R 7 ⋅ I MULT−OUT (13)

where IMULT-OUT is the multiplier output current, which is related

to the output voltage of the voltage error amplifier VA-OUT by:
VA −OUT − 1. 28
I MULT−OUT = I AC ⋅ 2
(14)
VRMS
which is valid if pin 6 (VLFF) is connected to pin 11 (VREF).

Imposing that the maximum input current occurs with a voltage

VA-OUT=5V, we obtain R7=R8=3.3kΩ.

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CONTROL STAGE DESIGN

7) Over voltage protection:
æ R 12 ö
Vo, max = VREF ⋅ çç1 + ÷
÷ (15)
è R 13 ø
Choosing R12=1.5MΩ and R13=18kΩ gives Vo,max=425V.

8) Soft-start:

Connecting a capacitor between pin 12 and ground a ramp voltage

is generated which causes the duty-cycle to vary from minimum to
nominal value.

Suggested value: C9 = 10µF.

9) Feedback signal divider:

R p2
VREF = Vo ⋅ (16)
R p1 + R p2

Rp1=1MΩ e Rp2=12kΩ + 4.7kΩ trimmer.

As suggested a filter capacitor C7 = 10µF is connected between pin

11 (VREF) and ground.

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CURRENT REGULATOR DESIGN

Approximated power stage transfer function (between duty-cycle

and input current) for frequency above the output filter corner
frequency:
i g (s )
G i (s ) =
Vo
=
d (s )
(17)
sL

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CURRENT REGULATOR DESIGN

The current loop transfer function is:

Ti (s ) = ⋅ R s ⋅ G ri (s )
Vo 1
⋅ (18)
sL Vosc
where, Vosc = 5V is the amplitude of the internal ramp of the PWM
generator.
m(s ) ω ri (1 + sτ zi )
G ri (s ) = = ⋅
Current error amplifier:
ε i (s ) s 1 + sτ pi ( ) (19)

where
1 1
ω ri = ≈ if C 5 >> C 6
R 8 (C 5 + C 6 ) R 8 C 5
(20)

τ zi = R 9 ⋅ C 5 (21)
C5 ⋅ C 6
τ pi = R 9 ⋅ ≈ R 9 ⋅ C 6 if C 5 >> C 6 (22)
C5 + C 6

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CURRENT REGULATOR DESIGN

< f c < f pi where fc is the crossover frequency, then:

If f zi

G ri ( jωc ) ≈
R9
(23)
R8
R 9 2 πf c ⋅ L ⋅ Vosc
Ti ( jωc ) = 1Þ = (24)
R8 R s ⋅ Vo
As far as the phase is concerned:
æ fc ö æ fc ö
∠Ti ( jωc ) = −90 − 90 + arctg çç ÷÷ − arctg ç ÷= m ϕ − 180 (25)
o o o

ç f pi ÷
è f zi ø è ø
where mϕ is the desired phase margin.

Given fc , the phase margin and choosing fs/2<fpi<fs so as to

attenuate the high-frequency ripple R9, C5 and C6 values are
obtained.

Example: fc = 15 kHz, fpi = 50 kHz and mϕ = 60° Þ fzi = 3.5kHz,

R9=47kΩ, C5=1nF, C6=68pF.

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VOLTAGE REGULATOR DESIGN

Transfer function between control voltage and output voltage:
V0 (s ) rp
G v (s ) = = gc ⋅
Vc (s )
(26)
1 + sCrp
where,
ro ⋅ Z L Vg,rms V Vo
rp = , gc = , ro = o , M = (27)
ro + Z L k⋅M Io Vg,rms

ZL = RL = ro resistive load
ZL = ¥ constant current load
ZL = - RL constant power load

and k is defined by the relation:

Vg,rms
I g,rms = ⋅ vc (28)
k
In the L4981A controller, feedforward term VRMS eliminates the
dependence of gain gc from input voltage.

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VOLTAGE REGULATOR DESIGN

From eqs. (13-14) we can write (RM=R7):

R7 R 7 Vg, RMS VA − OUT − 1.28

I g , RMS = ⋅ I MULT − OUT = ⋅ ⋅ 2
RS RS R6 VRMS
(29)
R 7 Vg , RMS VA − OUT − 1.28
= ⋅ ⋅
RS R6 2α2 Vg2, RMS

which corresponds to (28) if:

2
RS æ 2 R5 ö
k = 2R 6 ⋅ ç
⋅ç ⋅ ÷ ⋅ Vg2, RMS (30)
R 7 è π R 3 + R 4 + R 5 ÷ø

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VOLTAGE REGULATOR DESIGN

The voltage regulator transfer function is:

VC (s ) ω rv (1 + τ zv )
G rv (s ) = = ⋅
ε v (s ) s (1 + sτ )
pv
(31)

where
R p2 1 1 VREF 1 1
ω rv = ⋅ ⋅ ≈ ⋅ ⋅ (C2>>C1) (32)
R p1 + R p2 C1 + C 2 R1 Vo C 2 R1

with R1=Rp1||Rp2
τ zv = R 2 ⋅ C 2 (33)
τ pv = R 2 ⋅ (C1 // C 2 ) ≈ R 2 ⋅ C1 se C 2 >> C1 (34)

Considering a crossover frequency higher than the power stage

pole we have:
gc
⋅ω τ = 1 (35)
jω c C rv zv

Choosing fc = 10÷20 Hz, fi<fpv<2fi and a suitable phase margin,

the regulator parameters can be calculated.
Example: fc = 20Hz, fpv = 70Hz and mϕ = 60° Þ fzv = 5Hz,
R2=150kΩ,C1=15nF, C2=220nF.

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6th European Conference on Power Electronics and Applications - EPE '95

DESIGN OF A SEPIC PFC OPERATING IN

DCM

POWER STAGE SCHEME

PROTOTYPE PARAMETERS

Vg = 220 Vrms ± 20% V = 36 V P = 100W fs = 100 kHz

L2 = 74 µH C1 = 0.68 µF C2 = 10 µF n = 0.5

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SEPIC MAIN EQUATIONS

1) Operation as dc/dc converter.
The voltage conversion ratio is:
V Ig D
M= = = n⋅ (CCM)
Vg I 1− D
V Ig D
M= = = (DCM)
Vg I K

where n=N2/N1 is transformer turns ratio, D is duty-cycle and

parameter K is given by:
2 Le L1 L 2
K= , with Le =
RTs L1 + L 2

In the above equations Ts is the switching period and L2 is the

transformer magnetizing inductance.

Critical parameter:

=
(1 − D)
2
=
1 ì K > K crit ÞCCM
2 í
K crit
n2 (n + M ) îK < K crit ÞDCM

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SEPIC MAIN EQUATIONS

Average inductor current I2 : I2 = n ⋅ i D = n ⋅ I

Inductor current waveforms in DICM

2) Operation as a rectifier.

When operating as a rectifier, the dc input voltage Vg is substituted

by the rectified line voltage:
v g (θ) = Vg ⋅ sin(θ)
where θ = ω i t . Consequently, the voltage conversion ratio
becomes:

m(θ) =
V M
=
v g (θ) sin (θ)

where M=V/Vg.

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6th European Conference on Power Electronics and Applications - EPE '95

SEPIC MAIN EQUATIONS

Under power factor correction conditions:
i 2 (θ) = n ⋅i D (θ)= n ⋅ 2Isin 2 (θ)

The apparent load r(q) seen at the secondary side of the

transformer is given by:

r (θ) =
V R
=
i D (θ) 2sin 2 (θ)
Thus the parameter k becomes function of angle q

k (θ) = = 2K a sin (θ), K a =

2L e 2 2L e
r (θ)Ts RTs
sin 2 (θ)
k crit (θ) =
(
M + n ⋅ sin (θ)
2
)
For the converter to operate in DCM the following condition must be
satisfied:
1
Ka <
(
2 M + n ⋅ sin (θ) )2

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SEPIC MAIN EQUATIONS

The average current drawn by the converter, at constant duty-cycle
and switching frequency, is sinusoidal and in phase with the line
voltage and is given by
D 2 Ts v g (θ)
i g (θ) = ⋅ v g (θ) =
2L e R em

where,
2 Le
R em = 2
is the emulated resistance.
D Ts

The converter duty-cycle results:

D = M ⋅ 2K a

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POWER STAGE DESIGN

INPUT DATA:

❏ minimum and maximum input voltage peak value Vgmin,

Vgmax;

❏ output voltage V;

❏ output power P;

❏ switching frequency fs;

❏ initial value for transformer turns ratio n.

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POWER STAGE DESIGN

DESIGN PROCEDURE:

❏ calculate minimum and maximum voltage conversion ratio

Mmin, Mmax

❏ evaluate Ka for π= π /2 and Mmax (minimum line voltage)

1
Ka = α ⋅ , α = 0.9 ÷ 0.95
2(M max + n ) 2

❏ find the value of inductance Le from Ka definition

❏ find the value of duty-cycle D;

❏ calculate the value of inductances L1 and L2 from Le and the

desired input current ripple

❏ calculate device current and voltage stresses as well as peak

inductor currents;

❏ repeat the procedure for different values of transformer turns

ratio;

❏ choose the solution which best meets device ratings.

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POWER STAGE DESIGN

NOTE:

particular attention must be given to the selection of capacitor C1.

Three constrains must be taken into account:

❏ voltage u1 must follow the input voltage shape without distorsion

❏ its voltage ripple must be as low as possible

❏ C1 should not cause low-frequency oscillations with inductors L1

and L2.

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