Wideband TV White Space Transceiver Design and Implementation
Wideband TV White Space Transceiver Design and Implementation
Wideband TV White Space Transceiver Design and Implementation
1, JANUARY 2016
I. INTRODUCTION
THE switch from analog to digital television (TV) has resulted in the local availability of benign wireless
communication channels in the so-called TV white space (TVWS) spectrum, which has triggered a number of
important applications including rural broadband access [1], [2]. The latter also offers infrastructure for smart grid [3]
and potentially 5G services. In the U.K., the TVWS spectrum ranges from 470 to 790 MHz and is divided into 40
channels of 8-MHz bandwidth each. Wireless transmission over TVWS sets a number of requirementsto potential
devices, includingfrequencyagility in order to select and change channels depending on geolocation, and the strict
adherence to spectral masks which are likely to be imposed by regulators to protect incumbent users [4].
With substantial progress in the area of analog-to-digital (ADC) and digital-to-analog conversion (DAC) (see, e.g.,
[5]–[7] where devices can operate close to 3 GHz), softwaredefined radio transceivers that exhibit the frequency agility
and flexibility required of future TVWS devices appear viable. Therefore, the aim of this brief is to explore a
transceiver design and implementation that is capable of converting the entire
Manuscript received April 1, 2015; revised May 25, 2015; accepted June 12, 2015. Date of publication July 14, 2015; date of current version
December 22, 2015. The work of S. Weiss and K. Thompson was supported by the Engineering and Physical Sciences Research Council
(EPSRC) Grant EP/K014307/1 and the MOD University Defence Research Collaboration in Signal Processing. This brief was recommended
by Associate Editor Y. Sun.
The authors are with the Department of Electronic and Electrical Engineering, University of Strathclyde, Glasgow G1 1XQ, U.K. (e-mail:
ross.elliot@ strath.ac.uk; stephan.weiss@strath.ac.uk).
Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSII.2015.2456272
Fig. 1. Spectral mask defining permitted PSD levels in adjacent (l ±1) and next-adjacent (l ±2) TVWS channels [4].
320-MHz TVWS range from and to RF and to discuss some of its characteristics in terms of cost, latency, and
selectivity.
The permitted interference levels outlined in Fig. 1 cannot be met by standard orthogonal frequency division
multiplexing (OFDM). Therefore, filter bank techniques that predate OFDM [8]–[11] have recently seen a revival in
the form of filter-bankbased multicarrier (FBMC) modulation [12]–[14] due to their superior spectral confinement
and resulting advantages in terms of synchronization over OFDM [15]–[17].
Most FBMC transceivers operate in the baseband, where a number of subchannels or multiple users are allocated to
welldefined frequency bands. Popular structures include discrete Fourier transform (DFT) modulated filter banks [8],
[15] and derivatives [18] but also iterated halfband schemes such as [11]. Many filter bank schemes currently evolving
in the context of frequency agility and cognitive radio [19], [20] are also located in the baseband. In the context of
software radio, recently, a number of implementations of wideband receivers based on filter banks have been discussed
[21]–[24], whereby very high speed implementations such as [23] are restricted to essentially a DFT, while more
flexible filter bank designs such as [21] and [22] do not comment on complexity or attempt a real-time implementation.
Based on initial design work in [25] and [26] for a twostage architecture and a low-rate implementation in [27], this
brief explores the design and real-time field-programmablegate array (FPGA) implementation of a wideband TVWS
frequency agile transceiver. In order to accomplish an implementation, different from [25], the number of subbands is
restricted to a power of 2. In the following discussion, Section II outlines the overall system, while Section III provides
some design details. The multirate implementation and its impact on complexity and latency are explored in Section
IV and demonstrated in Section V. This design is ported onto a Xilinx Virtex-7 in Section VI, with the conclusion
drawn in Section VII.
Fig. 2. Proposed multistage TVWS filter bank transmitter (above) and receiver (below) with a PPF in stage 1 and an FBMC modulator in stage
2.
to impose [4]. While OFDM-based standards generally exhibit too poor frequency selection to comply with this mask,
FBMC systems can provide sufficient frequency selectivity to fulfill this specification.
The implementationof an FBMC system is numerically most efficient with a single filter bank, as it requires fewer
coefficientsandthereforelowerlatencythananiteratedfilterbankwith several stages leading to interpolated FIR filters [28].
However, targeting an FPGA implementation, there is a limit to the sampling rate of such devices. Using a polyphase
structure, data can beexternallymultiplexedanddemultiplexedintoa limitednumber
ofstreams,withpolyphasecomponentsrunningontheFPGA at a lower rate. Therefore,a two-stage approachis adopted,
with the proposed transceiver system outlined in Fig. 2.
On the transmitter side—the upper branch in Fig. 2—stage 2 combines 40 TVWS baseband channels each of 8-MHz
bandwidth by means of an FBMC synthesis bank into a baseband signal that feeds into stage 1. Stage 1 comprises a
PPF, which, together with a position correcting term e−jΩn, will translate the baseband signal to the UHF range of 470–
790 MHz, with a sampling rate fs and a word length Rtx. The real part of the analytic outputs is then fed to a DAC at
RF.
The receiver in the lower branch of Fig. 2 operates a dual design to the transmitter. In stage 1, the RF signal is sampled
at fs with word length Rrx. A complex-valued polyphase bandpass filter creates an analytic signal which is appropriately
modulated with a complex exponential of normalized angular frequency Ω such that the 40 channels of the TVWS
spectrum lie flush at dc. In stage 2, an analysis filter bank implementing the FBMC receiver extracts the 40 TVWS
baseband channels. Oversampled by a factor of 2, the outputs of the FBMC run at 16MHztoeasethetaskof
synchronization,subsequentfiltering, and further downconversion of the individual 8-MHz channels.
channels in the FBMC to be a powerof2. This differsfroma previousdesign[25], and it will enable the realization
on an FPGA to be discussed in Section VI.
A. PPF—Stage 1
In the filter bank receiver, stage 1 extracts the TVWS bands with a center frequency fc = 630 MHz from the RF signal
Fig. 3. Stage 1 filter with a passband width of 320 MHz to capture the TVWS spectrum and with transition bandwidth depending on the
selected decimation ratio .
sampled at fs = 2.048 GHz, to create an analytic baseband signal with TVWS channels aligned from dc to 320 MHz.
This can be achieved by means of an analytic bandpass filter centeredat fc, whose bandlimitation will allow
decimationby a factor i . The required filter characteristic is shown in Fig. 3, whereby aliasing is permitted in the
MHz. (1)
1
with polyphase outputs interfaced to a hardware multiplexer [25]. The latter is often already incorporated in state-of-
the-art DACs [7].
B. FBMC System—Stage 2
The two designs for stage 1 necessitate different filter bank approaches for stage 2. With an RF sampling rate of
2.048 GHz and decimations by in stage 1, channels of 8-MHz bandwidth have to be extracted for
the three designs in stage 2, respectively, as contained in Table I. For each of the designs, only 40 of the channels
will be utilized. Due to their uniform ordering, a modulated filter bank is an efficient approach, which is oversampled
by a factor of 2. First, this eases the synchronization efforts of individual TVWS channels in the baseband. Second,
oversampling is advantageous as it relaxes the prototype filter , which is outlined in Fig. 4, allowing a maximum
possible transition bandwidth . This design characteristic assumes that the TVWS channel inputs to Tx stage 2 are
perfectly bandlimited to 8 MHz.
We here employ a DFT-modulated filter bank [29], where the analysis filter bank in the transmitter employs an
inverse DFT and the synthesis bank in the receiver a DFT, in order to align channels in ascending order from dc to
320 MHz.
A. Polyphase Implementations
For stage 1, the receiver requires a hardware demultiplexer to feed polyphase components of the sampled RF
signal into the FPGA for polyphase filtering, while in the transmitter, the output of the PPF components is passed out
of the FPGA implementation, and it will be multiplexed in hardware to form the RF signal. As mentioned before, such
hardware multiplex-
Fig. 4. Stage 2 prototype filter with 8-MHz passband width and decimation to 16-MHz sampling rate. The absolute bandwidths are identical for
all designs, which, however, differ in their number of bands .
ers are often readily incorporated in state-of-the-art ADCs [6] and DACs [7].
The implementation in Section III-A assumes a complex bandpass PPF, combined with a frequency shift Ω. With a
filter length , the complexity is real-valued multiply accumulates (MACs). Alternatively, the
stage 1 signal could be filtered by a real-valued low-pass filter, requiring a modulation at both the input and output of
stage 1, leading to . The second implementation is only favored if
(2)
which, for the selected values , is not satisfied.
For stage 2, different implementations are possible [15]. Since circular buffers are not advantageous for FPGA
implementations, we have selected polyphase implementations according to [30], which require only one tapped delay
line, a set of multipliers, and the transform on which the modulated filter bank is based, such as in this case a DFT
implemented via a fast Fourier transform.
(3)
28 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 63, NO. 1, JANUARY 2016
measured in real-valued MACs/s. For stage 2, the complexity of up- and downconverting 40 channels with a DFT-
modulated filter bank is the same as that for a single channel, plus the modulating transform, i.e., a -point DFT. The
overall complexity in (3) is likely to be dominated by the stage 1 filter of length and is listed for the two different
implementations in Table I.
The latency of a filter bank transmitter or receiver, assuming linear phase prototype filters, is given by
. (4)
The latency will be dominated by the lower rate stage 2 filter, with the overall transmitter or receiver delay for the two
implementations shown in Table I.
ELLIOT et al.: WIDEBAND TV WHITE SPACE TRANSCEIVER DESIGN AND IMPLEMENTATION 27
Fig. 5. Magnitude responses of (a) stage 2 and (b) stage 1 prototype filters.
The power spectral densities (PSDs) of simulated Tx signals after stages 1 and 2 are shown in Fig. 6, whereby each
TVWS channel is loaded with a 5.33-MHz signal [25]. The stage 2 transmitter output, containing the 320-MHz TVWS
baseband across 40 of the channels, is depicted in Fig. 6(a). Fig. 6(b) displays the PSD of the stage 1 output
occupying the TVWS band 470–790 MHz with the spectral mask satisfied.
Fig. 7. PSDs after (a) stage 2 and (b) stage 1 obtained by a bit-true and cycle accurate simulation with 16-bit word length.
VII. CONCLUSION
We have discussed a two-stage filter bank transceiver design with the capability to simultaneously up- and
downconvert the entire U.K.’s TVWS range of 40 8-MHz wide channels by sampling at the radio frequency. The
system satisfies regulatory requirements w.r.t. the spectral mask as well as hardware limitations on the sampling rate
and the FPGA devices. Among two discussed parameterizations, a tradeoff between complexity and latency arises.
The design exploits additional word length resolution due to oversampling and can cope with fixed-point
implementations while still satisfying design requirements. Results of an FPGA implementation have been reported,
with the more costly design fitting comfortably onto a Virtex-7 device.
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