1 SystemVerilog

Verification Flow

Learning Objectives

After completing this lab, you should be able to:

• Generate the SystemVerilog testbench files for a
Device Under Test (DUT)
• Write a SystemVerilog task to reset the DUT
• Compile and simulate the SystemVerilog test program
• Verify that the DUT signals are driven as specified with
Discovery Verification Environment (dve)

Lab Duration:
30 minutes

SystemVerilog Verification Flow Lab 1-1

Synopsys 50-I-052-SLG-001
Lab 1

Getting Started

Once logged in, you will see three directories: rtl, labs and solutions.

labs/ solutions/ rtl/

lab1/ lab6/ lab1/ lab6/ router.v

Figure 1. Lab Directory Structure

In this lab, you will develop a simple SystemVerilog test program to reset the
DUT.

Test program

Configure DUT
program router_test

reset()

router

DUT

reset_n

Figure 2. Testbench Architecture

Lab 1-2 SystemVerilog Verification Flow

Synopsys SVTB
 Lab 1

Lab Overview

This lab takes you through the process of building, compiling, simulating and
debugging the testbench:

Generate
SystemVerilog files

Develop testbench to
reset DUT

Compile and simulate

with VCS

Verify simulation
results with DVE

Figure 3. Lab 1 Flow Diagram

Note: You will find Answers for all questions and solutions in the
Answers / Solutions at the end of this lab.

SystemVerilog Verification Flow Lab 1-3

Synopsys SVTB
Lab 1

Constructing SystemVerilog Testbench Program

Task 1. Template File Generation

A typical architecture of a SystemVerilog testbench looks like the following:

Configure

Generator Coverage

Test
Transactor Self Check Transactor program
Top level
harness file
Driver Monitor

DUT
interface

The process with VCS in creating this SystemVerilog testbench is as follows:

router.v

ntb_template -t router ../../rtl/router.v

Discard
router.test_top.v router.vr.tmp router.if.vrh

router.test_top.sv router.if.sv router.tb.sv

Top level harness Interface Test program

vcs –sverilog router.test_top.sv router.tb.sv router.if.sv ../../rtl/router.v

simv

Lab 1-4 SystemVerilog Verification Flow

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 Lab 1

1. Log into workstation (use login and password provided by instructor)

2. Go into lab1 directory:

> cd labs/lab1

3. Generate OpenVera template files:

> ntb_template -t router ../../rtl/router.v

This command creates three files intended to be used for the VCS Native
Testbench simulation environment. You will be using only one of the files,
router.test_top.v. The other two will be discarded.

Task 2. Create SystemVerilog Interface File

1. Discard the OpenVera files:

> rm *.tmp *.vrh

2. Create router.if.sv interface file by copying from the

router.test_top.v file.
> cp router.test_top.v router.if.sv

3. Open router.if.sv with a text editor.

4. Change the declaration of module to a declaration of interface. Include an

argument to pass in clock(s) in the interface.
Change:

module router_test_top;
...
endmodule

To:

interface router_io(input logic clock);

...
endinterface

This starts the process of building the interface between the DUT and the test
program.

SystemVerilog Verification Flow Lab 1-5

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 Lab 1

5. Retain the wire declarations with the exception of clock and delete all other
content of the interface block.
Change:

interface router_io(input logic clock);

parameter simulation_cycle = 100;
reg SystemClock ; Keep
wire reset_n ;
delete
wire clock ; // moved to the port list of interface
wire [15:0] din ;
...
wire [15:0] frameo_n ;
ifdef SYNOPSYS_NTB
...
endinterface

To:

interface router_io(input logic clock);

wire reset_n ;
wire [15:0] din ;
...
wire [15:0] frameo_n ;
endinterface

6. Change the wire declaration to logic:

interface router_io(input logic clock);

logic reset_n ;
logic [15:0] din ;
...
logic [15:0] frameo_n ;
endinterface

At this stage, all interface signals are asynchronous and without direction
specification (i.e. input, output, inout).

Lab 1-6 SystemVerilog Verification Flow

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 Lab 1

The next step is to create the set of synchronous signal for the test program to
drive and sample the DUT signals. This is done with clocking block
declarations.

7. Declare a clocking block driven by the posedge of the signal clock. This
clocking block will be used by the test program to execute synchronous drives
and samples. All directions for the signals in this clocking block must be with
respect to the test program.

interface router_io(input logic clock);

logic reset_n;
logic [15:0] din;
...
logic [15:0] frameo_n;
Create synchronous
signals by placing clocking cb @(posedge clock);
signals into clocking output reset_n;
block with direction output din; // no bit reference
specific to test program output frame_n; // no bit reference
output valid_n; // no bit reference
input dout; // no bit reference
input valido_n; // no bit reference
input busy_n; // no bit reference
input frameo_n; // no bit reference
endclocking
endinterface

8. In the clocking block, make sure that race conditions are avoided by adding in
specification for input and output skews:

interface router_io(input logic clock);

...
clocking cb @(posedge clock);
default input #1 output #1;
output reset_n;
output din; // no bit reference
...
endclocking
endinterface

SystemVerilog Verification Flow Lab 1-7

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Lab 1

9. Lastly, create a modport to be used for connection with the test program. In
the argument list, there should be references to the clocking block created in
the previous step and all other potential asynchrous signals.

interface router_io(input logic clock);

...
clocking cb @(posedge clock);
default input #1 output #1;
output reset_n;
output din; // no bit reference
...
endclocking
modport TB(clocking cb, output reset_n);
endinterface

10. Save and close the file.

Task 3. Create SystemVerilog Test Program File

1. Open a new SystemVerilog test program file called router.tb.sv with an

editor

2. In this file, declare a test program block with arguments which connects to the
TB modport in the interface block:

program automatic router_test(router_io.TB router);

endprogram

3. Within the program block, print a simple message to the screen:

program automatic router_test(router_io.TB router);

initial begin
$display(“Hello World!”);
end
endprogram

4. Save and close the file.

Lab 1-8 SystemVerilog Verification Flow

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 Lab 1

Task 4. Create SystemVerilog Test Harness File

1. Create the SystemVerilog test harness file by rename the Verilog test harness
file created by the template generator:
> mv router.test_top.v router.test_top.sv

2. Open router.test_top.sv with a text editor.

3. Clean out the content of the file keeping only the following:

module router_test_top;
parameter simulation_cycle = 100;
reg SystemClock;
router dut(
.reset_n (reset_n),
.clock (clock),
.din (din),
.frame_n (frame_n),
.valid_n (valid_n),
.dout (dout),
.valido_n (valido_n),
.busy_n (busy_n),
.frameo_n (frameo_n)
);
initial begin
SystemClock = 0;
forever begin
#(simulation_cycle/2)
SystemClock = ~SystemClock;
end
end
endmodule

4. Add an interface instance to the harness:

module router_test_top;
parameter simulation_cycle = 100;
reg SystemClock;
router_io top_io(SystemClock); // instantiating interface
router dut( … );
initial begin
SystemClock = 0;
...
end
endmodule

SystemVerilog Verification Flow Lab 1-9

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Lab 1

5. Instantiate the test program (make I/O connection via interface instance):

module router_test_top;
parameter simulation_cycle = 100;
reg SystemClock;
router_io top_io(SystemClock); // instantiating interface
router_test test(top_io); // add program
router dut( … );
initial begin
SystemClock = 0;
...
end
endmodule

6. Modify DUT connection to connect via interface:

module router_test_top;
parameter simulation_cycle = 100;
reg SystemClock;
router_io top_io(SystemClock); // instantiating interface
router_test test(top_io, top_io.reset_n); // add program
router dut(
.reset_n (top_io.reset_n),
.clock (top_io.clock),
.din (top_io.din),
.frame_n (top_io.frame_n),
.valid_n (top_io.valid_n),
.dout (top_io.dout),
.valido_n (top_io.valido_n),
.busy_n (top_io.busy_n),
.frameo_n (top_io.frameo_n)
);
initial begin
SystemClock = 0;
Connect DUT via
...
end interface instance
endmodule

7. Save and close the file

Lab 1-10 SystemVerilog Verification Flow

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 Lab 1

Task 5. Compile & Simulate

1. Compile all files with the following command (using vcs):

> vcs -sverilog router.test_top.sv router.tb.sv router.if.sv ../../rtl/router.v

VCS will compile the files and create an executable file called simv.

router.test_top.sv router.if.sv router.tb.sv router.v

vcs –sverilog router.test_top.sv router.tb.sv router.if.sv ../../rtl/router.v

simv

The next step is to execute the simulation binary.

2. Run the simulation by executing the binary created by VCS:
> simv
3. Check to see if you see the $display() message. If so, proceed to the next step.
If not, debug your testbench to see why the message was not displayed.

Task 6. Reset the Router

You have successfully built, compiled and simulated a simple SystemVerilog

testbench. The next step is to added needed functionality to the testbench. In this
task, you will add a routine to intialize the router.

1. Open router.tb.sv with a text editor.

2. In the program block define a task called reset()to reset the DUT per spec.
as described in lecture: (bear in mind that reset_n is an asynchronous
signal where as all other signals are synchronous to the clock signal)

clock

reset_n

frame_n[i]

15 clock

SystemVerilog Verification Flow Lab 1-11

Synopsys SVTB
 Lab 1

3. Replace the $display() call in the initial block to create vcd+ dump file
with $vcdpluson followed by calling the reset() task.
When completed, your program should look like:

program automatic router_test(router_io.TB router);

initial begin
$vcdpluson;
reset();
end
task reset();
router.reset_n <= 1'b0; // asynchronous
router.cb.frame_n <= '1; // synchronous
router.cb.valid_n <= '1; // synchronous
##2 router.cb.reset_n <= 1'b1; // synchronous
repeat(15) @(router.cb); // synchronous
endtask
endprogram

4. Save and close the file.

Task 7. Compile & Simulate

Once you are finished writing the router.vr routine, compile and simulate the router
rtl code with the OpenVera testbench. This is done in a single step.

1. Compile all files with the following command (using vcs):

> vcs -sverilog –debug router.test_top.sv router.tb.sv router.if.sv../../rtl/router.v

The above compile added usage of one more switch: -debug.

This switch combined with the $vcdpluson; system task call in you test
program will create a dump file “vcdplus.vpd” which stores the activities
of signals during simulation. You will be using the VCS Discovery Visual
Environment (dve) to examine the DUT signals in a waveform window.
The next step is to execute the simulation binary.
2. Run the simulation by executing the binary created by VCS:
> simv

Lab 1-12 SystemVerilog Verification Flow

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 Lab 1

Did the simulation execute correctly? Looking at the simulation print out,
there is no way to know for sure. You will need to examine the simulation
waveform with a waveform viewer to verify that your testbench was executed
correctly.
For future compile/simulate iterations, there is a make file (Makefile)
already written to simplify this process. To use it, just type “make” to
recompile and run simulation.
The content of the Makefile is as follows:

# Makefile for SystemVerilog Lab1

RTL= ../../rtl/router.v
SVTB = ./router.test_top.sv ./router.if.sv ./router.tb.sv

vcs: clean sv_cmp sim

sim:
./simv | tee log

template:
ntb_template -t router -c clock $(RTL)

sv_cmp:
vcs -sverilog -PP -debug_all $(RTL) $(SVTB)

clean:
rm -rf simv* csrc* *.tmp *.vpd *.key *.log log *.tcl *.old *debugger_rc

nuke: clean
rm -rf *.v* *.sv include .*.lock .*.old

SystemVerilog Verification Flow Lab 1-13

Synopsys SVTB
Lab 1

Task 8. Browse Simulation Hierachy in DVE

1. Bring up the waveform viewer using the UNIX command dve.

> dve &

It may take a while for the gui to appear.

2. Click on File Æ Open Database.

3. Double click on vcdplus.vpd file.

The DVE debugging windows should now be opened with the RTL hierarchy and
source code. This window is the Source window of DVE.

The next step is to view the waveforms in the Waveform window.

Lab 1-14 SystemVerilog Verification Flow

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 Lab 1

4. Display waveform by clicking on .

5. The Waveform window should open up looking like the following:

The only signal that shows up is the signal declared in the top level harness
file, SystemClock. To add other signals, you will need to add the rest of the
signals.

SystemVerilog Verification Flow Lab 1-15

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Lab 1

6. Select Signal -> Signal Group to open up a window for configuring signals.

In the Signal Groups window, you can access the signals in the interface block and
placing them into either the existing signal group or create new signal groups. In
this step, you will be creating new signal groups.

7. Click on the icon to expand the content of the harness file.

8. To create a new signal group, click on router_io, Then, highlight the signals
in middle pane, and drag and drop them into New Group on the right pane.

Lab 1-16 SystemVerilog Verification Flow

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 Lab 1

9. Click on Apply to have the creation activated.

10. Close the Signal Group window to go back to the Waveform window.

11. Click on Signal -> Display Signal Group -> All in the Waveform window to
see the waveforms.

12. Click on to expand window to see through all simulation time.

SystemVerilog Verification Flow Lab 1-17

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Lab 1

13. Visually verify the operation of the reset signal in the Waveform window. If
there are errors, correct the error then type “make” to re-compile and re-
simulate the modified code.
If there are no errors, you are done with lab1.

Lab 1-18 SystemVerilog Verification Flow

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Answers / Solutions Lab 1

Answers / Solutions

router.if.sv Solution:

interface router_io(input logic clock);

logic reset_n;
logic [15:0] din;
logic [15:0] frame_n;
logic [15:0] valid_n;
logic [15:0] dout;
logic [15:0] valido_n;
logic [15:0] busy_n;
logic [15:0] frameo_n;

clocking cb @(posedge clock);

default input #1 output #1;
output reset_n;
output din;
output frame_n;
output valid_n;
input dout;
input valido_n;
input busy_n;
input frameo_n;
endclocking

modport TB(clocking cb, output reset_n);

endinterface

router.tb.sv Solution:

program automatic router_test(router_io.TB router);

initial begin
$vcdpluson;
reset();
end

task reset();
router.reset_n <= 1'b0;
router.cb.frame_n <= '1;
router.cb.valid_n <= '1;
##2 router.cb.reset_n <= 1'b1;
repeat(15) @(router.cb);
endtask

endprogram

SystemVerilog Verification Flow Lab 1-19

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Lab 1 Answers / Solutions

router.test_top.sv Solution:

module router_test_top;

parameter simulation_cycle = 100;

reg SystemClock;
router_io top_io(SystemClock);
router_test test(top_io);
router dut(
.reset_n (top_io.reset_n),
.clock (top_io.clock),
.din (top_io.din),
.frame_n (top_io.frame_n),
.valid_n (top_io.valid_n),
.dout (top_io.dout),
.valido_n (top_io.valido_n),
.busy_n (top_io.busy_n),
.frameo_n (top_io.frameo_n)
);

initial begin
SystemClock = 0;
forever begin
#(simulation_cycle/2)
SystemClock = ~SystemClock;
end
end

endmodule

Lab 1-20 SystemVerilog Verification Flow

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