2.2 II] ARCHITECTURE OF 8051 Figure 22 shows a functional block of the intemal operations of an 8051 microcontroller, The 8051 includes an 8 bit CPU, memory, four 8 bit /O ports, two timers/counters and @ Universal Asynchronous Receiver Transmitter (UART). 2.2.1 PROCESSOR ‘The processor includes arithmetic and logic unit, instruction decoder and timing generation unit, Accumulator A or Ace), B register and status regis Arithmetic and Logie Unit The Arithmetic and Logic Unit (ALU) performs the computing functions. The accumulator is an 8 bit register. In arithmetic and logical operations, one of the operands is in ‘A’ register. After the arithmetic/logical operations, are performed, the result is stored in ‘A’ register and this affects various flags namely Carry (C), Auxiliary Carry (AC), Overflow (O), and Parity (P) of status register. Instruction Decoder and Control The instruction decoder and control ate parts of the timing and control unit, When an instruction is fetched from program memory, itis loaded in the instruction register. “The decoder decodes the instruction and establishes the sequence of events to follow. The instruction register iy not programmable and cannot be accessed through any instruction, The timing generation and ‘control unit synchronises all the microcontroller operations with the clock and generates control signals necessary for communication between the processor and peripherals. CPU Registers ‘A’ Register (EOH) Similar toany Intel microprocessor, the $051 hasan 8 bit A and in the instruction, itis referred as “A’. The accumulator is used in al arithmetic and logical operations and hes direct connection to ALU. One of the operands is stored in the accumulator. After the operation is performed, the result is stored in the A. In multiplication operation, one of the 8 bit operands is stored in “A’ register. After the operation, it stores the lower byte of the result in “A' register. In division operation, it holds an 8 bit dividend and after the operation, the quotient is stored in the accumulator. I is also used in indexed addressing mode to access information from program memory. ‘A’ is bit addressable register. ‘B’ Register (FOH) The 8 bit “B" register is used during multiply and divide operations. In multiplication ‘operation, one of the 8 bit operands is stored in “B’ register. After the operation, it stores the higher byte of the result in °B* register. In division operation, it holds 8 bit divisor and after the operation the remainder is stored in “B" register. For other instructions, it can be used as an & bit general purpose register. “B” is bit addressable register. Program Status Word (DOH) The & bit Program Siatus Word (PSW) register contains the arithmetic status of the ALU and the bank selects bits for the data memory. After the arithmetic and logic operations, the C, AC, P, and O flags of PSW register are set or reset according to the result. In subtraction, the C and AC bits operate as borrow and digit borrow flag respectively. PSW is bit addressable register cy | ac] ro [ esi] eso [ ow] — [? Bit7 BitOStack Pointer (81H) Stack Pointer is an 8 bit register It contains the address of the data item on the top of the steck. It is incremented before the data is stored. While the siack may reside anywhere in on-chip RAM, the Stack Pointer is initialised to 07H after a reset. The operation and instruction associated with the stack will be discussed in detail in Chapter 3. Data Pointer (DPH-83 H and DPL-82 H) ‘The Data Pointer (DPTR) consists of two 8 bit registers—a high byte (DPH) anda low byte (DPL). Its intended function is to hold a 16 bit address. It is used to fumish address information for internal and external program memory and for extemal data memory. Program Counter Program Counter (PC) is a 16 bit register. The 16 bit program counter specifies the address of the next instruction to be executed. Afier reset, the PC will be set to 0000H and the CPU will siart executing the first instruction stored at program memory location O0OOH, The 8051 fetches the instruction one byte ata time and afer fetching, it increments the PC by 1. One of the important fettars of a microcontroller isthe number of pins which ean be uscd for connection with the extemal world, These pin are refered as Inpu(uiput (VO) pinsand a group of sueh pins are refered as an 0 port. The VO ports ate used to transfer dat in and out of a mierocontoler. I the 805, each VO pin has built-in MO cirewits which allows a pin to diteetly interface with the external circuits. This feature is usually not evailale in the microprocessors, therefore, we noed additional chips with the microprocessors to interface it with the external word 13.1 | THE 8051 PORTS ‘The BUSI port structute is extremely versatile and flexible. The devies has 32 1/0 pins configured as four bit parallel ports named PQ, P1,P2 and P3. Each pin can be used as an inputor as an output under the sofiware contol. Tse LO pins can be accessed directly by instructions during the program exceution. The HO ports are memory mapped in the 8051. ic, they are treated as memory’ Toeations. vt of the 32 170 pins, 24 pins (PO, P2 and P3) may each be used for two diferent Fanctions (bu only one ata im), providing «total 66 pins (40 normal pins + 24 alternate Functions of ports + 2 for programming). “The fanetion performed by a pin at any time depends on whic connected o that pin: therefore these actors ean be iruction is used 10 access a pin and what signal is ceil controlled by a progtammer. The altenate Functions of pons ate given below. Table 13 Fort Jornal fonction Ps Ln ones ts (AD7- ADO nd Fs lighontr aes bs AIS AS Fi taht ns svola able 123, FADGAID | XD Steps Reset Even witin al po, VO cpr yt combine in ERR rin re Da sitecent ways. Dilfeent pins ean be configured as an input or P3200ia 12) | TRO (xtra inert cnt non fon ast pn canbe st SSS) aa nr SliseBle Al pnsof tc S31 phi ee nS inkctondautatrwcestctsDinhotwr3us fgg yaa bn ‘The SFR for each port is made of these eight Latches, which 2208 OY ie isi sans ve [TH CTimefCounts 1 external inp) js shown Table 13.2.Tobe 122 Fort Ss and ther addressee SL S00 Port ri om sont Poot 2 ‘NTL Ponts Ps B-Bon 12.1.1 Porta Port Tis. rue HO port bees thas no alternate function al therefore ithas the simplest structure, The basic opcratio of Por 1 is discussed first to develop the understanding of sore basic concepts like configuring the por as an put or ‘output, reading port pin and writing a prt pin, The base discussion of Pot is equally applicable all ther ports unless specified explicily. The simplified structure of Port | is given in igure 13.1 AAs mentioned eatie, each port pin as aIstch (D latch), inpur baffers (BL and 12) and output driver (TH). The daa from the intemal data us is writen into the D hatch whea the “tte w ate’ signal fs acivated asa resulcof appropriate instruction execution. The Q output ofthe latch scoped into the internal data bus when the “eal latch signal i activated and the level of a port pin is copied into the internal data bus when the ‘read pin signal is activated, The instructions whieh aetvate these signals ae discussed in the later section ofthis chapter. srou/output Ports nt Veo Interna Pul-Up Resistor Read Latch . of Pix \ Pia Iniernal Date Bus. t——p Pix JN > LATCH Wrte to Lateh Read Pin B21. Configuring the Portasen Input The por pin wll be configured san input when we wie “110 dhe caesponing bit (ath) ali The emon for this explaied below, Conse {) senor Fire 132. seas taten Whoa “1° is writen to port bi itis writen to Mt je |] the D fateh: therefore, 1 will appear at output ermal outa y | yy of the latch, ic. Q = 1 and Q Now O=0 Bus: i connected (0 gate ofthe tansior (FET) TI, stich wil um oT TI wll Beave a» an open Circuit nd sconnect he pa pin snd sou thereon. the input inal comested to the pin wil goo te buffer 2, When we rea the put Read Pr port ssing an imrucion tke MOY A, Pl. the Boffer 2 whe ena (by “ead pga ad we ae cally veadins a pr pin. Figure 132 shows the path fr ssn Mow, The sina evel on dhe pin wl be essed he atral da gh he her 2 Yee ire tate Fe.132. Reading port pin red! as an inpat afer eset because the S0S1 writes 1S 0 all pot latches afer ress. 13 0 is All the port pins are eon written by a program to the port late, it ean be reconfigured as an input by writing a °T* to it Remember that c shown in Figute 13.1 and 18. ave only for one pin. There will he 8 seh cirewts, one For each pin ofthe port Note: Ports 29, P2 and P3 have additional cieuitry hecause they have dual functions furthermore, tho pull-up resistor is internal for ports PI, P2 and P3. We have to connect the external pull-up resistor For PO. 2. Configuring the Portas an Output ‘Nothing ext has (o be done o configure a por as an output—whatever level (1 or 0) is written (oa port late, the same level will directly appear on the port pin. Logic I’ (high) can be written to the port pin by simply writing “I” tothe port latch, As showa in Figure. 13.3,when “1° is writen to the D latch, it will make Q = | and Q=0, which will tum off TL and, therefore, I” will appear on the pin and the pin will source the cartent; similarly, logic “O" can be written by writing ‘0"to port latch. When "Dis writen, Q = 0 and Q = 1 wich will ru on TI and the pin will be connected t the ground (© volt as show in Figure 134 and i will sink the current, During the execution ofan instruction that modifies the valve ina por latch, the new value is available 10 the latch during S6P2 of the last machine cycle of the insuuction,[Newer write 0) tothe por that was configu Alireetly 10 Vee (logic high inped. Writing ‘0° will um on TT and it grounds the input pin, This will shor Yoo ‘Whatever Writen to Latch Bit ‘Appear at Port Pin } pinternal Pullup Read Laich—— aR Pin Internal Data Bus write to Latch mene Fig. 29.3. Whiting 3 tothe port pin Whatever Wiritlon to Latch Bit ‘Appeer at Port Pin Internal Pul-up Resistor Road Latch: ‘Write to Latoh Read Pin Fig. 13.4 Writing Oto the por pin das am input port hecause may da age the port when the pi is connected ¢ high-level signal (Vcc ) Connected 10a pin, and a high current will low hough TH and may damage it, To avoid such problems, ‘ere a to be taken while the connee hetwoen the input signal and the port pin as shown in F 12 input signal toa port pin, One simple way is to use a curent-limiting resisor Fg. 19S. Portprotecton axing current iting resistor13.1.2 Porto Port O can be used as an inpuvoutput or os a esa onal data bus and low-order address mory. The sirctare of PO is at ‘shown in Figure 13.6. a When PO is sed as an oui weg “01 peat ach pin takes wil make Q= Oand Qe 1. The PIN he will connected to the get TI hough ga imalipleace When he pom is wpe sane yg as] i ‘output internal signal “Control” will be O and ues a ‘contacts tote out 2-0-1 muliplsn. 4 will wen on TH, thus grounding the port pin and logic willbe available the port Read Pn pin. The operation is summarized in Figure 1B. ead Lae. internal Data ue Wie to Latch Fig. 3.7 Writing 010 Port Opin While writing “1° to the fatehes, Q-= | and J = 0 this will tar off the TH, which Moats pin to high impedance state ‘Therefore, an extemal pup resistor is needed © proxige logic “I*, Note that T2 remains off when the pin is used as InpuvOutpur Port Oas an Address/Data Bus When PO is used as an address bus (function of the port is decided by instructions used to secess the port), the inte ‘control signal connects the address line (indicated as ADDR/DATA in Figure 13.6) to the gate of 71 (lower PET) using the multiplexer. The logic “I'on the address bit will ten on the T2 (upper FEET) sinee ‘contol is also “T'whon PO is used ‘san address bus and atthe same time, TI is tacned off, which in tuin provides logic *I" on the port pin as shown in Figure 13.8 ‘When aildress bit is ‘0°. 1 is turned on and T2 is umed off providing logic 0" at port pin. Once an address is issued and latched into external latch using ALE. the bus behaves as a data bus. Now if data isto be written tothe external memoryead Leteh Br Iomat Data Bus +p] ets yo eae — teh BO, 0 Lt ei 182 Read Pin Fig. 138 Port Os address (tte to por operation, he data willbe written to pins exactly in a way asthe address is written tothe pins as deseribed just above, Ifthe data isto be read irom the extsral memory; the contro Jogi will automatically write I's to laehes to ‘configure ports an inp control = 0 and, so both Tt and 12 will be off, “control” =O will connoet Q of the tteh to the gie of TH through the multiplexer) and the da athe port pin will he transferred the intemal data us through the buffer B2, Discussion Question Why do Por pins need external pull presisons? Answer PortOneedsa pull-up resistor because this port provides an open colleetoroutpat. With an open collector output, logic | cannot ne supplied to the in, when we write | o kate bit, the corresponding pin wil Hot (high impedance state) “Therefore, w provile logic 1 atthe por pin, we need to connect the external pull-up resistor 13.1.3 Port2 Port? can he used as Input/Output port exactly similar to Port 1."The other use of Port? provide high-order address byte w aveess extemal memory. The strcture of Port 2 is shown in Figure 139. ecriData Cento! a teal Dats ‘LN Bus +I) 7 Witte Leteh —/.— Rid itux a 2 Read Pin Fig. 39 Port 2steacture‘When itis supplying high-onder address signals (5-9), the internal control signals conncet ares Hine (indicated a¢ ADDR in Figure 13.9) to the gate of TT through the inverter. A 0" on de address bit will turn on TL and provide “O'on the port pin, Similarly, °I' on dhe adress bit will peovide “Ion the por pia, Port 2 latches are kept stable forthe duration ‘of the entire external memory teacivrite eyele 13.14 Pores Port 3 can also be used as InpaOutput por similar to Port | ad the sltemate funetions are controlled by various SFRS. Port 3 strucwre is shown in Figure 13.10 ‘The altemate functions can only be used ifthe bit Lach inthe corresponding port SFR contains 21, otherwise the port nis fined al “O". As shown in Figure 13.10, ifthe P3 bit lach contains 1 then output is controlled by the signal labled ‘aliemate output function’. The actual P3.X pin lovel is always available wo the pins alternate input function Diseussion Question What are the alternate functions of Port, |, 2 and Answer Port 0 also functions as the lower order 8 bits ofthe multiplexed addressdata bus fr external memory access. “There is no altemate function for Port 1, for Port 2 also aes as higher-order 8 bits ofthe address bus for extemal memory acess Port 3 pins have individual altemate fonctions. The pins on this port funetion as extemal imterrupeinpats, serial <éta input and output, timer/eounter inputs and control signals fr external memory access (Refer Table 13.1), Yoo ‘ternate Output | Invern Puta uneven Resistor oad Latch Aernate Input Funetion