COMBINATIONAL LOGIC COMBINATIONAL LOGIC

UNIT 5: COMBINATIONAL LOGIC 5.1 BASIC COMBINATIONAL LOGIC CIRCUITS AND

IMPLEMENTATION
INTRODUCTION
Combinational logic employs the use of two or more of the basic logic gates to form a
When logic gates are connected together to produce a specified output for certain more useful, complex function. For example, in the design of an automobile warning
specified combinations of input variables with no storage involved, the resulting circuit is buzzer, it uses combinational logic. The criterion for the activation of the warning buzzer
category of combinational logic. In combinational logic, the output level is at all times is as follows: the buzzer activates if the headlights are on and the driver’s door is
dependent on the combination of input levels. This chapter expands on the material opened, or if the key is in the ignition and the door is opened.
introduced in the earlier chapters, with coverage of the analysis, design and
troubleshooting of various combinational logic circuits. The logic function for the automobile warning buzzer is illustrated symbolically in figure
5.1. The figure illustrates a combination of logic functions that can be written as a
Boolean equation in the form
LEARNING OBJECTIVES
B=K and D or H and D
The objectives of this unit are to:
1. Introduce basic combinational logic
which can also be written as
2. Simplify Boolean algebra
3. Differentiate half adder, full adder and ripple carrier
B = KD + HD
4. Introduction encoder and decoder
5. Understand code converter
This equation can be stated as B is HIGH if K and D are HIGH or if H and D are HIGH.
6. Understand multiplexer and de-multiplexer.
K
LEARNING OUTCOMES Key in Ignition
After completing the unit, students should be able to: Door Opened D
1. Utilize Boolean algebra laws and rules for simplifying combinational logic circuits. H
2. Distinguish between half adder and full adder. Headlights on
3. Implement a basic binary encoder
4. Understand and explain the function of encoder, decoder and comparator D
Door Opened
5. Identify the function of multiplexer and de-multiplexer.
Figure 5.1: An example of the application of combinational logic – automobile
warning buzzer
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Closely looking at the system, this warning buzzer can also be activated whenever the Example 5.2 :
door is opened and either the key is in the ignition or the headlights are on. This is a
simplification method for Boolean algebra. Using common reasoning, reduce the logic function described in Example 5-1 to a
simpler form.
The new Boolean equation becomes B = D and ( K = H ) also written as B = D (K +H).
The new equation represents the same logic operation but is simplified implementation. Solution :
Because it requires only two logic gates as shown in figure 5.2.
The alarm is activated if it is after banking hours and if either the front door is opened or
Door Opened D the vault is opened (see below). The simpler equation is written as
Warning Buzzer
H
Headlights on A = H (F+ V)
Key in Ignition D H
After Hours
Warning Buzzer
F
Front Door Opened
Figure 5.2
Vault Door Opened V
Example 5.1 :
Figure 5.4
Write the Boolean logic function and draw the logic circuit that represent the following
function: A bank burglar alarm (A) is to activate if it is after banking hours (H) and the
front door (F) is opened or if it is after banking hours (H) and the vault door is opened
(V). 5.2 BASIC ADDER
Solution : Computer executes adding operation on two binary numbers only at a time. Every
number consist a few bits. Adding operation starts from LSB to MSB. In some cases,
A= HF +HV. The logic circuit is shown below ‘Carry’ is produced. There are 2 types of adder circuit
i. Half adder
H ii. Full adder
Key in Ignition
F 5.2.1 Half Adder
Front Door Opened
H
After Hours The half adder accepts two binary digits on its inputs and produces two binary digits on
its outputs, a sum bit and a carry bit. Half adder add 2 binary number and produce Sum
Vault Door Opened V (S) , Carry Out ,COUT. A half adder is represented by the logic symbol in Figure 5.5. The
Figure 5.3 truth table for 1-bit Half-Adder is shown in table 5.1 and the equivalent circuit is shown in
Figure 5.6.
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A B
A B
HA
COUT
CIRCUIT FA
CIRCUIT
COUT CIN
S
Figure 5.5 S
Figure 5.7
Table 5.1. Table 5.2
X Y Cout S A B CIN COUT S
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
A 1 0 1 1 0
S
1 1 0 1 0
B
C Cout
= A •B
1 1 1 1 1
COUT S= A⊕B
S = AB + AB
Boolean expression for COUT and sum, S
Figure 5.6
S = A ⊕ B ⊕ CIN and COUT = AB + B CIN +A CIN
5.2.2 Full Adder
A
Full-Adder is a circuit that adds two binary numbers with the existence of input carry. The
B S
Truth table for 1-bit Full-Adder is shown in Table 5.2 and the symbol for full adder is C
IN
illustrated in Figure 5.7. Figure 5.8 is the equivalent circuit for full adder.
C
OUT
Figure 5.8
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Two half-adders can be use as a full adder as illustrated in Figure 5.9 5.3 COMPARATOR
Comparator is a device that compares two digital quantities to determine the relationship
of those quantities. Comparison is made in terms of :
– Equal to ‘=’
– Less than ‘<’
– Greater than ‘>’
Table 5.3
Inputs Outputs
A B A<B A=B A >B
0 0 0 1 0
Figure 5.9 0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
5.2.3 Ripple Carry Adder
Ripple-carry adder is the simplest and most compact parallel adders. It requires as little
as four cells per bit and one layout has a carry delay of only one cell per bit. The
NAND/XOR is used in making full adders which in turn are used in creating parallel
adders. It start to perform addition from the least –significant digit/bit (LSB) and add pairs
a) logic symbol b) circuit
of digits progressing to the most-significant digit/bit (MSB). For each bit position it uses a
full adder circuit, connected as shown in Figure 5.10. Carries that are produced by the
Figure 5.11: For two 2-bit quantities
full adders propagate to the left.
Table 5.4
A3 B3 A2 B2 A1 B1 Inputs Outputs
An Bn A1 A0 B1 B0 A<B A=B A >B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
Cn-1 C3 C0
Cn
F-A
F-A C F-A C F-A 0 0 1 0 1 0 0
3 2 1 0 0 1 1 1 0 0
n 0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
S2 S1 1 0 0 0 0 0 1
Sn S3 1 0 0 1 0 0 1
1 0 1 0 0 1 0
Figure 5.10: The n-bit ripple carry adder
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
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5.4 MEDIUM-SCALE-INTEGRATION (MSI) LOGIC CIRCUIT
Digital systems obtain binary-coded data and information that are continuously being
A1 operated on in some manner. Some of the operations include:
A0 i. Decoding and Encoding
ii. Multiplexing
iii. Demultiplexing
B1
B0 iv. Code conversion
5.4.1 Decoders
A decoder is a logic circuit that accepts a set of inputs that represent a binary number
Figure 5.12: For two 1-bit quantities - Equal to ‘=’
and activates only the output that corresponds to that input number. A decoder looks at
its inputs, determines which number is present there, and activates the one output that
correspond to that number, all other outputs remain inactive. Decoders are widely used
in the memory system of a computer where they respond to the address code generated
by the central processor to activate a particular memory location.
Example: 3-line-to-8-line (or 1-of-8) Binary Decoder as shown in Figure 5.15.
Only one output is activated at one time, correspond to the input number. Active-HIGH
input and output.
Figure 5.13: For two n-bit quantities
Example 5.3:
Apply each of the following sets of binary numbers to the comparators inputs in Figure
and determine the output by following the logic levels through the circuits.
Figure 5.15
a) 00 and 11 Table 5.5: Truth table for 1-of-8 Binary Decoder
b) 11 and 10
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1
0 0 0 1 1
0 0 1 0 1
1 0 1 1 1
1 0 0 1
1
1 0 1 1
1
1 1 0 1
Figure 5.14 1 1 1 1
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Example of Boolean expression from Table 5.5 Example 5.4:
Y0 = ABC
Y1 = ABC Indicate the states of the 74138 ICs (refer figure 5.17) outputs for each of the following
sets of inputs:
1-of-8 Binary Decoder logic circuit is shown in Figure 5.16. i) E 3 = E2 = 1
E1 = 0
C = B =1
A=0
ii) E 3 = 1
E2 = E1 = 0
C=0
B = A =1
Solution :
(i) With E2 =1, the decoder is disabled and all of its outputs will be in their in active
HIGH state. This can be determined from the truth table or by following the input
levels through the circuit logic.
Figure 5.16
(ii) All of the enable inputs are activated, so the decoding portion is enabled. It will
decode the input code 0112=310 to activate output Y 3 . Thus, Y 3 will be low and
The 74138 Decoder (1-of-8 Decoder) and the enable input pin is illustrated in Figure
all other outputs will be high.
5.16.
E3 5.4.2 Encoder
Y0
E2
Y1
E1
Y2 Circuit that allows only one input to be activated, and produces an N-bit output code,
74LS138
Y3 depending on which input is activated. For example, as shown in figure below, the
Y4
Y5 Encoder has 10 inputs and 4-bit output. Input and output are ACTIVE HIGH as illustrated
A
B Y6 in figure 5.19.
C Y7
Figure 5.17: IC 74138 Decoder
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Figure 5.19: From the view of controlled switch
Figure 5.18
Figure 5.19 shows the logic circuitry for a two input multiplexer with data inputs I0 and
The truth table for Decimal-to-BCD encoder is shown in Table 5.6 SELECT input S.
Table 5.6: Decimal-to-BCD encoder The logic level applied to the S input determines which AND gate is enabled so that its
data input passes through the OR gate to output Z. The 2-input Multiplexer (2-to-1
MUX) is shown in figure 5.20. The Truth table for 2-to-1 MUX is shown in Table 5.7
Table 5.7
S I1 I0 Z
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
5.4.3 Multiplexer (Data Selector)
Multiplexer (MUX) also known as ‘data selector’ is a logic circuit that accepts several
digital data inputs and selects one of them at any given time to pass on to the output.
MUX has several data-input lines (I0, I1, … In-1) and only one output line (Z), n is the
number of data-input lines. It also has data-select inputs (S0, S1, … S(log2n)-1) which are
used to select which input line should be switched to the output line, log2n is the number Figure 5.20
of data-select inputs. Refer to Figure 5.19.
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Boolean Expression:
S1S0 Output S Output
(Z) Z = S1 S 0 I 0 + S1 S 0 I1 + S1 S 0 I 2 + S1S 0 I 3
(Z)
00 I0 0 I0
Logic circuit for 4 input MUX
01 I1 1 I1
10 I2
11 I3
Figure 5.21: Two input multiplexer
Boolean Expression:
Z = I0 S + I1S Figure 5.23
4-input Multiplexer (4-to-1 MUX) - The same basic idea used to form the four-input Design 8-input Multiplexer (8-to-1 MUX)
multiplexer shown in Figure 5.22 (symbol) and 5.22.These four inputs, which are
selectively transmitted to the output according to the four possible combinations of the Figure 5.24 shows the symbol of 8-input Multiplexer. This multiplexer has an enable
S1S0 select inputs. Each data input is gated with a different combination of select input input E and provides both the normal and the inverted outputs.
levels. I0 is gated with S1 S0 so that I0 will pass through its AND gate to output Z only • When E =0, the select inputs S2 S1S 0 will select one data input (from I0 through I7)
when S1=0 and S0=0. for passage to output Z.
• When E =1, the multiplexer is disabled so that Z= 0 regardless of the select input
code.
This operation is summarize in table 5.8.
Figure 5.22
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Figure 5.24
Table 5.8
S2 S1 S0 E Z Figure 5.26
0 0 0 1 I0
0 0 1 1 I1
5.4.4 Demultiplexer
0 1 0 1 I2
0 1 1 1 I3
Demultiplexer (DEMUX) reverses the MUX function. DEMUX is a device that selects one
1 0 0 1 I4
of the data-output lines to receive the digital information from the data-input line. It has
1 0 1 1 I5
only one data-input line (I0) and several data-output lines (Q0, Q1, Q2.....QN-1). Data-
1 1 0 1 I6
select input (S0 , S1 … Sn-1) is used to select which data-output line should be
1 1 1 1 I7
switched from the data-input line.
Two 8-Input MUX can be combine to produce 16-input MUX and 4-Input MUX can be
combine to produce 8-input MUX.
Design 16-input Multiplexer (16-to-1 MUX)
Figure 5.27
• 2-output Demultiplexer (1-to-2 DEMUX)
Figure 5.25
We can use 2-to-1 MUX to implement 4-to-1 MUX. 3 units of 2-to-1 MUX are required.
Figure 5.28
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S1S0 Q3 Q2 Q1 Q0
00 0 0 0 I0
01 0 0 I0 0
10 0 I0 0 0
11 I0 0 0 0
Simplified truth table
S Io Q1 Q0 • Design 8-output Demultiplexer (1-to-8 DEMUX) and Design 16-output
0 0 0 0 S Q1 Q0
Demultiplexer (1-to-16 DEMUX)
0 1 0 1 0 0 Io
1 0 0 0 1 Io 0
1 1 1 0
Q0 = SI0
Q1 = SI 0
• 4-output Demultiplexer (1-to-4 DEMUX)
Figure 5.30
S1S0 I0 Q3 Q2 Q1 Q0
0 0 0 0 0 0 0
We can use the following:
0 0 1 0 0 0 1
• 1-to-2 DEMUX to implement 1-to-4 DEMUX.
0 1 0 0 0 0 0
• 1-to-2 DEMUX to implement 1-to-8 DEMUX.
0 1 1 0 0 1 0
• 1-to-2 DEMUX to implement 1-to-16 DEMUX.
1 0 0 0 0 0 0
• 1-to-2 DEMUX and 1-to-4 DEMUX to implement 1-to-8 DEMUX.
1 0 1 0 1 0 0
• 1-to-4 DEMUX to implement 1-to-16 DEMUX.
1 1 0 0 0 0 0
1 1 1 1 0 0 0
Simplified truth table
Figure 5.29
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5.4.5 Code Converters 5.5 UNIT’s SUMMARIZED NOTES
A code converter is a logic circuit that changes data presented in one type of binary code In this unit we have studied that:
to another type of binary code. A partial list of some of the more common code converter
are: 1. Several logic gates can be connected together to form combinational logic.
i. BCD to 7-Segment 2. NAND and NOR gates are sometimes referred to as universal gates, because
ii. BCD to Binary they can be used to form any of the other gates.
iii. Binary to BCD 3. Half adder accepts two binary digits on its inputs and produces two binary digits
iv. Binary to Gray Code on its outputs, a sum bit and a carry bit.
v. Gray Code to Binary 4. Full adder accepts three inputs including an input carry and generates a sum
vi. ASCII to EBCDIC output and an output carry.
vii. EBCDIC to ASCII 5. The basic function of a comparator is to compare the magnitude of two binary
quantity to determine the relationship of those quantities.
Consider a BCD-to-Binary converter. For example 5710 is represented 6. The basic function of a decoder is to detect the presence of a specified
as 5 7 combination of bits on its inputs and to indicate the presence of the code by a
specified output level.
7. An encoder is a combinational logic circuit that essentially performs a reverse
0101 0111
decoder function.
-Binary representation for decimal 5710 is 1110012
The basic idea of a two-digit BCD –to-Binary converter is as shown below:
Figure 5.31
:
The input to the converter are the two four-bit code groups D0C0B0A0, representing the
100 or unit digit and D1C1B1A1 representating the 101 or tens digit of the decimal value.
The output of the converters is b6b5b4b3b2b1b0, the seven bits of the binary equivalent of
the same decimal value.
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