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2015 - M. Schwartz, O. Manickum - Programming Arduino With LabVIEW

This document describes a VHDL code for a safe box entity with the following ports and signals: - Ports for clock, row inputs, column outputs, reset, display output, and 7-segment output - Signals for present and next state, column select, row number, key value, and counter The code contains state machine logic to rotate through the column selection, read the row inputs, determine the key value, and display the output on 7-segment displays.

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90 views

2015 - M. Schwartz, O. Manickum - Programming Arduino With LabVIEW

This document describes a VHDL code for a safe box entity with the following ports and signals: - Ports for clock, row inputs, column outputs, reset, display output, and 7-segment output - Signals for present and next state, column select, row number, key value, and counter The code contains state machine logic to rotate through the column selection, read the row inputs, determine the key value, and display the output on 7-segment displays.

Uploaded by

Rene
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity caja_fuerte is
Port (
clk : in STD_LOGIC;
filas : in STD_LOGIC_VECTOR (3 downto 0);
columnas : out STD_LOGIC_VECTOR (3 downto 0);
reset : in STD_LOGIC;
display : out STD_LOGIC_VECTOR(7 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0; );

end caja_fuerte;

architecture caja_fuerte of caja_fuerte is

type estado is(reposo,inicio,cuenta,rotacion,DfilaCol,Dtecla,mostrar);


signal presente, futuro: estado;
signal scol : unsigned(3 downto 0);
signal scol4 : unsigned(3 downto 0);
signal nfila : unsigned(3 downto 0);
signal tecla : unsigned(3 downto 0);
signal multi : unsigned(7 downto 0);
signal contador: unsigned(9 downto 0);

constant U0L: unsigned(9 downt to 0) := to_unsigned(0,10);


constant U0: unsigned(3 downt to 0) := to_unsigned(0,4);
constant U1: unsigned(3 downt to 0) := to_unsigned(1,4);
constant U2: unsigned(3 downt to 0) := to_unsigned(2,4);
constant U3: unsigned(3 downt to 0) := to_unsigned(3,4);
constant U4: unsigned(3 downt to 0) := to_unsigned(4,4);
constant U5: unsigned(3 downt to 0) := to_unsigned(5,4);
constant U6: unsigned(3 downt to 0) := to_unsigned(6,4);
constant U7: unsigned(3 downt to 0) := to_unsigned(7,4);
constant U8: unsigned(3 downt to 0) := to_unsigned(8,4);
constant U9: unsigned(3 downt to 0) := to_unsigned(9,4);

begin

-- asignaciones de inicio
display <= "11111110";
col<=scol;
multi<= U4*nfila;

--registro de estado
process(clk,reset)
begin
if(reset='1') then
presente<=reposo;

elsif(clk'event and clk='1') then


presente<=futuro;
end if;
end process;

--Camino de datos
process(clk,presente,tecla,scol,fila)
begin

if(clk'event and clk='1') then

case presente is

when reposo=>
scol<='1111';
contador<= U0L;

when inicio=>
scol<="0111";

when cuenta=>
contador<= contador+1;

when rotacion=>
scol<= scol(2 downto 0) & scol(3);
contador<= U0L;

when DfilaCol=>
case fila is
when "0111"=> nfila <= U0;
when "1011"=> nfila <= U1;
when "1101"=> nfila <= U2;
when "1110"=> nfila <= U3;
when others=> nfila <= U0;
end case;

case scol is
when "1110"=> scol4 <= U0;
when "1101"=> scol4 <= U1;
when "1010"=> scol4 <= U2;
when "0111"=> scol4 <= U3;
when others=> scol4 <= U0;
end case;

when Dtecla=>
if fila(3)='0' then
tecla<=U0;
else
tecla<= sol4+multi(3 downto 0);
end if;

when mostrar=>
case tecla is

when U0= > seg <="00000011";--abcdefgp


when U1 => seg <="10011111";
when U2 => seg <="00100101";
when U3 => seg <="00001101";
when U4 => seg <="10011001";
when U5 => seg <="00001001";
when U6 => seg <="01000001";
when U7 => seg <="00011111";
when U8 => seg <="00000001";
when U9 => seg <="00001001";
when A => seg <="00010001";
when B => seg <="11000001";
when C => seg <="01100011";
when D => seg <="10000101";
when As => seg <="10011101";
when Gat=> seg <="00111001";
when others => seg <="00000011";
end case;
end case;

--logica del estado siguiente

process (presente,fila,contador) is
begin

case presente is

when reposo=>futuro<=inicio;

when inicio=>futuro<=cuenta;

when cuenta=>
if contador="111111111" then
futuro<= rotacion;
else
futuro<=cuenta;
end if;

when rotacion=>
if(fila="1111") then
futuro<=cuenta;
else
futuro<=DfilaCol;
end if;

when DfilaCol=>
futuro <= Dtecla;
when Dtecla=>
futuro <= mostrar;
when mostrar=>
futuro <= rotacion;
end case;
end process;
end caja_fuerte;

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