PORT DETAILS

DAC KEY BOARD

DC/STEPPER DIP SWITCH/ PORT PORT
EEPROM/RTC
MOTOR PORT PORT 1 P0.0 1 R0 P2.0
1 P0.0 1 S1 P2.0
2 P0.1 2 R1 P2.1
2 P0.1 2 S2 P2.1
3 P0.2 3 R2 P2.2
3 P0.2 3 S3 P2.2
4 P0.3 4 R3 P2.3
4 P0.3 4 S4 P2.3
5 P0.4 5 C0 P1.0
5 P0.4 5 S5 P2.4
6 P0.5 6 C1 P1.1
6 P0.5 6 S6 P2.5
7 P0.6 7 S7 P2.6 7 P0.6 7 C2 P1.2
8 P0.7 8 S8 P2.7 8 P0.7 8 C3 P1.3

LCD PORT 7 – SEGMENT PORT ADC PORT

1 P3.2 RS 1 P0.0 A 1 P1.0 WR
2 P3.3 R/W 2 P0.1 B 2 P1.1 RD
3 P3.4 EN 3 P0.2 C 3 P1.2 CS
4 P0.0 DAT 0 4 P0.3 D 4 P1.3 INTR
5 P0.1 DAT 1 5 P0.4 E 5 P2.0 DATA7
6 P0.2 DAT 2 6 P0.5 F 6 P2.1 DATA6
7 P0.3 DAT 3 7 P0.6 G 7 P2.2 DATA5
8 P0.4 DAT 4 8 DP 8 P2.3 DATA4
9 P0.5 DAT 5 9 P3.2 DIS-1 9 P2.4 DATA3
10 P0.6 DAT 6 10 P3.3 DIS-2 10 P2.5 DATA2
11 P0.7 DAT 7 11 P3.4 DIS-3 11 P2.6 DATA1
12 12 P3.5 DIS-4 12 P2.7 DATA0

SERIAL PORT
RXD P3.0
TXD P3.1
INT0 P3.2
INT1 P3.3
Features
• Compatible with MCS®51 Products
• 8K Bytes of In-System Reprogrammable Downloadable Flash Memory
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 2K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
• 4V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Three-level Program Memory Lock
•
•
256 x 8-bit Internal RAM
32 Programmable I/O Lines
8-bit
•
•
Three 16-bit Timer/Counters
Nine Interrupt Sources
Microcontroller
• Programmable UART Serial Channel
• SPI Serial Interface with 8K Bytes
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Flash
• Programmable Watchdog Timer
• Dual Data Pointer
• Power-off Flag
AT89S8252
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcontroller with 8K Not Recommended
bytes of downloadable Flash programmable and erasable read-only memory and 2K
bytes of EEPROM. The device is manufactured using Atmel’s high-density nonvolatile
for New Designs.
memory technology and is compatible with the industry-standard 80C51 instruction Use AT89S8253.
set and pinout. The on-chip downloadable Flash allows the program memory to be
reprogrammed In-System through an SPI serial interface or by a conventional nonvol-
atile memory programmer. By combining a versatile 8-bit CPU with downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcontroller, which
provides a highly-flexible and cost-effective solution to many embedded control
applications.
The AT89S8252 provides the following standard features: 8K bytes of downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog
timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt
architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition,
the AT89S8252 is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next external interrupt or hardware reset.
The downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless lock bits have been activated.

0401G–MICRO–3/06

1
Pin Configurations
TQFP
PDIP

P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.4 (SS)

P1.0 (T2)
(T2) P1.0 1 40 VCC
(T2 EX) P1.1 2 39 P0.0 (AD0)

VCC
P1.3
P1.2

NC
P1.2 3 38 P0.1 (AD1)
P1.3 4 37 P0.2 (AD2)

44
43
42
41
40
39
38
37
36
35
34
(SS) P1.4 5 36 P0.3 (AD3)
(MOSI) P1.5 6 35 P0.4 (AD4)
(MOSI) P1.5 1 33 P0.4 (AD4)
(MISO) P1.6 7 34 P0.5 (AD5)
(MISO) P1.6 2 32 P0.5 (AD5)
(SCK) P1.7 8 33 P0.6 (AD6)
(SCK) P1.7 3 31 P0.6 (AD6)
RST 9 32 P0.7 (AD7)
RST 4 30 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP
(RXD) P3.0 5 29 EA/VPP
(TXD) P3.1 11 30 ALE/PROG
NC 6 28 NC
(INT0) P3.2 12 29 PSEN
(TXD) P3.1 7 27 ALE/PROG
(INT1) P3.3 13 28 P2.7 (A15)
(INT0) P3.2 8 26 PSEN
(T0) P3.4 14 27 P2.6 (A14)
(INT1) P3.3 9 25 P2.7 (A15)
(T1) P3.5 15 26 P2.5 (A13)
(T0) P3.4 10 24 P2.6 (A14)
(WR) P3.6 16 25 P2.4 (A12)
(T1) P3.5 11 23 P2.5 (A13)
(RD) P3.7 17 24 P2.3 (A11)

12
13
14
15
16
17
18
19
20
21
22
XTAL2 18 23 P2.2 (A10)
XTAL1 19 22 P2.1 (A9)

(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
GND 20 21 P2.0 (A8)

PLCC
P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.4 (SS)

P1.0 (T2)

VCC
P1.3
P1.2

NC
6
5
4
3
2
1
44
43
42
41
40
(MOSI) P1.5 7 39 P0.4 (AD4)
(MISO) P1.6 8 38 P0.5 (AD5)
(SCK) P1.7 9 37 P0.6 (AD6)
RST 10 36 P0.7 (AD7)
(RXD) P3.0 11 35 EA/VPP
NC 12 34 NC
(TXD) P3.1 13 33 ALE/PROG
(INT0) P3.2 14 32 PSEN
(INT1) P3.3 15 31 P2.7 (A15)
(T0) P3.4 16 30 P2.6 (A14)
(T1) P3.5 17 29 P2.5 (A13)
18
19
20
21
22
23
24
25
26
27
28
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

Pin Description
VCC Supply voltage.

GND Ground.

Port 0 Port 0 is an 8-bit open drain bi-didirectional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code
bytes during program verification. External pull-ups are required during program
verification.

Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers
can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.

2 AT89S8252
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 AT89S8252

Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC
PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. PORT 0 PORT 2

EEPROM REGISTER RAM LATCH LATCH FLASH

PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING INSTRUCTION DUAL
AND REGISTER
CONTROL DPTR
EA / VPP
RST

WATCH PORT 3 PORT 1 SPI PROGRAM

DOG LATCH LATCH PORT LOGIC

OSC
PORT 3 DRIVERS PORT 1 DRIVERS

P3.0 - P3.7 P1.0 - P1.7

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0401G–MICRO–3/06
 Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be
the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input
(P1.1/T2EX), respectively.
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select,
data input/output and shift clock input/output pins as shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.4 SS (Slave port select input)
P1.5 MOSI (Master data output, slave data input pin for SPI channel)
P1.6 MISO (Master data input, slave data output pin for SPI channel)
P1.7 SCK (Master clock output, slave clock input pin for SPI channel)

Port 1 also receives the low-order address bytes during Flash programming and
verification.

Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers
can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are exter-
nally being pulled low will source current (IIL) because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During
accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits
the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash
programming and verification.

Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers
can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high
by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are exter-
nally being pulled low will source current (IIL) because of the pull-ups.
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89S8252, as shown
in the following table.

4 AT89S8252
0401G–MICRO–3/06
 AT89S8252

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0 (external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD (external data memory read strobe)

RST Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device.

ALE/PROG Address Latch Enable is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during
Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and
may be used for external timing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the
bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.

PSEN Program Store Enable is the read strobe to external program memory.
When the AT89S8252 is executing code from external program memory, PSEN is acti-
vated twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory.

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to
fetch code from external program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming when 12-volt pro-
gramming is selected.

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting oscillator amplifier.

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0401G–MICRO–3/06