Ordering number : ENA1059

Monolithic Linear IC
For TV
LA72730 Audio/Video Switch

Overview
The LA72730 is an Audio/Video Switch for TV.

Functions
• Audio : Possible to Change 4 Channel×2, ALC OUTPUT, 4dB Amplifier MONITOR OUTPUT
• Video : Possible to Change 4 Channel, 6dB Amplifier
• Control : I2C (Slave address : 92h)

Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VCC max Pin 8 7.0 V
Allowable power dissipation Pd max Ta ≤ 70°C 300 mW
Operating temperature Topr -20 to +70 °C
Storage temperature Tstg -55 to +150 °C

Recommended Operating Conditions at Ta = 25°C

Parameter Symbol Conditions Ratings Unit
Recommended operating voltage VCC Pin 8 5.0 V
Operating voltage range VCC op Pin 8 4.5 to 5.5 V

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
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Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.

52108 MS PC 20080514-S00004 No.A1059-1/8

 LA72730
Electrical Characteristics at Ta = 25°C, VDD = 5.0V
Ratings
Parameter Symbol Conditions Unit
min typ max
Current dissipation ICC VCC = 5V, No signal 15.2 18 20.8 mA
Audio block
Audio input DC voltage INa No signal pin 1, 2, 3, 4, 5, 6, 23, 24 DC voltage 2.2 2.4 2.6 V
Audio output DC voltage Oa No signal pin 19, 20 DC voltage 2.2 2.4 2.6 V
Audio channel bandwidth Fa Input : 1kHz/20kHz, -6dBV : Pin 19, 20 output -2 0 +2 dB
Audio voltage gain (Audio-out) Aa1 f = 1kHz, VIN = -6dBV, Pin 19, 20 output -0.3 0.0 +0.3 dB
Audio voltage gain (Monitor-out) Aa2 f = 1kHz, VIN = -6dBV, Pin 12, 16 output 3.5 4.0 4.5 dB
Audio input dynamic range Da1 f = 1kHz, THD = ≤1% -3.0 -1.0 dBV
(Audio-out) Pin 19, 20 output
Audio input dynamic range Da2 f = 1kHz, THD = ≤1% -5.0 -3.0 dBV
(Monitor-out) Pin 13, 16 output
Audio channel PSRR PSa VCC = 5V+1Vp-p, SINE WAVE (50Hz) 35 50 dB
Audio channel input impedance Ria 80 100 120 kΩ
Audio channel output impedance Roa 150 200 250 Ω
Audio channel crosstalk CTa f = 1kHz 65 80 dB
Audio channel S/N SNa Filter = DIN/AUDIO 70 85 dB
Audio channel THD THDa f = 1kHz, VIN = -6dBV 0.15 0.3 %
ALC Detect level-1 ALC1 -10.5 -9 -7.5 dBV
ALC Detect level-2 ALC2 -15.5 -14 -12.5 dBV
ALC Detect level-3 ALC3 -13.5 -12 -10.5 dBV
ALC Detect level-4 ALC4 -19.5 -18 -16.5 dBV
Video block
Video input DC voltage INv 1.44 1.6 1.76 V
Video output DC voltage Ov 1.26 1.4 1.54 V
Video channel bandwidth Fv -3dB frequency 10 MHz
Video signal voltage gain Av f = 500kHz, VIN = 1Vp-p 5.0 6.0 7.0 dB
Video input dynamic range Dv f = 100kHz, THD ≤ 1% 2.0 2.5 Vp-p
Video channel PSRR PSv VCC = 5V+1Vp-p, SINE WAVE (50Hz) 35 50 dB
Video channel input impedance Riv 8.0 10 12.0 kΩ
Video channel output impedance Rov 30 40 50 Ω
Video channel crosstalk CTv f = 3.58MHz, VIN = 1Vp-p 45 60 dB
Video channel noise SNv Bandwidth 10MHz 55 60 dB

Package Dimensions
unit : mm (typ)
3067B

21.0

24 13
7.62
6.4

1 12
0.25

0.9 0.95
3.3 3.9 max
(3.25)
0.51min

(0.71) 1.78 0.48

SANYO : DIP24S(300mil)

No.A1059-2/8
 LA72730
Block Diagram

LIN-1 LIN-TV
1 24
0.1µF 0.1µF

LIN-2 RIN-TV
2 23
0.1µF 0.1µF

LIN-3
REG +
3 22
0.1µF 47µF

RIN-1 VIN-TV
4 21 +
0.1µF 10µF

RIN-2 AUDIO L OUT

5 BUFF 20 +
0.1µF ALC 10µF

RIN-3 AUDIO R OUT

6 BUFF 19 +
0.1µF ALC 10µF

VIN-1 75Ω + VIDEO OUT

+ 7 6dB 18
10µF 220µF
75Ω
VCC
47µF
+ 8 DET 17 +

0.1µF 47µF
100µH ALC FILT

VCC 5V VIN-2
9 4dB 16 +
+
10µF 10µF
L Monitor out

GND
10 NC 15

VIN-3
SDA
+ 11 14
10µF MODE
SELECT

SCL
+ 12 4dB 13
10µF

R Monitor out

No.A1059-3/8
 LA72730
I2C Bit Pattarn
D8 D7 D6 D5 D4 D3 D2 D1 Condition

* 0 0 AV IN-TV
0 1 AV IN-1
1 0 AV IN-2
1 1 AV IN-3
* 0 Norma
1 Mute
0 0 ALC Level-1 (-9dBV)
0 1 ALC Level-2 (-14dBV)
* 1 0 ALC Level-3 (-12dBV)
1 1 ALC Level-4 (-18dBV)
* 0 ALC-ON
1 ALC-OFF
0 Prohibit
* 1 Fix
* 0 Fix
1 Prohibit
“*” : Shows initial condition.
Slave address : 92h (1001 0010)

LINE-OUT MONITOR
10 15

5 10

5
0
F
OF
OUTPUT – dBV

OUTPUT – dBV

0
–5 C-
AL
ALC-1 –5
– 10 R
ALC-3 – 10 NITO
– 15
ALC-2 MO
ALC-4 – 15

– 20
– 20

– 25 – 25

– 30 – 30
– 30 – 25 – 20 – 15 – 10 –5 0 – 30 – 25 – 20 – 15 – 10 –5 0
INPUT – dBV INPUT – dBV

No.A1059-4/8
 LA72730
Test Circuit

LIN-1 LIN-TV
1 24
0.1µF 0.1µF
620Ω 620Ω

LIN-2 RIN-TV
2 23
0.1µF 0.1µF
620Ω 620Ω

LIN-3
REG +
3 22
0.1µF 1µF
620Ω

RIN-1 VIN-TV
4 21
0.1µF 0.1µF
620Ω 75Ω

RIN-2
5 BUFF 20
0.1µF ALC
AUDIO L OUT
620Ω

RIN-3 AUDIO R OUT

6 BUFF 19
0.1µF ALC
620Ω

VIN-1 VIDEO OUT

7 6dB 18
0.1µF
75Ω
VCC

DET +
8 17
VCC5V + 47µF 1µF
ALC FILT
0.1µF
VIN-2 L Monitor out
9 4dB 16
0.1µF
75Ω

GND NC
10 15

VIN-3
SDA
11 14
0.1µF MODE
75Ω
SELECT

SCL
12 4dB 13

R Monitor out

No.A1059-5/8
 LA72730
Pin Functions
DC : voltage
Pin No. Pin Name Function Equivalent Circuit
AC : level
1 PIA_L1 Audio input DC : 2.4V
2 PIA_L2
3 PIA_L3
4 PIA_R1
5 PIA_R2
6 PIA_R3
50kΩ
23 PIA_RTV
50kΩ
24 PIA_LTV

7 PIV_1 Video input DC : 1.6V

9 PIV_2
11 PIV_3
21 PIV_TV

500Ω

8 GND
10 VCC
12 POMONITR Monitor output DC : 2.4V
16 POMONITL

200Ω

13 PISCL Serial clock input

1kΩ

14 PISDA Serial data input

1kΩ

17 POALCFIL ALC detect filter

2kΩ 150Ω

Continued on next page

No.A1059-6/8
 LA72730
Continued from preceding page.
DC : voltage
Pin No. Pin Name Function Equivalent Circuit
AC : level
18 POVIDEO Video output DC : 1.4V

19 POALCR Audio output DC : 2.4V

20 POALCL
200Ω

10kΩ

22 PCREG Reference voltage DC : 2.4V

10kΩ 500Ω
9.6kΩ

1kΩ

I2C BUS serial interface specification

(1) Data Transfer Manual
This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial
clock) and SDA (serial data).At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to
SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit),
and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes “H”, this IC pull down the
SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition,
thus the transfer comes to close.
*1 Defined by SDA fall down SCL during ‘H’ period.
*2 Defined by SDA rise up SCL during ‘H’ period.

(2) Transfer Data Format

After transfer start condition, transfers slave address (92h : 1001 0010 ) to SDA terminal, control data, then, stop
condition (See figure 1).
Slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, but this IC does not have READ
mode, so that this bit fix to “L”.
Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled
the transfer dates.
*3 It is called R/W bit.

Fig.1 DATA STRUCTURE

R/W
START Condition Slave Address ACK Control data ACK STOP condition
L

(3) Initialize
This IC is initialized for circuit protection. Initial condition is shown on bitmap.

No.A1059-7/8
 LA72730
Reference
Parameter Symbol min max unit
LOW level input voltage VIL -0.5 1.5 V

HIGH level input voltage VIH 2.5 5.5 V

LOW level output current IOL 3.0 mA
SCL clock frequency fSCL 0 100 kHz
Set-up time for a repeated START condition tSU : STA 4.7 µs
Hold time START condition. After this period, the first clock pulse is generated tHD : STA 4.0 µs
LOW period of the SCL clock tLOW 4.7 µs
Rise time of both SDA and SDL signals tR 0 1.0 µs
HIGH period of the SCL clock tHIGH 4.0 µs
Fall time of both SDA and SDL signals tF 0 1.0 µs
Data hold time tHD : DAT 0 µs
Data set-up time tSU : DAT 250 ns
Set-up time for STOP condition tSU : STO 4.0 µs
BUS free time between a STOP and START condition tBUF 4.7 µs

Definition of timing

tR t HI G H tF

S CL

t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F

S DA

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This catalog provides information as of May, 2008. Specifications and information herein are subject
to change without notice.

PS No.A1059-8/8