6A-4 (Invited)

Design Challenges of Low-Power and High-Speed Memory Interface in Advanced

CMOS Technology
Yohan Frans, Ralf Schmitt, Nhat Nguyen, Sunil Bhardwaj, Gary Bronner
Rambus Inc., 1050 Enterprise Way, Suite 700, Sunnyvale, CA 94089
[email protected]

Abstract is desirable to move most of the control circuits (e.g., voltage

Design requirements for low-power and high-speed and timing adjustments) to the ASIC PHY which is expected to
memory interfaces in mobile systems are discussed within the have tighter performance specifications. Such asymmetric
context of CMOS process scaling. Key challenges include design helps optimize the system power/performance budget.
process variations, low Vdd/Vth ratio, interconnect parasitics, Design Challenges in Advanced CMOS Process
and model accuracy of key process parameters. It is shown that A. Process Variations
careful system architecture along with appropriate circuit In order to meet specifications in the worst-case scenario,
techniques allow mobile memory interface to meet aggressive controller PHY circuits must cover wider global process
performance and power targets with conventional technology. variations, causing extra power consumption. Local variations
Future Mobile Memory Interface Requirements due to random device mismatch and layout-dependent
Future mobile systems will require increased memory variations such as Well Proximity Effect (WPE) and Length of
bandwidth while staying within existing power envelopes, Diffusion (LOD) introduce DCD in the clock buffers and
creating a need for significant power efficiency improvement non-linearity in the delay-control circuits. In order to minimize
in memory system. While new technologies such as local variations, foundries impose strict design rules which
direct-attach/TSV memories have emerged, discrete memory cause circuit area to grow (potentially causing power increase)
components remain attractive because they leverage existing and also change circuit design flow (pre-layout simulations are
technology and infrastructure. Discrete memories fit well into no longer accurate). Significant compute resources are
architectures that require capacity and performance scalability required to perform Monte-Carlo simulations along with
across a wide range of packaging options (PoP, C2C, MCP) global corners.
and systems. Utilizing existing infrastructure allows ease of B. Low Vdd/Vth Ratio
integration into existing manufacturing flows and supply Speed improvement in advanced CMOS process is obtained
chains, which in turn help to reduce costs. Even with these by shortening channel length and improving strain–induced
advantages, discrete memory components must increase mobility. Gate-overdrive voltage is getting smaller. As a result,
performance and improve power efficiency in order to meet although gate delay improves, delay sensitivity to supply noise
the needs of future mobile systems. Adoption of low pin count, does not (Figure 4), making it difficult to meet PSIJ
high per-pin data rate, low-swing signaling, and aggressive requirement in CMOS clock buffers.
power management (Figure 1) enables memory interfaces with C. Wire Capacitance and RC Delay
up to 4.3GB/s peak bandwidth in a x8 memory device [1] and Signal propagation delay is dominated by parasitic wire
17.2GB/s with 4 x8 memory devices housed in a 12x12mm2 capacitance since metal capacitance does not scale
PoP package, satisfying requirements of next-generation proportionally as gate capacitance. Ultra Low-K process helps
mobile systems. to reduce wire capacitance, but wire resistance of low-level
In high-speed memory interface design, signal and power metals is getting worse, causing higher wire RC delay. As a
integrity analysis is used to close voltage and timing budget at result, more buffers are needed to propagate signals which
the system level under high-volume manufacturing conditions further increase power consumption.
[2]. From this analysis, component-level specifications are D. Model Accuracy
derived for the controller PHY, channel, and DRAM. Due to Accuracy criteria for analog/mixed-signal design are often
relatively short channels in mobile systems, voltage and timing not met by foundry-generated SPICE models. For example,
parameters of the controller PHY and DRAM are dominant models are accurate for minimum channel length, but not for
and have to be accurately predicted and tightly controlled longer channel length devices which are commonly used in
(Figure 2). analog/mixed-signal circuits (Figure 5).
Low-swing signaling requires low-offset receivers. It also Thermal noise models, required for the design of low
depends on low noise on supply and reference voltages, a voltage-offset receivers and low phase-noise PLLs, are not
challenge especially during power mode transitions and modeled accurately or silicon calibrated (Figure 6).
simultaneous switching output (SSO) events. This requires low System-level simulation of power supply noise profile relies
supply impedance in the package and on-chip silicon, and a on accurate model of bypass capacitor, including bulk
careful optimization of mode transitions to control current resistivity. Inaccurate modeling of bulk resistivity impacts
amplitude and spectrum. simulation result of supply noise profile (Figure 7).
High per-pin data rate requires delay-control circuit to Circuit/System/Architecture Solutions
compensate for per-pin channel variations. It also requires A. Addressing Process Variation
circuit design with low timing errors in data and clock paths. To address global process variations, circuit solutions such
Major timing errors in mobile memory systems are random as process-dependent body-bias control [3] and system
clock jitter (RJ), duty cycle distortion (DCD), and power solutions such as process-dependent power supply are adopted.
supply induced jitter (PSIJ). Especially, PSIJ can have major Analog circuits that are sensitive to local variations are
impact to voltage and timing margin (Figure 3). calibrated digitally. For example, mismatch-induced
Because ASIC processes are faster than DRAM processes, it receiver/sampler offset can be corrected by setting its inputs to

110 978-4-86348-164-0 2011 Symposium on VLSI Technology Digest of Technical Papers

null and digitally adjusting the offset currents until the
resulting samples have equal number of 1s and 0s (Figure 8).
In order to compensate for VT drift, system solutions that
allow periodic calibration when the memory interface is idle
(e.g., during DRAM refresh) can be adopted.
B. Addressing Low Vdd/Vth Ratio
In order to reduce PSIJ while keeping leakage current under Figure 3: PSIJ impact on data eye diagram
control, low-Vth devices are selectively used in the design. 30 70
INV Supply Sensitivity (fs/mV)
INV Delay (ps)
These devices can be gated with larger-sized regular-Vth or 25 60

high-Vth devices to further reduce leakage. In some circuits, 20

50

differential current mode logic (CML) can be used instead of 15

40

CMOS. Power penalty from using CML is not too significant

30
40LP_DELAY 40LP_PSIJ
10
28LP_DELAY 20 28LP_PSIJ
when used in high-activity nodes such as clock buffers. 5 10

C. Addressing Wire Capacitance and RC Delay 0

FANOUT
0
FANOUT

Early design partitioning is done to ensure a majority of 1 2 3 4 5 1 2 3 4 5

high-speed paths are contained locally. High-speed global Figure 4: Inverter delay and delay sensitivity to supply
routing is done using top-level metal layers, requiring careful variation at two different process nodes.
co-design of power grid and global routing. nmos-gds (Id/Vd(sat)) w=0.5u l=0.5u T=25C

D. Addressing Model Inaccuracy

20.00
18.00

Inaccurate device models cannot be solved by designers. 16.00

14.00
Designers anticipate this by building extra margins into the 12.00 Measured

gds
10.00 Model
designs (at the expense of power), taping out test structures 8.00 Fitted_Model

early on fab shuttles, correlating simulation versus 6.00

4.00

measurement, and maintaining history of model fudge-factors. 2.00

0.00
Conclusion 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8

Future needs of mobile systems can be met with discrete vgs

memory components incorporating power-efficient and Figure 5: Long channel length model inaccuracy
high-speed memory interfaces. CMOS scaling will present -110
Noise Factor
Measured
additional challenges to the design of these interfaces. While Fitted

circuit, architecture, and system solutions exist to address -120

some of these challenges, interaction between design and Phase Noise

(dBc/Hz)

process technology remains ever more critical. -130

-140
Simulated
pause SYNC CK (Default Model)
φ (1.6GHz) -150 10log(Frequency)
pclkDRAM
8
2 PLL 6 6.5 7 7.5 8 8.5
3
Figure 6: Fitting noise factor to measured PLL phase noise
Half-rate clocks, 900 apart VDD-VSS
DQ (x8)
τ = 50ps
φ
CA (x3)
4 Supply Noise Model
(3.2 Gb/s)
8 16
VRM Board PKG Chip
8 VDD
8
16 Rbulk
Near ground, Transient
τ
-
4
+

low-swing Current τ = 100ps

φ signaling VSS
TIME
Controller PHY Channel DRAM
Figure 1: High-speed memory interface with low-swing Figure 7: Bulk-resistivity effect on supply noise profile
Digital Offset Trim
differential signaling DAC
offset
currents
Digital
bias Block

Inputs set to NULL bias Sampling clock

during calibration

Figure 8: Digitally-calibrated receiver circuit

References
[1] Leibowitz, et.al., Solid-State Circuits, IEEE Journal of,
vol. 45, no.4, pp. 889-898, April 2010.
Figure 2: Contributions to interface VT-budget [2] Beyene, et.al, IEEE Trans. Adv. Pkg. Tech., vol. 27, no. 1,
pp. 34-44, Feb. 2004.
[3] Tschanz, et.al., Digest of Technical Papers, ISSCC, vol. 2,
pp. 344-539, 2002.

2011 Symposium on VLSI Technology Digest of Technical Papers 111