Design of 8-bit Arithmetic And Logic Unit using Mach-

Zehnder Interferometer type logic gates

Abstract
Overview: In modern days,very large scale integration technologies plays a vital role in consumer products, space Commented [i1]: play
and defence applications. Hence, recent scientific researchers focused more on achieving low power, area and
delay. In all applications, the processing elements called as Arithmetic and Logic Unit (ALU) is a critical
component. The operations of the Arithmetic Logic Unit is directly depending upon on both adders and Commented [i2]: upon on - on could be removed
multipliers.Motivation:In normal ALU computation, the traditional Multi-Input Floating Gate based
reconfigurable logic, conventional CMOS and normal reversible gate based designs are utilized for these days.
Since, there is a problem that occur in terms of heat, power loss and transmission delay. Therefore, this research Commented [i3]: after delay, a comma can be introducted and
focused on providing low power arithmetic computations. Objective:The major objective of this research is to next sentence can be combined as the sentence is not complete
provide low power and delay in ALU computation. Next, the utilization of Look up Table is optimized. Commented [i4]: Change as "to optimize" for objective.
Methodology:In this research, the reversible logic gates are considered for constructing arithmetic and logic units
as existing module. Then, proposed design depends upon optical reversible logic gates with signed vedic
multiplier for reducing the partial products and its results are better than existing design. Result: The overall Commented [i5]: results could be removed here?
module is designed using Verilog Hardware Description Language and tested with the help of Xilinx 14.5. The
proposed method has the minimum delay of 24.266ns and the power as 2.78mW. It is noticed that the proposed Commented [i6]: What conditions?
method has improved by 2.06479% difference.

Keywords: Adders, Reversible logic gates, optical reversible gates, Vedic Multiplier.

reversible gates, constant inputs, the number of

I. INTRODUCTION garbage outputs and quantum Cost. Commented [i21]: cost or Cost?

In the five generation level of the computing This is the era of reversible computing, since Commented [i22]: vague. consider to rephrase the sentence.
era we are in Fifth generation, so that in the sub field one of the applications in reversible computing is
Commented [i7]: ?
of Integrated circuit is Very Large Scale Integration. optical computers. Now-a -days the research is going
The Main parameters of VLSI is Area, Power and on in this area. Optical reversible computing is one of Commented [i23]: rephrase
Delay. Currently we are using 0.18nm technology for the mfost promising fields for designing high speed
better applications. DRDO designed VIKRAM 1601 and low power consuming future computers. Commented [i8]: Expansion and reference to be included
Floating Point Processor only for Aeronautical Recently, many researches have been concentrated on
Applications. The Origin of ALU starts from 1968 chip level implementation of the optical circuits. Thus
where Fairchild designed the first Arithmetic Logic realizing an efficient adder is required for better
Unit in Integrated Circuit. While designing the ALU performance of an ALU and therefore the processor.
there are various challenges are faced by the engineer, Another important element in an ALU after adder is a Commented [i9]: remove "are"
such as high computational complexity, achieving multiplier.
low power then previous designs and transmission Commented [i10]: than
delay. The complexity leads to high cost and data loss The technology of reversible computing is
occurs due to heat dissipation. For eliminating heat frequently developed. In further, reversible Commented [i11]: include reference?
dissipation low power ALU is designed. computing on all the circuits is designed. Lala et al.,
Commented [i24]: ?
(2010) designed the adder circuits in reversible logic.
Here in major applications, reversible For decreasing the area and power [4]. Pan and Commented [i25]: Further
gatesare used to reduce the power consumption and Nalasani (2005) presented the logical reversibility Commented [i12]: ?
loss of data. Basically this type of gates are first [5]. The inputs and outputs of this type of gates can
Commented [i13]: reference
introduced in thermodynamic level.The basic be uniquely retrievable from each other. The
reversible computing technique was first proposed by information is secured and cannot erased. The Commented [i26]: remove . & for decreasing
Rolf William Landauer in 1963. In 1973, Bennet operation performed in this type of circuit is Commented [i14]: gates are
given the theory of computation in biotechnology backward so that it is only less power.Vedral et al.,
Commented [i15]: reference?
level which is the basement of reversible level (1996) represented an addition and modulo
[1].Later, Tommaso Toffoli and Edward Fredkin computations in research level [6]. In the field of Commented [i16]: Use reference instead?
invented the reversible gates in their name which was biotechnology itself the reversible gates are designed. Commented [i17]: space after period.
Toffoli Gate and Fredkin Gate. Pawel Kerntopf The major applications of reversible logic is low
studied the remaining gates which is Peres, Sayem power CMOS and Optical information processing, Commented [i27]: ?
respectively [2]. In 1985,Feynman given the solution DNA computing, quantum computation and Commented [i18]: space
that are faced byquantum physics which is based on nanotechnology. It is the n x n logic device which is
Commented [i19]: had given?
Toffoli, Fredkin and Bennet[3].In Reversible logic ‘n’ inputs and ‘n’ outputs.
there are many parameters such as number of Commented [i20]: space
 The major contributions of this research to Syamala and Tilak (2011) demonstrated the Commented [i28]: is to
design an advanced Arithmetic Logic Unit with less ALU concept with the help of reversible logic gates
complexity. It is mainly designed with the help of by using multiplexers and control signals.In this type Commented [i29]: what about power and delay requirements
Signed Vedic Multipliers and Carry Select adders. of ALU applications they had designed only four
The internal blocks of such adders and multipliers are basic arithmetic logical operations on two n-bit
framed with optical reversible gates constructed by operands. Some suggestion are carried out in terms Commented [i42]: vague
the Mach-Zehnder Interferometer (MZI) under the of the production of garbage outputs and constant
Semiconductor Optical Amplifiers (SOAs) strategy. inputs.Most of the logics utilizes the frequently used
for random logic for error detecting and correction. Commented [i43]: remove
Further, this paper is organized as follows. Yelekar and Chiwande (2011) also considered the
Section 2 reviews some critical events in arithmetic reversible gate to build more complicated circuits
and logical events and its demerits. Next, the existing such as sequential and combinational circuits. It
module with reversible logic gates are designed and designed the adder concept using reversible peres
simulated to verify the delay and power. Then, the gate and TSG gate. Mamun and Menville (2014) Commented [i44]: They designed or It designed?
proposed methodology is framed with the help of framed a ‘Selim Al Mamun’ (SAM) gate with the
optical reversible logic gates and the vedic multiplier performance metrics like quantum cost, delay and
units under section 3. The simulated results are garbage outputs.Mainly, the SAM gate is designed to
discussed under section 4. Finally, the research is manage the performance of memory elements in
summarized in the section 5. recent developments.

II. LITERATURE REVIEW Some reversible latches are presented over all
computation for improving the sequential circuits. In
Sun and Jiang (2010) identifies the problems any type of circuit, there is a need for low power Commented [i30]: identify or identified
that are occurred in conventional structures namely, consumption. Since, the sequential elements
Commented [i31]: that occured
complex structure, adder independent structure and consumes more power than combinational. The
tree structure and chain structure. David et al., (2005) process of combining the memory elements decides Commented [i32]: ,
described the complex structure with the combination the overall performance. Singh and Goel (2015) Commented [i45]: incomplete sentence
of arithmetic and logic operations in a single unit. In framed an adder and subtractor using reversible logic
such cases, various control signals are used to control gates. Since, lot of innovative reversible concepts are Commented [i33]: remove "are"
each activities, decides the complexity. Similarly, the publishing since, there is a limitation like
Commented [i34]: decide
Prakash and Saxena (2009) considered the adder combinational delay, transition delay, computation
independent structure separately for arithmetic time and power utilization. Nielsen and Chuang Commented [i46]: two since - rephrase
operations and an individual module performs logic (2000) described about the quantum error correction Commented [i47]: are limitations
operations, it provides huge complexity. Zhou and in all arithmetic operations. Thapliyal and
Commented [i35]: incomplete
Guo (2008) presented the tree structure that organizes Ranganathan (2010) represented a conservative logic
a set of functional components as a tree. Here, the in terms of various combinational structures. Commented [i36]: ?
operation performs like a chain for each
component/operation. Biswas et al., (2014) concentrated on quantum
computing with the help of various designs. Coarse-
The conventional ALU designs are framed grained architecture, on the other hand, is typically
with different styles namely, transistor level (Ryu et much larger, and may consist of ALUs and possibly
al., 1999),Feedback Switch Logic based ALU even a significant amount of storage. There is a need Commented [i37]: space
(Prakash and Saxena 2009),ALU using Novel 8T full for developing the reconfigurable architecture with
Commented [i38]: space
adder and Pass transistor logic based multiplexers various process. For processing such cases, the low
(Nehru et al., 2012), Clock gating based energy power architectures are considered with various
efficient ALU design (Pandey et al., 2013) etc. Up to multipliers and adder logics. The vedic multipliers are
now various researchers focussed on implementing considered for effective speed of computation. The
the ALU design. While combining various operations reversible circuits are considered for reducing the
some internal fault may occur. To identify and detect power dissipation with the information/bits loss as in Commented [i39]: vague
the fault, Veeravalli (2009) implemented the error- but in the case irreversible circuit limited to some
detection mechanisms for regulating the faults arrived errors. Power gating technique is incorporated in the Commented [i48]: revisit or rephrase
during computation. The internal Boolean unit architecture to reduces the power consumed by the
Commented [i49]: reduce
suggested to find the alternate solution to the overall ALU. Recently,
hardware units. Whenever, there is an error that occur swamynathanandbanumathipresenteda 32-bit ALU Commented [i40]: is to
during the active ALU processing, replacement is usingverilogHDL with the logical functions. The Commented [i50]: year? space to be provided.
carried out with the sparse ALU. Various fault design was implemented in Xilinx. The design of an
tolerance mechanisms are executed for managing the ALU and a Cache recollection for use in a high
redundancy and avoid unwanted mechanism. performance processor was examined. Reversible Commented [i41]: to avoid
logic vital in recent years because it has competency Commented [i51]: is vital
to reduce the powerdissipation which is main
Commented [i52]: space
requisite in low power design. ALU which are The optical implementation of an optical
designed utilizing non reversible logic gates consume reversible gate, which is shown in figure 2. It Commented [i57]: remove
more latency. contains 3 MZI basedSwitches, 4 Beam Splitters (BS)
Commented [i58]: whether figure or fig. to be used?
and 3 Beam Combiners(BC). From the figure 2, the
A review of various ALU design approaches in BC denotes the combination of optical beams while
computing system for various architectures are the beam splitter simply. Taraphdar et al., (2010) Commented [i59]: incomplete
considered to find the merits and de-merits of various coined out the optical reversible circuits for all basic
designs. Most of the researchers discussed above has gates. Likewise, this research is followed for Commented [i60]: ?
the same objective of minimizing the power designing the arithmetic and logical gates.
consumption of the adder, multiplier and memories. .
In adder designs some control input technique are Commented [i53]: techniques
degraded and creates complexity. To avoid such
complexity, various reversible logic gates are
considered with more transistors and possess high
power dissipation. The limitation of conventional
adders are fan out and high computation cost.
Similarly, multipliers also consume more power
because of high switching activity. To avoid all such
limitations, the enriched ALU is to be designed. Commented [i54]: all such?

III. RESEARCH METHODOLOGY

The following section provides the detail

Fig 2 Optical Reversible Gate I
description of traditional methodology and its
description. In recent days, the Mach-Zehnder Commented [i55]: two description in a sentence
3.1 Different Types of Reversible Gates
interferometer (MZI) based optical switch has
The arithmetic and logic unit designs are framed
attracted many researchers in the field of all optical
with the help of reversible logic gates to perform high
reversible logic. Hence, this optical gate was
speed, low power with minimum computation
constructed with 3 input and 3 output reversible gate
complexity. It is framed with the help of reversible
with mapping of inputs (A, B, C) to output as shown
gates namely, Feynman gate, Fredkin Gate and Peres
in the equation 3.1. Figure 1 indicates the Mach-
gate. Initially, the combination of proposed reversible
Zehnder Interferometer Logic Gate.
logics are carried out here as an overview. Finally, Commented [i61]: ?
the combination of all reversible gates are constructed
Commented [i62]: ?
and designed a low power ALU module.
Commented [i56]: diagram is it clear in print?
3.1.1 Feynman gate
In this gate A, B are the inputs and P, Q are
the outputs. This Feynman gate is motivated from the
Kotiyal et al., (2012). It is totally an optical Commented [i63]: from Kotiyal
illustration of the Feynman gate. The Feynman gate
(FG) is a 2 inputs and 2 output reversible gate. It is
Fig 1: Mach-Zehnder Interferometer Logic Gate represented in the equation 3.3.
P=A and Q=A⊕B (3.3)
P = AB + (A ⊕B) C (3.1) where A, B are the inputs and P, Q are the outputs,
respectively.
Q = A ⊕B, R = A (invB) + (A ⊕B) C (3.2)
This gate is also termed as Controlled-Not
From the equation 3.1 and 3.2, the fan out are gate(CNOT) when the input A=1 then its output Q
represented by P and Q. The working of the MZI can has the complement of B. It is normally implemented
be clarified as: with 2 MZI optical switch, 2beam combiner (BC) and
(i) When there is an approaching input sign at 2 beam splitter (BS) in all opticalreversible
port A and the control motion at port B, at that computing. The designed Feynman gate is shown in
point there is a light present at the yield bar the figure 3.
port B. Here, there is no light present at the
yield cross port,
(ii) Without control motion at input port B and
approaching sign at input port A then the fan
out of MZI are exchanged and brings about the
presence of light at the yield cross port and no
light at the bar port.
 Fig3: Feynman gate
3.1.2 Fredkin Gate
Fredkin gate (FRG) is called as controlled
permutation gate. Normally, Fredkin gate is a
universal gate for designing complex circuits to Fig 5: Peres Gate
minimize the fan out. Here, the FRG is designed and
implemented by other reversible components like BS, P=A (3.7)
BC and MZI units. As shown in the figure 4, the Q=A⨁B (3.8)
output of Fredkin Gate is the operation of multiplexer
R=AB ⨁ C (3.9)
in with the first input as a status line. Its input vector Commented [i64]: verify the sentence
3.2 Proposed ALU Design
has the hamming weight that is equal to hamming
weight of its output vector. Reversible 3*3 gate maps Commented [i65]: map
As shown in the figure 6, the proposed ALU is
inputs contains the variable A, B and C. the output
designed. It is specifically designed with the Commented [i69]: in figure
representation is listed in equation 3.4 to 3.6.
reversible gates. The description of each arithmetic Commented [i66]: The
block is explained below. Apart from that logical
P=A (3.4) blocks such as AND, OR, NAND, NOR, XOR and
Q=A'B+AC (3.5)
XNOR are similar to the past logics. The Commented [i70]: incomplete
R=AB+A'C (3.6)
modifications are carried out in adder, multiplier and
subtractor. Since, literature review stated that there is
a complexity in multiplier design. Hence, we
concentrated more on internal units of multiplier.
Further, some stages of adders are also constructed
with the help of modified peres gate and feynmen
gate logics. Table 1 indicates the overall computation
process with 15 stages of selection lines. Commented [i71]: stages or states?

Table 1: Truth table for proposed logic

S3 S2 S1 S0 OPERATION DESCRIPTION

0 0 0 0 RESULT=A+B HALF ADDER

Fig 4: Fredkin Gate 0 0 0 1 RESULT=A+B+CIN FULL ADDER
3.1.3 Peres Gate
The output of Peres gate is a combination of 0 0 1 0 RESULT=A-B SUBTRACTOR
both Feynman and Toffoli Gate. The combination of 0 0 1 1 RESULT=A*B MULTIPLIER
both logics simplifies the design and provide proper
0 1 0 0 RESULT=A+1 INCREMENTER
output similar to normal conventional Peres gate. It is
designed with normal X-or gate and Feynman gate 0 1 0 1 RESULT= A-1 DECREMENTER
for minimizing the quantum cost. For better
0 1 1 0 RESULT=A&B AND LOGIC
performance in speed and power we are designing Commented [i67]: power,
reversible gates using semiconductor Optical 0 1 1 1 RESULT=A|B OR LOGIC
amplifiers. With help of this amplifiers Mach- 1 0 0 0 RESULT= Inv A COMPLEMENT Commented [i68]: these
Zehnder Interferometer (MZI) is designed. The Peres
gate is represented with respect to the equations 3.7 to 1 0 0 1 RESULT=~(A&B) NAND LOGIC
3.9. 1 0 1 0 RESULT=~(A|B) NOR LOGIC

1 0 1 1 RESULT=A^B XOR LOGIC

1 1 0 0 RESULT=~(A^B) XNOR LOGIC

1 1 0 1 RESULT=SHIFT A BARREL SHIFT

1 1 1 0 COMPARE (A,B) COMPARATOR

 Since the ALU is selected according to the
selection inputs S3 S2 S1 and S0. The final output of Commented [i72]:
the ALU is determined by the set of multiplexers and
Commented [i73]: incomplete, combine next sentence
with the input selection lines. The function table for
the ALU is completely determined by the input
selection. Based on the combination of the output
pins are selected. Commented [i74]: rephrase

Half Adder
Full Adder
Subtraction
Multiplier
Figure 8: Adder design with optical full adder
Incremental
Decrement
Input [0:7]

AND logic
Output

OR logic
Complement
NAND logic
NOR logic
XOR Logic
XNOR Logic
Barrel Shifter
Comparator

Fig 6: Block Diagram of Arithmetic Logic Figure 9: Optical full adder design
Unit
3.2.2 Subtractor
3.2.1 Adder For subtraction, some conventional methods
The adder is one of the basic element in the uses addition of 2’s complement of subtrahend to
arthimetic computation. It decides the complexity of the minuend. In such case of operation, the
the whole system. The process of providing the low complexity increses to great extent. Hence, a Commented [i77]: spelling increases
power is a key motive, but still the reduction of adder reversible a comparator with countable X-OR
units are difficult. Hence, with the new idea of Commented [i78]: not correct
logic gates are used to limit the complexity. The
reversible logic a new adder is designed with binary comprator helps to minimize the computational Commented [i75]: is difficult
to excess converter and multiplier. Figure 7 shows the complexity and increses the way of obtaining the Commented [i79]: spelling
tradtional adder design and its internal block optical low power. Figure 10 provides the RTLview of
full adder is shown in the figure 8. Similarly, the Commented [i76]: spelling traditional
comparator and figure 11 proves that the
internal block of optical full adder is designed with subtractor framed with the comparator. This Commented [i80]: proves?
basic 2 beam combiner (BC) and 4 beam splitter (BS) operation intiates the operation through the
with 2 MZI component, which is shown in the figure selection bits S3, S2, S1, S0 as 0010.
9. This operation intiates the half adder operation
through the selection bits S3, S2, S1, S0 as 0000 and
for full adder the S3, S2, S1, S0 will be 0001.

Figure 7: Adder design with binary to excess Figure 10: RTL view of Comparator
converter and multiplexer
 Fig 12: Signed Vedic Multiplier

The RTL architecture of 2x2 bit Vedic

multiplier is similar to that of 2x2 bit conventional
Array Multiplier. It is implemented by four input
Figure 11: RTL view of Subtractor AND gates and two half-adders. The 4x4 bit Vedic
multiplier module is implemented using four 2x2 bit
The main advantage of this subtractor is to Vedic multiplier modules. Similarly 8X8 bit Vedic
process simultaneously and displays the artimetic multiplier is implemented using four 4x4 bit Vedic
Commented [i81]: spelling arithmetic
outcome exactly. The composition of various internal multiplier. Here, the input bit streams are considered
with the various (N-1) terms. Based onthe Most Commented [i82]: rephrase sentence
units decides the carry and borrow of previous stage.
The combination of multiplexer provides the Significant Bit (MSB), the multiplexer decides the
operation of unsigned or signed. Hence, for example
numerous support to XOR logic and provide exact Commented [i83]: provides
result. if N=8, then the operation turns towards the unsigned
multiplication and skips the 2’s complement stage if
3.2.3 Multiplier A7 bit is logic high and vice versa. The unsigned
Low-power multipliers are very important vedic multiplier contains carry select adder and 2*2
for reducing energy consumption of digital vedic multiplier.
processing systems. This research provides the
experience of applying an reversible version of our
logic gates and adders on multipliers for high-speed
and low-power purposes. Here, the computational
steps are reduced to filter out the useless power. It is
framed with the signed vedic multiplier and
combniation of adder for partial product generation Commented [i84]: combination spelling
unit with the help of multiplexer. Figure 12 displays
the flow of signed vedic multiplier. Vedic
Mathematics is the ancient system of mathematics
which has a unique technique of calculations based
on 16 Sutras. It is the design of high speed Vedic Commented [i85]: can be in Literature review part
Multiplier using the techniques of Ancient Indian Figure 13: Unsigned Vedic multiplier
Vedic Mathematics that have been modified to get
better performance. In Carry select adder, two adders are used
while one adder is for carry ‘0’ position and other is
for carry ‘1’ position. Here carry input is the signal
selected from the multiplexer and processed with the
AOI logic, which is represented in the figure Commented [i86]: abbreviation used before definition
14.AND-OR-Invert (AOI) logic are two-level
compound logic functions constructed from the dynamically varied due to the internal computation
combination of one or more AND gates followed by a process. Since, the carry flag is avoided to minimize
NOR gate. It is simpler and more efficient than the the delay and avoid over computation. The output
sum of the individual gates. The major outcome of verification is determined as shown in the figure 15.
this AOI implementation is to raise speed, reduce Similarly, the utilization of look up table is reduced to Commented [i87]: increase
power, and potentially ensure lower fabrication cost. great extent.

Table 2: Comparison Result

Parameters Existing Proposed

system system

Area (LUTs) 426 413

Power 2.838mW 2.78mW

Fig 14: Logical diagram of AOI Converter

The following steps are considered for signed vedic
multiplication.
Step1: Initially, the inputs and outputs are declared. Commented [i88]: justification ctrl+J
Fig 15: Simulated result for ALU design
Step2: Analyse the MSB bit of both inputs and
decides the signed and unsigned operation.
From the experimental results, it is noticed
Step 3: Now the negative numbers which are in 2’s that the low power objective is achieved. However,
complement form should convert to normal the computation process of an ALU design is framed
representation. Then, subtract the number with 4 bits similar to the previous modules. The process is
of combination in the case of 2x2 vedic multiplier completely simple and in unique style.
and 16 bit combination.
V. Conclusion
Step 4: After converting the numbers execute the
reversible unsigned vedic multiplier. This research focused on implementing the
reversible logical gates with the addition of low
Step 5: Output will be signed multiplication that powerMach-Zehnder Interferometer (MZI) technique.
provides the exact computation. The design adopts the low power reversible gates in
adder designs to simplify the internal computation.
IV. Experimental Results Similarly, the multiplier is designed by equipping the
vedic multiplier and reversible multiplexer to manage
The overall design modules are tested with the partial products through carry save adder. In
the help of Xilinx 14.5 integrated synthesis addition, the carry save adder is designed with the
environment. The internal logical blocks are designed AOI Convertermodule for limiting the power
with the Verilog module to minimize the coding overload. Similarly, the traditional methods has Commented [i91]: were
complexity. The internal blocks are minimized so that designed and synthesized to verify the functionality
the flow of the computation will be exactly reduced. of proposed reversible MZI based arithmetic and
Table 2 denotes the experimental results of existing logical unit. The vedic multiplier implementation
ALU with normal CMOS operation and which is with Carry save adder have an extremely high Commented [i92]: has
compared with the proposed reversible logics based flexibility on adjusting the data computation time.
ALU unit. The total power consumption of the This facilitates the robustness of ALU that can attain
2% power reduction in proposed ALU design when Commented [i89]: termed?
proposed module is termed as 2.78 mW. It is
Commented [i90]: is it maximum or under what configuration?
compared with the conventional designs.This design implementation on FPGA. In Energy Efficient
is completely verified by using Xilinx14.5 using Technologies for Sustainability (ICEETS),
verilog coding. 2013 International Conference on(pp. 93-97).
IEEE.
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