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Internal Architecture of 8086

The 8086 microprocessor has two main blocks: the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles all external bus operations like instruction fetching and memory access. It uses an instruction queue to prefetch bytes and implement pipelining. The EU decodes and executes instructions from the queue, performing operations and updating flags. Both units work asynchronously for overlapping fetch and execution, improving performance.

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111 views2 pages

Internal Architecture of 8086

The 8086 microprocessor has two main blocks: the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles all external bus operations like instruction fetching and memory access. It uses an instruction queue to prefetch bytes and implement pipelining. The EU decodes and executes instructions from the queue, performing operations and updating flags. Both units work asynchronously for overlapping fetch and execution, improving performance.

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pvlpavani
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Internal Architecture of 8086

•8086 has two blocks BIU and EU.


•The BIU performs all bus operations such as instruction fetching, reading and writing operands for
memory and calculating the addresses of the memory operands. The instruction bytes are transferred
to the instruction queue.
•EU executes instructions from the instruction system byte queue.
•Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution
mechanism which is called as Pipelining. This results in efficient use of the system bus and system
performance.
•BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
•EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.
BUS INTERFACR UNIT:
•It provides a full 16 bit bidirectional data bus and 20 bit address bus.
•The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
•Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.
•The BIU uses a mechanism known as an instruction stream queue to implement a pipeline
architecture.
•This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU
is not full, it has room for at least two more bytes and at the same time the EUis not requesting it to
read or write operands from memory, the BIU is free to look ahead in the program by prefetching the
next sequential instruction.

•These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches
two instruction bytes in a single memory cycle.
•After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to
the empty location nearest the output.
•The EU accesses the queue from the output end. It reads one instruction byte after the other from the
output of the queue. If the queue is full and the EU is not requesting access to operand in memory.
•These intervals of no bus activity, which may occur between bus cycles are known as Idle state.
•If the BIU is already in the process of fetching an instruction when the EU request it to read or write
operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before
initiating the operand read / write cycle.
•The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is
output on the address bus. This address is formed by adding an appended 16 bit segment address and
a 16 bit offset address.
•For example: The physical address of the next instruction to be fetched is formed by combining the
current contents of the code segment CS register and the current contents of the instruction pointer IP
register.
•The BIU is also responsible for generating bus control signals such as those for memory read or
write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
•The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles
to memory or I/O and perform the operation specified by the instruction on the operands.
•During the execution of the instruction, the EU tests the status and control flags and updates them
based on the results of executing the instruction.
•If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of
the queue.
•When the EU executes a branch or jump instruction, it transfers control to a location corresponding
to another set of sequential instructions.
•Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions
from this new location to refill the queue.
Module 1 and learning unit 4:
Signal Description of 8086•The Microprocessor 8086 is a 16-bit CPU available in different clock
rates and packaged in a 40 pin CERDIP or plastic package.
•The 8086 operates in single processor or multiprocessor configuration to achieve high performance.
The pins serve a particular function in minimum mode (single processor mode) and other function in
maximum mode configuration (multiprocessor mode ).
•The 8086 signals can be categorised in three groups. The first are the signal having common
functions in minimum as well as maximum mode.
•The second are the signals which have special functions for minimum mode and third are the signals
having special functions for maximum mode.

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