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Verilog Assignment Question

This document contains 20 questions about various Verilog concepts including: 1. The difference between blocking and non-blocking assignments when coding sequential logic. 2. The purpose of using #1 when coding flip-flops and when it should/should not be used. 3. The difference between tasks and functions in Verilog and when each would be used. 4. Whether it is possible to develop a flip-flop model using Verilog's specify statements and when specify statements would be used/their advantage. 5. How to handle tri-state logic in Verilog including what primitives support it and how to model different drive strengths.

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CLARITY UDT
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556 views

Verilog Assignment Question

This document contains 20 questions about various Verilog concepts including: 1. The difference between blocking and non-blocking assignments when coding sequential logic. 2. The purpose of using #1 when coding flip-flops and when it should/should not be used. 3. The difference between tasks and functions in Verilog and when each would be used. 4. Whether it is possible to develop a flip-flop model using Verilog's specify statements and when specify statements would be used/their advantage. 5. How to handle tri-state logic in Verilog including what primitives support it and how to model different drive strengths.

Uploaded by

CLARITY UDT
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1.

When would you use blocking vs non-blocking assignments when coding


sequential logic?

2. A lot of designers like to use a #1 when coding flip-flops (sequential logic).


What purpose does it serve? Why should you use #1 or not?

3. What is the difference between at task and a function? When would use one vs
the other?

4. Can you develop a flip flop model using Verilog's specify statements? When
would you use Verilog's specify statement? What advantage does it have?

5. How does one handle tri-state logic? What Verilog primitives support it? How
does one model various levels of drive strength?

6. When would you use casex vs a casez statement?


7. When using one of the case, casex, casez, variation, when would you use a
parallel case full_case directive? What does it do?
8. Should your Verilog case statement always include a "default" case? If yes,
why? If not, why not?

9. Suppose a part of your logic has 50 instances of a module. Do you cut and paste
it or generate the logic? If you are going to generate it, what tools do you use?

10. When running gate-level simulation, the output of a block is generating an "X".
How do you debug it? What could be causing the "X"?
11.write a verilog code to swap with and without temp variable.

12 what is the difference between #3 a= b and a =#b.

13. Given the following Verilog code, what value of "a" is displayed?

always @(clk) begin


a = 0;
a <= 1;
$display(a);
end
14. What is the difference between:

c = foo ? a : b;
and
if (foo) c = a;
else c = b;

15. What does `timescale 1 ns/ 1 ps signify in a verilog code?

16 Write a verilog code for 3x1 MUX

17. Write a verilog code 2:4 DECODER using 2:1MUX ?

18. Write a verilog code full adder using half adder

19. Write a verilog code for 4x1 mux using 2x1 mux

20. Write a verilog code SIPO using DFF

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